25a26
> mmap_using_noreserve=false
193a195
> sys=system
211d212
< port=system.cpu.toL2Bus.slave[9]
228c229
< port=system.cpu.toL2Bus.slave[7]
---
> port=system.cpu.toL2Bus.slave[5]
256a258
> pmu=Null
263a266
> sys=system
281d283
< port=system.cpu.toL2Bus.slave[8]
298c300
< port=system.cpu.toL2Bus.slave[6]
---
> port=system.cpu.toL2Bus.slave[4]
309a312
> demand_mshr_reserve=1
343a347
> sys=system
361d364
< port=system.cpu.toL2Bus.slave[5]
692a696
> demand_mshr_reserve=1
752a757
> pmu=Null
759a765
> sys=system
777d782
< port=system.cpu.toL2Bus.slave[4]
801a807
> demand_mshr_reserve=1
835c841,843
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
836a845
> snoop_response_latency=1
841c850
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
850a860
> drivers=
858a869
> kvmInSE=false
888c899,901
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
889a903
> snoop_response_latency=4
892c906
< width=8
---
> width=16
923c937
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
931a946
> device_size=536870912