Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

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config.ini (9348:44d31345e360)	config.ini (9449:56610ab73040)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775
17mem_mode=atomic	17mem_mode=timing 18mem_ranges=
18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU	19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU
33children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload	34children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=system.cpu.checker 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8	35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44activity=0 45backComSize=5 46cachePorts=200 47checker=system.cpu.checker 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8
59defer_registration=false
60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts	60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts
	81isa=system.cpu.isa
81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000	82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000
	119switched_out=false
118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.checker] 128type=O3Checker	120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.checker] 130type=O3Checker
129children=dtb itb tracer	131children=dtb isa itb tracer
130checker=Null 131clock=500 132cpu_id=0	132checker=Null 133clock=500 134cpu_id=0
133defer_registration=false
134do_checkpoint_insts=true 135do_quiesce=true 136do_statistics_insts=true 137dtb=system.cpu.checker.dtb 138exitOnError=false 139function_trace=false 140function_trace_start=0 141interrupts=Null	135do_checkpoint_insts=true 136do_quiesce=true 137do_statistics_insts=true 138dtb=system.cpu.checker.dtb 139exitOnError=false 140function_trace=false 141function_trace_start=0 142interrupts=Null
	143isa=system.cpu.checker.isa
142itb=system.cpu.checker.itb 143max_insts_all_threads=0 144max_insts_any_thread=0 145max_loads_all_threads=0 146max_loads_any_thread=0 147numThreads=1 148profile=0 149progress_interval=0	144itb=system.cpu.checker.itb 145max_insts_all_threads=0 146max_insts_any_thread=0 147max_loads_all_threads=0 148max_loads_any_thread=0 149numThreads=1 150profile=0 151progress_interval=0
	152switched_out=false
150system=system 151tracer=system.cpu.checker.tracer 152updateOnError=true 153warnOnlyOnLoadError=true 154workload=system.cpu.workload 155 156[system.cpu.checker.dtb] 157type=ArmTLB 158children=walker 159size=64 160walker=system.cpu.checker.dtb.walker 161 162[system.cpu.checker.dtb.walker] 163type=ArmTableWalker 164clock=500 165num_squash_per_cycle=2 166sys=system 167port=system.cpu.toL2Bus.slave[5] 168	153system=system 154tracer=system.cpu.checker.tracer 155updateOnError=true 156warnOnlyOnLoadError=true 157workload=system.cpu.workload 158 159[system.cpu.checker.dtb] 160type=ArmTLB 161children=walker 162size=64 163walker=system.cpu.checker.dtb.walker 164 165[system.cpu.checker.dtb.walker] 166type=ArmTableWalker 167clock=500 168num_squash_per_cycle=2 169sys=system 170port=system.cpu.toL2Bus.slave[5] 171
	172[system.cpu.checker.isa] 173type=ArmISA 174fpsid=1090793632 175id_isar0=34607377 176id_isar1=34677009 177id_isar2=555950401 178id_isar3=17899825 179id_isar4=268501314 180id_isar5=0 181id_mmfr0=3 182id_mmfr1=0 183id_mmfr2=19070976 184id_mmfr3=4027589137 185id_pfr0=49 186id_pfr1=1 187midr=890224640 188
169[system.cpu.checker.itb] 170type=ArmTLB 171children=walker 172size=64 173walker=system.cpu.checker.itb.walker 174 175[system.cpu.checker.itb.walker] 176type=ArmTableWalker 177clock=500 178num_squash_per_cycle=2 179sys=system 180port=system.cpu.toL2Bus.slave[4] 181 182[system.cpu.checker.tracer] 183type=ExeTracer 184 185[system.cpu.dcache] 186type=BaseCache 187addr_ranges=0:18446744073709551615 188assoc=2 189block_size=64 190clock=500 191forward_snoops=true	189[system.cpu.checker.itb] 190type=ArmTLB 191children=walker 192size=64 193walker=system.cpu.checker.itb.walker 194 195[system.cpu.checker.itb.walker] 196type=ArmTableWalker 197clock=500 198num_squash_per_cycle=2 199sys=system 200port=system.cpu.toL2Bus.slave[4] 201 202[system.cpu.checker.tracer] 203type=ExeTracer 204 205[system.cpu.dcache] 206type=BaseCache 207addr_ranges=0:18446744073709551615 208assoc=2 209block_size=64 210clock=500 211forward_snoops=true
192hash_delay=1
193hit_latency=2 194is_top_level=true 195max_miss_count=0 196mshrs=4 197prefetch_on_access=false 198prefetcher=Null	212hit_latency=2 213is_top_level=true 214max_miss_count=0 215mshrs=4 216prefetch_on_access=false 217prefetcher=Null
199prioritizeRequests=false 200repl=Null
201response_latency=2 202size=262144	218response_latency=2 219size=262144
203subblock_size=0
204system=system 205tgts_per_mshr=20	220system=system 221tgts_per_mshr=20
206trace_addr=0
207two_queue=false 208write_buffers=8 209cpu_side=system.cpu.dcache_port 210mem_side=system.cpu.toL2Bus.slave[1] 211 212[system.cpu.dtb] 213type=ArmTLB 214children=walker 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker 220clock=500 221num_squash_per_cycle=2 222sys=system 223port=system.cpu.toL2Bus.slave[3] 224 225[system.cpu.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 229 230[system.cpu.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234opList=system.cpu.fuPool.FUList0.opList 235 236[system.cpu.fuPool.FUList0.opList] 237type=OpDesc 238issueLat=1 239opClass=IntAlu 240opLat=1 241 242[system.cpu.fuPool.FUList1] 243type=FUDesc 244children=opList0 opList1 245count=2 246opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 247 248[system.cpu.fuPool.FUList1.opList0] 249type=OpDesc 250issueLat=1 251opClass=IntMult 252opLat=3 253 254[system.cpu.fuPool.FUList1.opList1] 255type=OpDesc 256issueLat=19 257opClass=IntDiv 258opLat=20 259 260[system.cpu.fuPool.FUList2] 261type=FUDesc 262children=opList0 opList1 opList2 263count=4 264opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 265 266[system.cpu.fuPool.FUList2.opList0] 267type=OpDesc 268issueLat=1 269opClass=FloatAdd 270opLat=2 271 272[system.cpu.fuPool.FUList2.opList1] 273type=OpDesc 274issueLat=1 275opClass=FloatCmp 276opLat=2 277 278[system.cpu.fuPool.FUList2.opList2] 279type=OpDesc 280issueLat=1 281opClass=FloatCvt 282opLat=2 283 284[system.cpu.fuPool.FUList3] 285type=FUDesc 286children=opList0 opList1 opList2 287count=2 288opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 289 290[system.cpu.fuPool.FUList3.opList0] 291type=OpDesc 292issueLat=1 293opClass=FloatMult 294opLat=4 295 296[system.cpu.fuPool.FUList3.opList1] 297type=OpDesc 298issueLat=12 299opClass=FloatDiv 300opLat=12 301 302[system.cpu.fuPool.FUList3.opList2] 303type=OpDesc 304issueLat=24 305opClass=FloatSqrt 306opLat=24 307 308[system.cpu.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312opList=system.cpu.fuPool.FUList4.opList 313 314[system.cpu.fuPool.FUList4.opList] 315type=OpDesc 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc 328issueLat=1 329opClass=SimdAdd 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList01] 333type=OpDesc 334issueLat=1 335opClass=SimdAddAcc 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList02] 339type=OpDesc 340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList03] 345type=OpDesc 346issueLat=1 347opClass=SimdCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList04] 351type=OpDesc 352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList05] 357type=OpDesc 358issueLat=1 359opClass=SimdMisc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList06] 363type=OpDesc 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList07] 369type=OpDesc 370issueLat=1 371opClass=SimdMultAcc 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList08] 375type=OpDesc 376issueLat=1 377opClass=SimdShift 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList09] 381type=OpDesc 382issueLat=1 383opClass=SimdShiftAcc 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList10] 387type=OpDesc 388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList11] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatAdd 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList12] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList14] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatMisc 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList17] 429type=OpDesc 430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList18] 435type=OpDesc 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList19] 441type=OpDesc 442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 450opList=system.cpu.fuPool.FUList6.opList 451 452[system.cpu.fuPool.FUList6.opList] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu.fuPool.FUList7] 459type=FUDesc 460children=opList0 opList1 461count=4 462opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 463 464[system.cpu.fuPool.FUList7.opList0] 465type=OpDesc 466issueLat=1 467opClass=MemRead 468opLat=1 469 470[system.cpu.fuPool.FUList7.opList1] 471type=OpDesc 472issueLat=1 473opClass=MemWrite 474opLat=1 475 476[system.cpu.fuPool.FUList8] 477type=FUDesc 478children=opList 479count=1 480opList=system.cpu.fuPool.FUList8.opList 481 482[system.cpu.fuPool.FUList8.opList] 483type=OpDesc 484issueLat=3 485opClass=IprAccess 486opLat=3 487 488[system.cpu.icache] 489type=BaseCache 490addr_ranges=0:18446744073709551615 491assoc=2 492block_size=64 493clock=500 494forward_snoops=true	222two_queue=false 223write_buffers=8 224cpu_side=system.cpu.dcache_port 225mem_side=system.cpu.toL2Bus.slave[1] 226 227[system.cpu.dtb] 228type=ArmTLB 229children=walker 230size=64 231walker=system.cpu.dtb.walker 232 233[system.cpu.dtb.walker] 234type=ArmTableWalker 235clock=500 236num_squash_per_cycle=2 237sys=system 238port=system.cpu.toL2Bus.slave[3] 239 240[system.cpu.fuPool] 241type=FUPool 242children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 243FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 244 245[system.cpu.fuPool.FUList0] 246type=FUDesc 247children=opList 248count=6 249opList=system.cpu.fuPool.FUList0.opList 250 251[system.cpu.fuPool.FUList0.opList] 252type=OpDesc 253issueLat=1 254opClass=IntAlu 255opLat=1 256 257[system.cpu.fuPool.FUList1] 258type=FUDesc 259children=opList0 opList1 260count=2 261opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 262 263[system.cpu.fuPool.FUList1.opList0] 264type=OpDesc 265issueLat=1 266opClass=IntMult 267opLat=3 268 269[system.cpu.fuPool.FUList1.opList1] 270type=OpDesc 271issueLat=19 272opClass=IntDiv 273opLat=20 274 275[system.cpu.fuPool.FUList2] 276type=FUDesc 277children=opList0 opList1 opList2 278count=4 279opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 280 281[system.cpu.fuPool.FUList2.opList0] 282type=OpDesc 283issueLat=1 284opClass=FloatAdd 285opLat=2 286 287[system.cpu.fuPool.FUList2.opList1] 288type=OpDesc 289issueLat=1 290opClass=FloatCmp 291opLat=2 292 293[system.cpu.fuPool.FUList2.opList2] 294type=OpDesc 295issueLat=1 296opClass=FloatCvt 297opLat=2 298 299[system.cpu.fuPool.FUList3] 300type=FUDesc 301children=opList0 opList1 opList2 302count=2 303opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 304 305[system.cpu.fuPool.FUList3.opList0] 306type=OpDesc 307issueLat=1 308opClass=FloatMult 309opLat=4 310 311[system.cpu.fuPool.FUList3.opList1] 312type=OpDesc 313issueLat=12 314opClass=FloatDiv 315opLat=12 316 317[system.cpu.fuPool.FUList3.opList2] 318type=OpDesc 319issueLat=24 320opClass=FloatSqrt 321opLat=24 322 323[system.cpu.fuPool.FUList4] 324type=FUDesc 325children=opList 326count=0 327opList=system.cpu.fuPool.FUList4.opList 328 329[system.cpu.fuPool.FUList4.opList] 330type=OpDesc 331issueLat=1 332opClass=MemRead 333opLat=1 334 335[system.cpu.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 340 341[system.cpu.fuPool.FUList5.opList00] 342type=OpDesc 343issueLat=1 344opClass=SimdAdd 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList01] 348type=OpDesc 349issueLat=1 350opClass=SimdAddAcc 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList02] 354type=OpDesc 355issueLat=1 356opClass=SimdAlu 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList03] 360type=OpDesc 361issueLat=1 362opClass=SimdCmp 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList04] 366type=OpDesc 367issueLat=1 368opClass=SimdCvt 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList05] 372type=OpDesc 373issueLat=1 374opClass=SimdMisc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList06] 378type=OpDesc 379issueLat=1 380opClass=SimdMult 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList07] 384type=OpDesc 385issueLat=1 386opClass=SimdMultAcc 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList08] 390type=OpDesc 391issueLat=1 392opClass=SimdShift 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList09] 396type=OpDesc 397issueLat=1 398opClass=SimdShiftAcc 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList10] 402type=OpDesc 403issueLat=1 404opClass=SimdSqrt 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList11] 408type=OpDesc 409issueLat=1 410opClass=SimdFloatAdd 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList12] 414type=OpDesc 415issueLat=1 416opClass=SimdFloatAlu 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList13] 420type=OpDesc 421issueLat=1 422opClass=SimdFloatCmp 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList14] 426type=OpDesc 427issueLat=1 428opClass=SimdFloatCvt 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList15] 432type=OpDesc 433issueLat=1 434opClass=SimdFloatDiv 435opLat=1 436 437[system.cpu.fuPool.FUList5.opList16] 438type=OpDesc 439issueLat=1 440opClass=SimdFloatMisc 441opLat=1 442 443[system.cpu.fuPool.FUList5.opList17] 444type=OpDesc 445issueLat=1 446opClass=SimdFloatMult 447opLat=1 448 449[system.cpu.fuPool.FUList5.opList18] 450type=OpDesc 451issueLat=1 452opClass=SimdFloatMultAcc 453opLat=1 454 455[system.cpu.fuPool.FUList5.opList19] 456type=OpDesc 457issueLat=1 458opClass=SimdFloatSqrt 459opLat=1 460 461[system.cpu.fuPool.FUList6] 462type=FUDesc 463children=opList 464count=0 465opList=system.cpu.fuPool.FUList6.opList 466 467[system.cpu.fuPool.FUList6.opList] 468type=OpDesc 469issueLat=1 470opClass=MemWrite 471opLat=1 472 473[system.cpu.fuPool.FUList7] 474type=FUDesc 475children=opList0 opList1 476count=4 477opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 478 479[system.cpu.fuPool.FUList7.opList0] 480type=OpDesc 481issueLat=1 482opClass=MemRead 483opLat=1 484 485[system.cpu.fuPool.FUList7.opList1] 486type=OpDesc 487issueLat=1 488opClass=MemWrite 489opLat=1 490 491[system.cpu.fuPool.FUList8] 492type=FUDesc 493children=opList 494count=1 495opList=system.cpu.fuPool.FUList8.opList 496 497[system.cpu.fuPool.FUList8.opList] 498type=OpDesc 499issueLat=3 500opClass=IprAccess 501opLat=3 502 503[system.cpu.icache] 504type=BaseCache 505addr_ranges=0:18446744073709551615 506assoc=2 507block_size=64 508clock=500 509forward_snoops=true
495hash_delay=1
496hit_latency=2 497is_top_level=true 498max_miss_count=0 499mshrs=4 500prefetch_on_access=false 501prefetcher=Null	510hit_latency=2 511is_top_level=true 512max_miss_count=0 513mshrs=4 514prefetch_on_access=false 515prefetcher=Null
502prioritizeRequests=false 503repl=Null
504response_latency=2 505size=131072	516response_latency=2 517size=131072
506subblock_size=0
507system=system 508tgts_per_mshr=20	518system=system 519tgts_per_mshr=20
509trace_addr=0
510two_queue=false 511write_buffers=8 512cpu_side=system.cpu.icache_port 513mem_side=system.cpu.toL2Bus.slave[0] 514 515[system.cpu.interrupts] 516type=ArmInterrupts 517	520two_queue=false 521write_buffers=8 522cpu_side=system.cpu.icache_port 523mem_side=system.cpu.toL2Bus.slave[0] 524 525[system.cpu.interrupts] 526type=ArmInterrupts 527
	528[system.cpu.isa] 529type=ArmISA 530fpsid=1090793632 531id_isar0=34607377 532id_isar1=34677009 533id_isar2=555950401 534id_isar3=17899825 535id_isar4=268501314 536id_isar5=0 537id_mmfr0=3 538id_mmfr1=0 539id_mmfr2=19070976 540id_mmfr3=4027589137 541id_pfr0=49 542id_pfr1=1 543midr=890224640 544
518[system.cpu.itb] 519type=ArmTLB 520children=walker 521size=64 522walker=system.cpu.itb.walker 523 524[system.cpu.itb.walker] 525type=ArmTableWalker 526clock=500 527num_squash_per_cycle=2 528sys=system 529port=system.cpu.toL2Bus.slave[2] 530 531[system.cpu.l2cache] 532type=BaseCache 533addr_ranges=0:18446744073709551615 534assoc=8 535block_size=64 536clock=500 537forward_snoops=true	545[system.cpu.itb] 546type=ArmTLB 547children=walker 548size=64 549walker=system.cpu.itb.walker 550 551[system.cpu.itb.walker] 552type=ArmTableWalker 553clock=500 554num_squash_per_cycle=2 555sys=system 556port=system.cpu.toL2Bus.slave[2] 557 558[system.cpu.l2cache] 559type=BaseCache 560addr_ranges=0:18446744073709551615 561assoc=8 562block_size=64 563clock=500 564forward_snoops=true
538hash_delay=1
539hit_latency=20 540is_top_level=false 541max_miss_count=0 542mshrs=20 543prefetch_on_access=false 544prefetcher=Null	565hit_latency=20 566is_top_level=false 567max_miss_count=0 568mshrs=20 569prefetch_on_access=false 570prefetcher=Null
545prioritizeRequests=false 546repl=Null
547response_latency=20 548size=2097152	571response_latency=20 572size=2097152
549subblock_size=0
550system=system 551tgts_per_mshr=12	573system=system 574tgts_per_mshr=12
552trace_addr=0
553two_queue=false 554write_buffers=8 555cpu_side=system.cpu.toL2Bus.master[0] 556mem_side=system.membus.slave[1] 557 558[system.cpu.toL2Bus] 559type=CoherentBus 560block_size=64 561clock=500 562header_cycles=1 563use_default_range=false 564width=32 565master=system.cpu.l2cache.cpu_side 566slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 567 568[system.cpu.tracer] 569type=ExeTracer 570 571[system.cpu.workload] 572type=LiveProcess 573cmd=hello 574cwd= 575egid=100 576env= 577errout=cerr 578euid=100	575two_queue=false 576write_buffers=8 577cpu_side=system.cpu.toL2Bus.master[0] 578mem_side=system.membus.slave[1] 579 580[system.cpu.toL2Bus] 581type=CoherentBus 582block_size=64 583clock=500 584header_cycles=1 585use_default_range=false 586width=32 587master=system.cpu.l2cache.cpu_side 588slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 589 590[system.cpu.tracer] 591type=ExeTracer 592 593[system.cpu.workload] 594type=LiveProcess 595cmd=hello 596cwd= 597egid=100 598env= 599errout=cerr 600euid=100
579executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello	601executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
580gid=100 581input=cin 582max_stack_size=67108864 583output=cout 584pid=100 585ppid=99 586simpoint=0 587system=system 588uid=100 589 590[system.membus] 591type=CoherentBus 592block_size=64 593clock=1000 594header_cycles=1 595use_default_range=false 596width=8 597master=system.physmem.port 598slave=system.system_port system.cpu.l2cache.mem_side 599 600[system.physmem] 601type=SimpleDRAM 602addr_mapping=openmap 603banks_per_rank=8 604clock=1000 605conf_table_reported=false 606in_addr_map=true 607lines_per_rowbuffer=64 608mem_sched_policy=fcfs 609null=false 610page_policy=open 611range=0:134217727 612ranks_per_channel=2 613read_buffer_size=32 614tBURST=4000 615tCL=14000 616tRCD=14000 617tREFI=7800000 618tRFC=300000 619tRP=14000 620tWTR=1000 621write_buffer_size=32 622write_thresh_perc=70 623zero=false 624port=system.membus.master[0] 625	602gid=100 603input=cin 604max_stack_size=67108864 605output=cout 606pid=100 607ppid=99 608simpoint=0 609system=system 610uid=100 611 612[system.membus] 613type=CoherentBus 614block_size=64 615clock=1000 616header_cycles=1 617use_default_range=false 618width=8 619master=system.physmem.port 620slave=system.system_port system.cpu.l2cache.mem_side 621 622[system.physmem] 623type=SimpleDRAM 624addr_mapping=openmap 625banks_per_rank=8 626clock=1000 627conf_table_reported=false 628in_addr_map=true 629lines_per_rowbuffer=64 630mem_sched_policy=fcfs 631null=false 632page_policy=open 633range=0:134217727 634ranks_per_channel=2 635read_buffer_size=32 636tBURST=4000 637tCL=14000 638tRCD=14000 639tREFI=7800000 640tRFC=300000 641tRP=14000 642tWTR=1000 643write_buffer_size=32 644write_thresh_perc=70 645zero=false 646port=system.membus.master[0] 647