Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

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config.ini (8911:4da2ea94319f)	config.ini (8983:8800b05e1cb3)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16
19physmem=system.physmem
20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=system.cpu.checker 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.checker] 129type=O3Checker 130children=dtb itb tracer 131checker=Null 132clock=1 133cpu_id=-1 134defer_registration=false 135do_checkpoint_insts=true 136do_quiesce=true 137do_statistics_insts=true 138dtb=system.cpu.checker.dtb 139exitOnError=false 140function_trace=false 141function_trace_start=0 142interrupts=Null 143itb=system.cpu.checker.itb 144max_insts_all_threads=0 145max_insts_any_thread=0 146max_loads_all_threads=0 147max_loads_any_thread=0 148numThreads=1 149phase=0 150profile=0 151progress_interval=0 152system=system 153tracer=system.cpu.checker.tracer 154updateOnError=true 155warnOnlyOnLoadError=true 156workload=system.cpu.workload 157 158[system.cpu.checker.dtb] 159type=ArmTLB 160children=walker 161size=64 162walker=system.cpu.checker.dtb.walker 163 164[system.cpu.checker.dtb.walker] 165type=ArmTableWalker 166max_backoff=100000 167min_backoff=0 168sys=system 169port=system.cpu.toL2Bus.slave[5] 170 171[system.cpu.checker.itb] 172type=ArmTLB 173children=walker 174size=64 175walker=system.cpu.checker.itb.walker 176 177[system.cpu.checker.itb.walker] 178type=ArmTableWalker 179max_backoff=100000 180min_backoff=0 181sys=system 182port=system.cpu.toL2Bus.slave[4] 183 184[system.cpu.checker.tracer] 185type=ExeTracer 186 187[system.cpu.dcache] 188type=BaseCache 189addr_ranges=0:18446744073709551615 190assoc=2 191block_size=64 192forward_snoops=true 193hash_delay=1 194is_top_level=true 195latency=1000 196max_miss_count=0 197mshrs=10 198prefetch_on_access=false 199prefetcher=Null 200prioritizeRequests=false 201repl=Null 202size=262144 203subblock_size=0 204system=system 205tgts_per_mshr=20 206trace_addr=0 207two_queue=false 208write_buffers=8 209cpu_side=system.cpu.dcache_port 210mem_side=system.cpu.toL2Bus.slave[1] 211 212[system.cpu.dtb] 213type=ArmTLB 214children=walker 215size=64 216walker=system.cpu.dtb.walker 217 218[system.cpu.dtb.walker] 219type=ArmTableWalker 220max_backoff=100000 221min_backoff=0 222sys=system 223port=system.cpu.toL2Bus.slave[3] 224 225[system.cpu.fuPool] 226type=FUPool 227children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 228FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 229 230[system.cpu.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234opList=system.cpu.fuPool.FUList0.opList 235 236[system.cpu.fuPool.FUList0.opList] 237type=OpDesc 238issueLat=1 239opClass=IntAlu 240opLat=1 241 242[system.cpu.fuPool.FUList1] 243type=FUDesc 244children=opList0 opList1 245count=2 246opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 247 248[system.cpu.fuPool.FUList1.opList0] 249type=OpDesc 250issueLat=1 251opClass=IntMult 252opLat=3 253 254[system.cpu.fuPool.FUList1.opList1] 255type=OpDesc 256issueLat=19 257opClass=IntDiv 258opLat=20 259 260[system.cpu.fuPool.FUList2] 261type=FUDesc 262children=opList0 opList1 opList2 263count=4 264opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 265 266[system.cpu.fuPool.FUList2.opList0] 267type=OpDesc 268issueLat=1 269opClass=FloatAdd 270opLat=2 271 272[system.cpu.fuPool.FUList2.opList1] 273type=OpDesc 274issueLat=1 275opClass=FloatCmp 276opLat=2 277 278[system.cpu.fuPool.FUList2.opList2] 279type=OpDesc 280issueLat=1 281opClass=FloatCvt 282opLat=2 283 284[system.cpu.fuPool.FUList3] 285type=FUDesc 286children=opList0 opList1 opList2 287count=2 288opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 289 290[system.cpu.fuPool.FUList3.opList0] 291type=OpDesc 292issueLat=1 293opClass=FloatMult 294opLat=4 295 296[system.cpu.fuPool.FUList3.opList1] 297type=OpDesc 298issueLat=12 299opClass=FloatDiv 300opLat=12 301 302[system.cpu.fuPool.FUList3.opList2] 303type=OpDesc 304issueLat=24 305opClass=FloatSqrt 306opLat=24 307 308[system.cpu.fuPool.FUList4] 309type=FUDesc 310children=opList 311count=0 312opList=system.cpu.fuPool.FUList4.opList 313 314[system.cpu.fuPool.FUList4.opList] 315type=OpDesc 316issueLat=1 317opClass=MemRead 318opLat=1 319 320[system.cpu.fuPool.FUList5] 321type=FUDesc 322children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 323count=4 324opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 325 326[system.cpu.fuPool.FUList5.opList00] 327type=OpDesc 328issueLat=1 329opClass=SimdAdd 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList01] 333type=OpDesc 334issueLat=1 335opClass=SimdAddAcc 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList02] 339type=OpDesc 340issueLat=1 341opClass=SimdAlu 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList03] 345type=OpDesc 346issueLat=1 347opClass=SimdCmp 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList04] 351type=OpDesc 352issueLat=1 353opClass=SimdCvt 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList05] 357type=OpDesc 358issueLat=1 359opClass=SimdMisc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList06] 363type=OpDesc 364issueLat=1 365opClass=SimdMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList07] 369type=OpDesc 370issueLat=1 371opClass=SimdMultAcc 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList08] 375type=OpDesc 376issueLat=1 377opClass=SimdShift 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList09] 381type=OpDesc 382issueLat=1 383opClass=SimdShiftAcc 384opLat=1 385 386[system.cpu.fuPool.FUList5.opList10] 387type=OpDesc 388issueLat=1 389opClass=SimdSqrt 390opLat=1 391 392[system.cpu.fuPool.FUList5.opList11] 393type=OpDesc 394issueLat=1 395opClass=SimdFloatAdd 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList12] 399type=OpDesc 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList14] 411type=OpDesc 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc 424issueLat=1 425opClass=SimdFloatMisc 426opLat=1 427 428[system.cpu.fuPool.FUList5.opList17] 429type=OpDesc 430issueLat=1 431opClass=SimdFloatMult 432opLat=1 433 434[system.cpu.fuPool.FUList5.opList18] 435type=OpDesc 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList19] 441type=OpDesc 442issueLat=1 443opClass=SimdFloatSqrt 444opLat=1 445 446[system.cpu.fuPool.FUList6] 447type=FUDesc 448children=opList 449count=0 450opList=system.cpu.fuPool.FUList6.opList 451 452[system.cpu.fuPool.FUList6.opList] 453type=OpDesc 454issueLat=1 455opClass=MemWrite 456opLat=1 457 458[system.cpu.fuPool.FUList7] 459type=FUDesc 460children=opList0 opList1 461count=4 462opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 463 464[system.cpu.fuPool.FUList7.opList0] 465type=OpDesc 466issueLat=1 467opClass=MemRead 468opLat=1 469 470[system.cpu.fuPool.FUList7.opList1] 471type=OpDesc 472issueLat=1 473opClass=MemWrite 474opLat=1 475 476[system.cpu.fuPool.FUList8] 477type=FUDesc 478children=opList 479count=1 480opList=system.cpu.fuPool.FUList8.opList 481 482[system.cpu.fuPool.FUList8.opList] 483type=OpDesc 484issueLat=3 485opClass=IprAccess 486opLat=3 487 488[system.cpu.icache] 489type=BaseCache 490addr_ranges=0:18446744073709551615 491assoc=2 492block_size=64 493forward_snoops=true 494hash_delay=1 495is_top_level=true 496latency=1000 497max_miss_count=0 498mshrs=10 499prefetch_on_access=false 500prefetcher=Null 501prioritizeRequests=false 502repl=Null 503size=131072 504subblock_size=0 505system=system 506tgts_per_mshr=20 507trace_addr=0 508two_queue=false 509write_buffers=8 510cpu_side=system.cpu.icache_port 511mem_side=system.cpu.toL2Bus.slave[0] 512 513[system.cpu.interrupts] 514type=ArmInterrupts 515 516[system.cpu.itb] 517type=ArmTLB 518children=walker 519size=64 520walker=system.cpu.itb.walker 521 522[system.cpu.itb.walker] 523type=ArmTableWalker 524max_backoff=100000 525min_backoff=0 526sys=system 527port=system.cpu.toL2Bus.slave[2] 528 529[system.cpu.l2cache] 530type=BaseCache 531addr_ranges=0:18446744073709551615 532assoc=2 533block_size=64 534forward_snoops=true 535hash_delay=1 536is_top_level=false 537latency=1000 538max_miss_count=0 539mshrs=10 540prefetch_on_access=false 541prefetcher=Null 542prioritizeRequests=false 543repl=Null 544size=2097152 545subblock_size=0 546system=system 547tgts_per_mshr=5 548trace_addr=0 549two_queue=false 550write_buffers=8 551cpu_side=system.cpu.toL2Bus.master[0] 552mem_side=system.membus.slave[1] 553 554[system.cpu.toL2Bus] 555type=Bus 556block_size=64 557bus_id=0 558clock=1000 559header_cycles=1 560use_default_range=false 561width=64 562master=system.cpu.l2cache.cpu_side 563slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 564 565[system.cpu.tracer] 566type=ExeTracer 567 568[system.cpu.workload] 569type=LiveProcess 570cmd=hello 571cwd= 572egid=100 573env= 574errout=cerr 575euid=100	19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 28system_port=system.membus.slave[0] 29 30[system.cpu] 31type=DerivO3CPU 32children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=system.cpu.checker 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.checker] 128type=O3Checker 129children=dtb itb tracer 130checker=Null 131clock=1 132cpu_id=-1 133defer_registration=false 134do_checkpoint_insts=true 135do_quiesce=true 136do_statistics_insts=true 137dtb=system.cpu.checker.dtb 138exitOnError=false 139function_trace=false 140function_trace_start=0 141interrupts=Null 142itb=system.cpu.checker.itb 143max_insts_all_threads=0 144max_insts_any_thread=0 145max_loads_all_threads=0 146max_loads_any_thread=0 147numThreads=1 148phase=0 149profile=0 150progress_interval=0 151system=system 152tracer=system.cpu.checker.tracer 153updateOnError=true 154warnOnlyOnLoadError=true 155workload=system.cpu.workload 156 157[system.cpu.checker.dtb] 158type=ArmTLB 159children=walker 160size=64 161walker=system.cpu.checker.dtb.walker 162 163[system.cpu.checker.dtb.walker] 164type=ArmTableWalker 165max_backoff=100000 166min_backoff=0 167sys=system 168port=system.cpu.toL2Bus.slave[5] 169 170[system.cpu.checker.itb] 171type=ArmTLB 172children=walker 173size=64 174walker=system.cpu.checker.itb.walker 175 176[system.cpu.checker.itb.walker] 177type=ArmTableWalker 178max_backoff=100000 179min_backoff=0 180sys=system 181port=system.cpu.toL2Bus.slave[4] 182 183[system.cpu.checker.tracer] 184type=ExeTracer 185 186[system.cpu.dcache] 187type=BaseCache 188addr_ranges=0:18446744073709551615 189assoc=2 190block_size=64 191forward_snoops=true 192hash_delay=1 193is_top_level=true 194latency=1000 195max_miss_count=0 196mshrs=10 197prefetch_on_access=false 198prefetcher=Null 199prioritizeRequests=false 200repl=Null 201size=262144 202subblock_size=0 203system=system 204tgts_per_mshr=20 205trace_addr=0 206two_queue=false 207write_buffers=8 208cpu_side=system.cpu.dcache_port 209mem_side=system.cpu.toL2Bus.slave[1] 210 211[system.cpu.dtb] 212type=ArmTLB 213children=walker 214size=64 215walker=system.cpu.dtb.walker 216 217[system.cpu.dtb.walker] 218type=ArmTableWalker 219max_backoff=100000 220min_backoff=0 221sys=system 222port=system.cpu.toL2Bus.slave[3] 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228 229[system.cpu.fuPool.FUList0] 230type=FUDesc 231children=opList 232count=6 233opList=system.cpu.fuPool.FUList0.opList 234 235[system.cpu.fuPool.FUList0.opList] 236type=OpDesc 237issueLat=1 238opClass=IntAlu 239opLat=1 240 241[system.cpu.fuPool.FUList1] 242type=FUDesc 243children=opList0 opList1 244count=2 245opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 246 247[system.cpu.fuPool.FUList1.opList0] 248type=OpDesc 249issueLat=1 250opClass=IntMult 251opLat=3 252 253[system.cpu.fuPool.FUList1.opList1] 254type=OpDesc 255issueLat=19 256opClass=IntDiv 257opLat=20 258 259[system.cpu.fuPool.FUList2] 260type=FUDesc 261children=opList0 opList1 opList2 262count=4 263opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 264 265[system.cpu.fuPool.FUList2.opList0] 266type=OpDesc 267issueLat=1 268opClass=FloatAdd 269opLat=2 270 271[system.cpu.fuPool.FUList2.opList1] 272type=OpDesc 273issueLat=1 274opClass=FloatCmp 275opLat=2 276 277[system.cpu.fuPool.FUList2.opList2] 278type=OpDesc 279issueLat=1 280opClass=FloatCvt 281opLat=2 282 283[system.cpu.fuPool.FUList3] 284type=FUDesc 285children=opList0 opList1 opList2 286count=2 287opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 288 289[system.cpu.fuPool.FUList3.opList0] 290type=OpDesc 291issueLat=1 292opClass=FloatMult 293opLat=4 294 295[system.cpu.fuPool.FUList3.opList1] 296type=OpDesc 297issueLat=12 298opClass=FloatDiv 299opLat=12 300 301[system.cpu.fuPool.FUList3.opList2] 302type=OpDesc 303issueLat=24 304opClass=FloatSqrt 305opLat=24 306 307[system.cpu.fuPool.FUList4] 308type=FUDesc 309children=opList 310count=0 311opList=system.cpu.fuPool.FUList4.opList 312 313[system.cpu.fuPool.FUList4.opList] 314type=OpDesc 315issueLat=1 316opClass=MemRead 317opLat=1 318 319[system.cpu.fuPool.FUList5] 320type=FUDesc 321children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 322count=4 323opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 324 325[system.cpu.fuPool.FUList5.opList00] 326type=OpDesc 327issueLat=1 328opClass=SimdAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList01] 332type=OpDesc 333issueLat=1 334opClass=SimdAddAcc 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList02] 338type=OpDesc 339issueLat=1 340opClass=SimdAlu 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList03] 344type=OpDesc 345issueLat=1 346opClass=SimdCmp 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList04] 350type=OpDesc 351issueLat=1 352opClass=SimdCvt 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList05] 356type=OpDesc 357issueLat=1 358opClass=SimdMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList06] 362type=OpDesc 363issueLat=1 364opClass=SimdMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList07] 368type=OpDesc 369issueLat=1 370opClass=SimdMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList08] 374type=OpDesc 375issueLat=1 376opClass=SimdShift 377opLat=1 378 379[system.cpu.fuPool.FUList5.opList09] 380type=OpDesc 381issueLat=1 382opClass=SimdShiftAcc 383opLat=1 384 385[system.cpu.fuPool.FUList5.opList10] 386type=OpDesc 387issueLat=1 388opClass=SimdSqrt 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList11] 392type=OpDesc 393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList13] 404type=OpDesc 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417issueLat=1 418opClass=SimdFloatDiv 419opLat=1 420 421[system.cpu.fuPool.FUList5.opList16] 422type=OpDesc 423issueLat=1 424opClass=SimdFloatMisc 425opLat=1 426 427[system.cpu.fuPool.FUList5.opList17] 428type=OpDesc 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList18] 434type=OpDesc 435issueLat=1 436opClass=SimdFloatMultAcc 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList19] 440type=OpDesc 441issueLat=1 442opClass=SimdFloatSqrt 443opLat=1 444 445[system.cpu.fuPool.FUList6] 446type=FUDesc 447children=opList 448count=0 449opList=system.cpu.fuPool.FUList6.opList 450 451[system.cpu.fuPool.FUList6.opList] 452type=OpDesc 453issueLat=1 454opClass=MemWrite 455opLat=1 456 457[system.cpu.fuPool.FUList7] 458type=FUDesc 459children=opList0 opList1 460count=4 461opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 462 463[system.cpu.fuPool.FUList7.opList0] 464type=OpDesc 465issueLat=1 466opClass=MemRead 467opLat=1 468 469[system.cpu.fuPool.FUList7.opList1] 470type=OpDesc 471issueLat=1 472opClass=MemWrite 473opLat=1 474 475[system.cpu.fuPool.FUList8] 476type=FUDesc 477children=opList 478count=1 479opList=system.cpu.fuPool.FUList8.opList 480 481[system.cpu.fuPool.FUList8.opList] 482type=OpDesc 483issueLat=3 484opClass=IprAccess 485opLat=3 486 487[system.cpu.icache] 488type=BaseCache 489addr_ranges=0:18446744073709551615 490assoc=2 491block_size=64 492forward_snoops=true 493hash_delay=1 494is_top_level=true 495latency=1000 496max_miss_count=0 497mshrs=10 498prefetch_on_access=false 499prefetcher=Null 500prioritizeRequests=false 501repl=Null 502size=131072 503subblock_size=0 504system=system 505tgts_per_mshr=20 506trace_addr=0 507two_queue=false 508write_buffers=8 509cpu_side=system.cpu.icache_port 510mem_side=system.cpu.toL2Bus.slave[0] 511 512[system.cpu.interrupts] 513type=ArmInterrupts 514 515[system.cpu.itb] 516type=ArmTLB 517children=walker 518size=64 519walker=system.cpu.itb.walker 520 521[system.cpu.itb.walker] 522type=ArmTableWalker 523max_backoff=100000 524min_backoff=0 525sys=system 526port=system.cpu.toL2Bus.slave[2] 527 528[system.cpu.l2cache] 529type=BaseCache 530addr_ranges=0:18446744073709551615 531assoc=2 532block_size=64 533forward_snoops=true 534hash_delay=1 535is_top_level=false 536latency=1000 537max_miss_count=0 538mshrs=10 539prefetch_on_access=false 540prefetcher=Null 541prioritizeRequests=false 542repl=Null 543size=2097152 544subblock_size=0 545system=system 546tgts_per_mshr=5 547trace_addr=0 548two_queue=false 549write_buffers=8 550cpu_side=system.cpu.toL2Bus.master[0] 551mem_side=system.membus.slave[1] 552 553[system.cpu.toL2Bus] 554type=Bus 555block_size=64 556bus_id=0 557clock=1000 558header_cycles=1 559use_default_range=false 560width=64 561master=system.cpu.l2cache.cpu_side 562slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 563 564[system.cpu.tracer] 565type=ExeTracer 566 567[system.cpu.workload] 568type=LiveProcess 569cmd=hello 570cwd= 571egid=100 572env= 573errout=cerr 574euid=100
576executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello	575executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
577gid=100 578input=cin 579max_stack_size=67108864 580output=cout 581pid=100 582ppid=99 583simpoint=0 584system=system 585uid=100 586 587[system.membus] 588type=Bus 589block_size=64 590bus_id=0 591clock=1000 592header_cycles=1 593use_default_range=false 594width=64 595master=system.physmem.port[0] 596slave=system.system_port system.cpu.l2cache.mem_side 597 598[system.physmem]	576gid=100 577input=cin 578max_stack_size=67108864 579output=cout 580pid=100 581ppid=99 582simpoint=0 583system=system 584uid=100 585 586[system.membus] 587type=Bus 588block_size=64 589bus_id=0 590clock=1000 591header_cycles=1 592use_default_range=false 593width=64 594master=system.physmem.port[0] 595slave=system.system_port system.cpu.l2cache.mem_side 596 597[system.physmem]
599type=PhysicalMemory	598type=SimpleMemory 599conf_table_reported=false
600file=	600file=
	601in_addr_map=true
601latency=30000 602latency_var=0 603null=false 604range=0:134217727 605zero=false 606port=system.membus.master[0] 607	602latency=30000 603latency_var=0 604null=false 605range=0:134217727 606zero=false 607port=system.membus.master[0] 608