Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

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config.ini (11219:b65d4e878ed2)	config.ini (11268:8b4b55d79ddd)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.clk_domain] 41type=SrcClockDomain 42clock=1000 43domain_id=-1 44eventq_index=0 45init_perf_level=0 46voltage_domain=system.voltage_domain 47 48[system.cpu] 49type=DerivO3CPU 50children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55SQEntries=32 56SSITSize=1024 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=system.cpu.checker 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dstage2_mmu=system.cpu.dstage2_mmu 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96istage2_mmu=system.cpu.istage2_mmu 97itb=system.cpu.itb 98max_insts_all_threads=0 99max_insts_any_thread=0 100max_loads_all_threads=0 101max_loads_any_thread=0 102needsTSO=false 103numIQEntries=64 104numPhysCCRegs=1280 105numPhysFloatRegs=256 106numPhysIntRegs=256 107numROBEntries=192 108numRobs=1 109numThreads=1 110profile=0 111progress_interval=0 112renameToDecodeDelay=1 113renameToFetchDelay=1 114renameToIEWDelay=2 115renameToROBDelay=1 116renameWidth=8 117simpoint_start_insts= 118smtCommitPolicy=RoundRobin 119smtFetchPolicy=SingleThread 120smtIQPolicy=Partitioned 121smtIQThreshold=100 122smtLSQPolicy=Partitioned 123smtLSQThreshold=100 124smtNumFetchingThreads=1 125smtROBPolicy=Partitioned 126smtROBThreshold=100 127socket_id=0 128squashWidth=8 129store_set_clear_period=250000 130switched_out=false 131system=system 132tracer=system.cpu.tracer 133trapLatency=13 134wbWidth=8 135workload=system.cpu.workload 136dcache_port=system.cpu.dcache.cpu_side 137icache_port=system.cpu.icache.cpu_side 138 139[system.cpu.branchPred] 140type=TournamentBP 141BTBEntries=4096 142BTBTagSize=16 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 146eventq_index=0 147globalCtrBits=2 148globalPredictorSize=8192 149instShiftAmt=2 150localCtrBits=2 151localHistoryTableSize=2048 152localPredictorSize=2048 153numThreads=1 154 155[system.cpu.checker] 156type=O3Checker 157children=dstage2_mmu dtb isa istage2_mmu itb tracer 158checker=Null 159clk_domain=system.cpu_clk_domain 160cpu_id=0 161do_checkpoint_insts=true 162do_quiesce=true 163do_statistics_insts=true 164dstage2_mmu=system.cpu.checker.dstage2_mmu 165dtb=system.cpu.checker.dtb 166eventq_index=0 167exitOnError=false 168function_trace=false 169function_trace_start=0 170interrupts= 171isa=system.cpu.checker.isa 172istage2_mmu=system.cpu.checker.istage2_mmu 173itb=system.cpu.checker.itb 174max_insts_all_threads=0 175max_insts_any_thread=0 176max_loads_all_threads=0 177max_loads_any_thread=0 178numThreads=1 179profile=0 180progress_interval=0 181simpoint_start_insts= 182socket_id=0 183switched_out=false 184system=system 185tracer=system.cpu.checker.tracer 186updateOnError=true 187warnOnlyOnLoadError=true 188workload=system.cpu.workload 189 190[system.cpu.checker.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 195sys=system 196tlb=system.cpu.checker.dtb 197 198[system.cpu.checker.dstage2_mmu.stage2_tlb] 199type=ArmTLB 200children=walker 201eventq_index=0 202is_stage2=true 203size=32 204walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 205 206[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 207type=ArmTableWalker 208clk_domain=system.cpu_clk_domain 209eventq_index=0 210is_stage2=true 211num_squash_per_cycle=2 212sys=system 213 214[system.cpu.checker.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.checker.dtb.walker 221 222[system.cpu.checker.dtb.walker] 223type=ArmTableWalker 224clk_domain=system.cpu_clk_domain 225eventq_index=0 226is_stage2=false 227num_squash_per_cycle=2 228sys=system 229port=system.cpu.toL2Bus.slave[5] 230 231[system.cpu.checker.isa] 232type=ArmISA 233decoderFlavour=Generic 234eventq_index=0 235fpsid=1090793632 236id_aa64afr0_el1=0 237id_aa64afr1_el1=0 238id_aa64dfr0_el1=1052678 239id_aa64dfr1_el1=0 240id_aa64isar0_el1=0 241id_aa64isar1_el1=0 242id_aa64mmfr0_el1=15728642 243id_aa64mmfr1_el1=0 244id_aa64pfr0_el1=17 245id_aa64pfr1_el1=0 246id_isar0=34607377 247id_isar1=34677009 248id_isar2=555950401 249id_isar3=17899825 250id_isar4=268501314 251id_isar5=0 252id_mmfr0=270536963 253id_mmfr1=0 254id_mmfr2=19070976 255id_mmfr3=34611729 256id_pfr0=49 257id_pfr1=4113 258midr=1091551472 259pmu=Null 260system=system 261 262[system.cpu.checker.istage2_mmu] 263type=ArmStage2MMU 264children=stage2_tlb 265eventq_index=0 266stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 267sys=system 268tlb=system.cpu.checker.itb 269 270[system.cpu.checker.istage2_mmu.stage2_tlb] 271type=ArmTLB 272children=walker 273eventq_index=0 274is_stage2=true 275size=32 276walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 277 278[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 279type=ArmTableWalker 280clk_domain=system.cpu_clk_domain 281eventq_index=0 282is_stage2=true 283num_squash_per_cycle=2 284sys=system 285 286[system.cpu.checker.itb] 287type=ArmTLB 288children=walker 289eventq_index=0 290is_stage2=false 291size=64 292walker=system.cpu.checker.itb.walker 293 294[system.cpu.checker.itb.walker] 295type=ArmTableWalker 296clk_domain=system.cpu_clk_domain 297eventq_index=0 298is_stage2=false 299num_squash_per_cycle=2 300sys=system 301port=system.cpu.toL2Bus.slave[4] 302 303[system.cpu.checker.tracer] 304type=ExeTracer 305eventq_index=0 306 307[system.cpu.dcache] 308type=Cache 309children=tags 310addr_ranges=0:18446744073709551615 311assoc=2 312clk_domain=system.cpu_clk_domain 313clusivity=mostly_incl 314demand_mshr_reserve=1 315eventq_index=0 316forward_snoops=true 317hit_latency=2 318is_read_only=false 319max_miss_count=0 320mshrs=4 321prefetch_on_access=false 322prefetcher=Null 323response_latency=2 324sequential_access=false 325size=262144 326system=system 327tags=system.cpu.dcache.tags 328tgts_per_mshr=20 329write_buffers=8 330writeback_clean=false 331cpu_side=system.cpu.dcache_port 332mem_side=system.cpu.toL2Bus.slave[1] 333 334[system.cpu.dcache.tags] 335type=LRU 336assoc=2 337block_size=64 338clk_domain=system.cpu_clk_domain 339eventq_index=0 340hit_latency=2 341sequential_access=false 342size=262144 343 344[system.cpu.dstage2_mmu] 345type=ArmStage2MMU 346children=stage2_tlb 347eventq_index=0 348stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 349sys=system 350tlb=system.cpu.dtb 351 352[system.cpu.dstage2_mmu.stage2_tlb] 353type=ArmTLB 354children=walker 355eventq_index=0 356is_stage2=true 357size=32 358walker=system.cpu.dstage2_mmu.stage2_tlb.walker 359 360[system.cpu.dstage2_mmu.stage2_tlb.walker] 361type=ArmTableWalker 362clk_domain=system.cpu_clk_domain 363eventq_index=0 364is_stage2=true 365num_squash_per_cycle=2 366sys=system 367 368[system.cpu.dtb] 369type=ArmTLB 370children=walker 371eventq_index=0 372is_stage2=false 373size=64 374walker=system.cpu.dtb.walker 375 376[system.cpu.dtb.walker] 377type=ArmTableWalker 378clk_domain=system.cpu_clk_domain 379eventq_index=0 380is_stage2=false 381num_squash_per_cycle=2 382sys=system 383port=system.cpu.toL2Bus.slave[3] 384 385[system.cpu.fuPool] 386type=FUPool 387children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 388FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 389eventq_index=0 390 391[system.cpu.fuPool.FUList0] 392type=FUDesc 393children=opList 394count=6 395eventq_index=0 396opList=system.cpu.fuPool.FUList0.opList 397 398[system.cpu.fuPool.FUList0.opList] 399type=OpDesc 400eventq_index=0 401opClass=IntAlu 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList1] 406type=FUDesc 407children=opList0 opList1 408count=2 409eventq_index=0 410opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 411 412[system.cpu.fuPool.FUList1.opList0] 413type=OpDesc 414eventq_index=0 415opClass=IntMult 416opLat=3 417pipelined=true 418 419[system.cpu.fuPool.FUList1.opList1] 420type=OpDesc 421eventq_index=0 422opClass=IntDiv 423opLat=20 424pipelined=false 425 426[system.cpu.fuPool.FUList2] 427type=FUDesc 428children=opList0 opList1 opList2 429count=4 430eventq_index=0 431opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 432 433[system.cpu.fuPool.FUList2.opList0] 434type=OpDesc 435eventq_index=0 436opClass=FloatAdd 437opLat=2 438pipelined=true 439 440[system.cpu.fuPool.FUList2.opList1] 441type=OpDesc 442eventq_index=0 443opClass=FloatCmp 444opLat=2 445pipelined=true 446 447[system.cpu.fuPool.FUList2.opList2] 448type=OpDesc 449eventq_index=0 450opClass=FloatCvt 451opLat=2 452pipelined=true 453 454[system.cpu.fuPool.FUList3] 455type=FUDesc 456children=opList0 opList1 opList2 457count=2 458eventq_index=0 459opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 460 461[system.cpu.fuPool.FUList3.opList0] 462type=OpDesc 463eventq_index=0 464opClass=FloatMult 465opLat=4 466pipelined=true 467 468[system.cpu.fuPool.FUList3.opList1] 469type=OpDesc 470eventq_index=0 471opClass=FloatDiv 472opLat=12 473pipelined=false 474 475[system.cpu.fuPool.FUList3.opList2] 476type=OpDesc 477eventq_index=0 478opClass=FloatSqrt 479opLat=24 480pipelined=false 481 482[system.cpu.fuPool.FUList4] 483type=FUDesc 484children=opList 485count=0 486eventq_index=0 487opList=system.cpu.fuPool.FUList4.opList 488 489[system.cpu.fuPool.FUList4.opList] 490type=OpDesc 491eventq_index=0 492opClass=MemRead 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5] 497type=FUDesc 498children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 499count=4 500eventq_index=0 501opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 502 503[system.cpu.fuPool.FUList5.opList00] 504type=OpDesc 505eventq_index=0 506opClass=SimdAdd 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList5.opList01] 511type=OpDesc 512eventq_index=0 513opClass=SimdAddAcc 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList5.opList02] 518type=OpDesc 519eventq_index=0 520opClass=SimdAlu 521opLat=1 522pipelined=true 523 524[system.cpu.fuPool.FUList5.opList03] 525type=OpDesc 526eventq_index=0 527opClass=SimdCmp 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList5.opList04] 532type=OpDesc 533eventq_index=0 534opClass=SimdCvt 535opLat=1 536pipelined=true 537 538[system.cpu.fuPool.FUList5.opList05] 539type=OpDesc 540eventq_index=0 541opClass=SimdMisc 542opLat=1 543pipelined=true 544 545[system.cpu.fuPool.FUList5.opList06] 546type=OpDesc 547eventq_index=0 548opClass=SimdMult 549opLat=1 550pipelined=true 551 552[system.cpu.fuPool.FUList5.opList07] 553type=OpDesc 554eventq_index=0 555opClass=SimdMultAcc 556opLat=1 557pipelined=true 558 559[system.cpu.fuPool.FUList5.opList08] 560type=OpDesc 561eventq_index=0 562opClass=SimdShift 563opLat=1 564pipelined=true 565 566[system.cpu.fuPool.FUList5.opList09] 567type=OpDesc 568eventq_index=0 569opClass=SimdShiftAcc 570opLat=1 571pipelined=true 572 573[system.cpu.fuPool.FUList5.opList10] 574type=OpDesc 575eventq_index=0 576opClass=SimdSqrt 577opLat=1 578pipelined=true 579 580[system.cpu.fuPool.FUList5.opList11] 581type=OpDesc 582eventq_index=0 583opClass=SimdFloatAdd 584opLat=1 585pipelined=true 586 587[system.cpu.fuPool.FUList5.opList12] 588type=OpDesc 589eventq_index=0 590opClass=SimdFloatAlu 591opLat=1 592pipelined=true 593 594[system.cpu.fuPool.FUList5.opList13] 595type=OpDesc 596eventq_index=0 597opClass=SimdFloatCmp 598opLat=1 599pipelined=true 600 601[system.cpu.fuPool.FUList5.opList14] 602type=OpDesc 603eventq_index=0 604opClass=SimdFloatCvt 605opLat=1 606pipelined=true 607 608[system.cpu.fuPool.FUList5.opList15] 609type=OpDesc 610eventq_index=0 611opClass=SimdFloatDiv 612opLat=1 613pipelined=true 614 615[system.cpu.fuPool.FUList5.opList16] 616type=OpDesc 617eventq_index=0 618opClass=SimdFloatMisc 619opLat=1 620pipelined=true 621 622[system.cpu.fuPool.FUList5.opList17] 623type=OpDesc 624eventq_index=0 625opClass=SimdFloatMult 626opLat=1 627pipelined=true 628 629[system.cpu.fuPool.FUList5.opList18] 630type=OpDesc 631eventq_index=0 632opClass=SimdFloatMultAcc 633opLat=1 634pipelined=true 635 636[system.cpu.fuPool.FUList5.opList19] 637type=OpDesc 638eventq_index=0 639opClass=SimdFloatSqrt 640opLat=1 641pipelined=true 642 643[system.cpu.fuPool.FUList6] 644type=FUDesc 645children=opList 646count=0 647eventq_index=0 648opList=system.cpu.fuPool.FUList6.opList 649 650[system.cpu.fuPool.FUList6.opList] 651type=OpDesc 652eventq_index=0 653opClass=MemWrite 654opLat=1 655pipelined=true 656 657[system.cpu.fuPool.FUList7] 658type=FUDesc 659children=opList0 opList1 660count=4 661eventq_index=0 662opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 663 664[system.cpu.fuPool.FUList7.opList0] 665type=OpDesc 666eventq_index=0 667opClass=MemRead 668opLat=1 669pipelined=true 670 671[system.cpu.fuPool.FUList7.opList1] 672type=OpDesc 673eventq_index=0 674opClass=MemWrite 675opLat=1 676pipelined=true 677 678[system.cpu.fuPool.FUList8] 679type=FUDesc 680children=opList 681count=1 682eventq_index=0 683opList=system.cpu.fuPool.FUList8.opList 684 685[system.cpu.fuPool.FUList8.opList] 686type=OpDesc 687eventq_index=0 688opClass=IprAccess 689opLat=3 690pipelined=false 691 692[system.cpu.icache] 693type=Cache 694children=tags 695addr_ranges=0:18446744073709551615 696assoc=2 697clk_domain=system.cpu_clk_domain 698clusivity=mostly_incl 699demand_mshr_reserve=1 700eventq_index=0 701forward_snoops=true 702hit_latency=2 703is_read_only=true 704max_miss_count=0 705mshrs=4 706prefetch_on_access=false 707prefetcher=Null 708response_latency=2 709sequential_access=false 710size=131072 711system=system 712tags=system.cpu.icache.tags 713tgts_per_mshr=20 714write_buffers=8 715writeback_clean=true 716cpu_side=system.cpu.icache_port 717mem_side=system.cpu.toL2Bus.slave[0] 718 719[system.cpu.icache.tags] 720type=LRU 721assoc=2 722block_size=64 723clk_domain=system.cpu_clk_domain 724eventq_index=0 725hit_latency=2 726sequential_access=false 727size=131072 728 729[system.cpu.interrupts] 730type=ArmInterrupts 731eventq_index=0 732 733[system.cpu.isa] 734type=ArmISA 735decoderFlavour=Generic 736eventq_index=0 737fpsid=1090793632 738id_aa64afr0_el1=0 739id_aa64afr1_el1=0 740id_aa64dfr0_el1=1052678 741id_aa64dfr1_el1=0 742id_aa64isar0_el1=0 743id_aa64isar1_el1=0 744id_aa64mmfr0_el1=15728642 745id_aa64mmfr1_el1=0 746id_aa64pfr0_el1=17 747id_aa64pfr1_el1=0 748id_isar0=34607377 749id_isar1=34677009 750id_isar2=555950401 751id_isar3=17899825 752id_isar4=268501314 753id_isar5=0 754id_mmfr0=270536963 755id_mmfr1=0 756id_mmfr2=19070976 757id_mmfr3=34611729 758id_pfr0=49 759id_pfr1=4113 760midr=1091551472 761pmu=Null 762system=system 763 764[system.cpu.istage2_mmu] 765type=ArmStage2MMU 766children=stage2_tlb 767eventq_index=0 768stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 769sys=system 770tlb=system.cpu.itb 771 772[system.cpu.istage2_mmu.stage2_tlb] 773type=ArmTLB 774children=walker 775eventq_index=0 776is_stage2=true 777size=32 778walker=system.cpu.istage2_mmu.stage2_tlb.walker 779 780[system.cpu.istage2_mmu.stage2_tlb.walker] 781type=ArmTableWalker 782clk_domain=system.cpu_clk_domain 783eventq_index=0 784is_stage2=true 785num_squash_per_cycle=2 786sys=system 787 788[system.cpu.itb] 789type=ArmTLB 790children=walker 791eventq_index=0 792is_stage2=false 793size=64 794walker=system.cpu.itb.walker 795 796[system.cpu.itb.walker] 797type=ArmTableWalker 798clk_domain=system.cpu_clk_domain 799eventq_index=0 800is_stage2=false 801num_squash_per_cycle=2 802sys=system 803port=system.cpu.toL2Bus.slave[2] 804 805[system.cpu.l2cache] 806type=Cache 807children=tags 808addr_ranges=0:18446744073709551615 809assoc=8 810clk_domain=system.cpu_clk_domain 811clusivity=mostly_incl 812demand_mshr_reserve=1 813eventq_index=0 814forward_snoops=true 815hit_latency=20 816is_read_only=false 817max_miss_count=0 818mshrs=20 819prefetch_on_access=false 820prefetcher=Null 821response_latency=20 822sequential_access=false 823size=2097152 824system=system 825tags=system.cpu.l2cache.tags 826tgts_per_mshr=12 827write_buffers=8 828writeback_clean=false 829cpu_side=system.cpu.toL2Bus.master[0] 830mem_side=system.membus.slave[1] 831 832[system.cpu.l2cache.tags] 833type=LRU 834assoc=8 835block_size=64 836clk_domain=system.cpu_clk_domain 837eventq_index=0 838hit_latency=20 839sequential_access=false 840size=2097152 841 842[system.cpu.toL2Bus] 843type=CoherentXBar 844children=snoop_filter 845clk_domain=system.cpu_clk_domain 846eventq_index=0 847forward_latency=0 848frontend_latency=1 849response_latency=1 850snoop_filter=system.cpu.toL2Bus.snoop_filter 851snoop_response_latency=1 852system=system 853use_default_range=false 854width=32 855master=system.cpu.l2cache.cpu_side 856slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 857 858[system.cpu.toL2Bus.snoop_filter] 859type=SnoopFilter 860eventq_index=0 861lookup_latency=0 862max_capacity=8388608 863system=system 864 865[system.cpu.tracer] 866type=ExeTracer 867eventq_index=0 868 869[system.cpu.workload] 870type=LiveProcess 871cmd=hello 872cwd= 873drivers= 874egid=100 875env= 876errout=cerr 877euid=100 878eventq_index=0	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27multi_thread=false 28num_work_ids=16 29readfile= 30symbolfile= 31work_begin_ckpt_count=0 32work_begin_cpu_id_exit=-1 33work_begin_exit_count=0 34work_cpus_ckpt_count=0 35work_end_ckpt_count=0 36work_end_exit_count=0 37work_item_id=-1 38system_port=system.membus.slave[0] 39 40[system.clk_domain] 41type=SrcClockDomain 42clock=1000 43domain_id=-1 44eventq_index=0 45init_perf_level=0 46voltage_domain=system.voltage_domain 47 48[system.cpu] 49type=DerivO3CPU 50children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 51LFSTSize=1024 52LQEntries=32 53LSQCheckLoads=true 54LSQDepCheckShift=4 55SQEntries=32 56SSITSize=1024 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=system.cpu.checker 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dstage2_mmu=system.cpu.dstage2_mmu 77dtb=system.cpu.dtb 78eventq_index=0 79fetchBufferSize=64 80fetchQueueSize=32 81fetchToDecodeDelay=1 82fetchTrapLatency=1 83fetchWidth=8 84forwardComSize=5 85fuPool=system.cpu.fuPool 86function_trace=false 87function_trace_start=0 88iewToCommitDelay=1 89iewToDecodeDelay=1 90iewToFetchDelay=1 91iewToRenameDelay=1 92interrupts=system.cpu.interrupts 93isa=system.cpu.isa 94issueToExecuteDelay=1 95issueWidth=8 96istage2_mmu=system.cpu.istage2_mmu 97itb=system.cpu.itb 98max_insts_all_threads=0 99max_insts_any_thread=0 100max_loads_all_threads=0 101max_loads_any_thread=0 102needsTSO=false 103numIQEntries=64 104numPhysCCRegs=1280 105numPhysFloatRegs=256 106numPhysIntRegs=256 107numROBEntries=192 108numRobs=1 109numThreads=1 110profile=0 111progress_interval=0 112renameToDecodeDelay=1 113renameToFetchDelay=1 114renameToIEWDelay=2 115renameToROBDelay=1 116renameWidth=8 117simpoint_start_insts= 118smtCommitPolicy=RoundRobin 119smtFetchPolicy=SingleThread 120smtIQPolicy=Partitioned 121smtIQThreshold=100 122smtLSQPolicy=Partitioned 123smtLSQThreshold=100 124smtNumFetchingThreads=1 125smtROBPolicy=Partitioned 126smtROBThreshold=100 127socket_id=0 128squashWidth=8 129store_set_clear_period=250000 130switched_out=false 131system=system 132tracer=system.cpu.tracer 133trapLatency=13 134wbWidth=8 135workload=system.cpu.workload 136dcache_port=system.cpu.dcache.cpu_side 137icache_port=system.cpu.icache.cpu_side 138 139[system.cpu.branchPred] 140type=TournamentBP 141BTBEntries=4096 142BTBTagSize=16 143RASSize=16 144choiceCtrBits=2 145choicePredictorSize=8192 146eventq_index=0 147globalCtrBits=2 148globalPredictorSize=8192 149instShiftAmt=2 150localCtrBits=2 151localHistoryTableSize=2048 152localPredictorSize=2048 153numThreads=1 154 155[system.cpu.checker] 156type=O3Checker 157children=dstage2_mmu dtb isa istage2_mmu itb tracer 158checker=Null 159clk_domain=system.cpu_clk_domain 160cpu_id=0 161do_checkpoint_insts=true 162do_quiesce=true 163do_statistics_insts=true 164dstage2_mmu=system.cpu.checker.dstage2_mmu 165dtb=system.cpu.checker.dtb 166eventq_index=0 167exitOnError=false 168function_trace=false 169function_trace_start=0 170interrupts= 171isa=system.cpu.checker.isa 172istage2_mmu=system.cpu.checker.istage2_mmu 173itb=system.cpu.checker.itb 174max_insts_all_threads=0 175max_insts_any_thread=0 176max_loads_all_threads=0 177max_loads_any_thread=0 178numThreads=1 179profile=0 180progress_interval=0 181simpoint_start_insts= 182socket_id=0 183switched_out=false 184system=system 185tracer=system.cpu.checker.tracer 186updateOnError=true 187warnOnlyOnLoadError=true 188workload=system.cpu.workload 189 190[system.cpu.checker.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 195sys=system 196tlb=system.cpu.checker.dtb 197 198[system.cpu.checker.dstage2_mmu.stage2_tlb] 199type=ArmTLB 200children=walker 201eventq_index=0 202is_stage2=true 203size=32 204walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 205 206[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 207type=ArmTableWalker 208clk_domain=system.cpu_clk_domain 209eventq_index=0 210is_stage2=true 211num_squash_per_cycle=2 212sys=system 213 214[system.cpu.checker.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.checker.dtb.walker 221 222[system.cpu.checker.dtb.walker] 223type=ArmTableWalker 224clk_domain=system.cpu_clk_domain 225eventq_index=0 226is_stage2=false 227num_squash_per_cycle=2 228sys=system 229port=system.cpu.toL2Bus.slave[5] 230 231[system.cpu.checker.isa] 232type=ArmISA 233decoderFlavour=Generic 234eventq_index=0 235fpsid=1090793632 236id_aa64afr0_el1=0 237id_aa64afr1_el1=0 238id_aa64dfr0_el1=1052678 239id_aa64dfr1_el1=0 240id_aa64isar0_el1=0 241id_aa64isar1_el1=0 242id_aa64mmfr0_el1=15728642 243id_aa64mmfr1_el1=0 244id_aa64pfr0_el1=17 245id_aa64pfr1_el1=0 246id_isar0=34607377 247id_isar1=34677009 248id_isar2=555950401 249id_isar3=17899825 250id_isar4=268501314 251id_isar5=0 252id_mmfr0=270536963 253id_mmfr1=0 254id_mmfr2=19070976 255id_mmfr3=34611729 256id_pfr0=49 257id_pfr1=4113 258midr=1091551472 259pmu=Null 260system=system 261 262[system.cpu.checker.istage2_mmu] 263type=ArmStage2MMU 264children=stage2_tlb 265eventq_index=0 266stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 267sys=system 268tlb=system.cpu.checker.itb 269 270[system.cpu.checker.istage2_mmu.stage2_tlb] 271type=ArmTLB 272children=walker 273eventq_index=0 274is_stage2=true 275size=32 276walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 277 278[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 279type=ArmTableWalker 280clk_domain=system.cpu_clk_domain 281eventq_index=0 282is_stage2=true 283num_squash_per_cycle=2 284sys=system 285 286[system.cpu.checker.itb] 287type=ArmTLB 288children=walker 289eventq_index=0 290is_stage2=false 291size=64 292walker=system.cpu.checker.itb.walker 293 294[system.cpu.checker.itb.walker] 295type=ArmTableWalker 296clk_domain=system.cpu_clk_domain 297eventq_index=0 298is_stage2=false 299num_squash_per_cycle=2 300sys=system 301port=system.cpu.toL2Bus.slave[4] 302 303[system.cpu.checker.tracer] 304type=ExeTracer 305eventq_index=0 306 307[system.cpu.dcache] 308type=Cache 309children=tags 310addr_ranges=0:18446744073709551615 311assoc=2 312clk_domain=system.cpu_clk_domain 313clusivity=mostly_incl 314demand_mshr_reserve=1 315eventq_index=0 316forward_snoops=true 317hit_latency=2 318is_read_only=false 319max_miss_count=0 320mshrs=4 321prefetch_on_access=false 322prefetcher=Null 323response_latency=2 324sequential_access=false 325size=262144 326system=system 327tags=system.cpu.dcache.tags 328tgts_per_mshr=20 329write_buffers=8 330writeback_clean=false 331cpu_side=system.cpu.dcache_port 332mem_side=system.cpu.toL2Bus.slave[1] 333 334[system.cpu.dcache.tags] 335type=LRU 336assoc=2 337block_size=64 338clk_domain=system.cpu_clk_domain 339eventq_index=0 340hit_latency=2 341sequential_access=false 342size=262144 343 344[system.cpu.dstage2_mmu] 345type=ArmStage2MMU 346children=stage2_tlb 347eventq_index=0 348stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 349sys=system 350tlb=system.cpu.dtb 351 352[system.cpu.dstage2_mmu.stage2_tlb] 353type=ArmTLB 354children=walker 355eventq_index=0 356is_stage2=true 357size=32 358walker=system.cpu.dstage2_mmu.stage2_tlb.walker 359 360[system.cpu.dstage2_mmu.stage2_tlb.walker] 361type=ArmTableWalker 362clk_domain=system.cpu_clk_domain 363eventq_index=0 364is_stage2=true 365num_squash_per_cycle=2 366sys=system 367 368[system.cpu.dtb] 369type=ArmTLB 370children=walker 371eventq_index=0 372is_stage2=false 373size=64 374walker=system.cpu.dtb.walker 375 376[system.cpu.dtb.walker] 377type=ArmTableWalker 378clk_domain=system.cpu_clk_domain 379eventq_index=0 380is_stage2=false 381num_squash_per_cycle=2 382sys=system 383port=system.cpu.toL2Bus.slave[3] 384 385[system.cpu.fuPool] 386type=FUPool 387children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 388FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 389eventq_index=0 390 391[system.cpu.fuPool.FUList0] 392type=FUDesc 393children=opList 394count=6 395eventq_index=0 396opList=system.cpu.fuPool.FUList0.opList 397 398[system.cpu.fuPool.FUList0.opList] 399type=OpDesc 400eventq_index=0 401opClass=IntAlu 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList1] 406type=FUDesc 407children=opList0 opList1 408count=2 409eventq_index=0 410opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 411 412[system.cpu.fuPool.FUList1.opList0] 413type=OpDesc 414eventq_index=0 415opClass=IntMult 416opLat=3 417pipelined=true 418 419[system.cpu.fuPool.FUList1.opList1] 420type=OpDesc 421eventq_index=0 422opClass=IntDiv 423opLat=20 424pipelined=false 425 426[system.cpu.fuPool.FUList2] 427type=FUDesc 428children=opList0 opList1 opList2 429count=4 430eventq_index=0 431opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 432 433[system.cpu.fuPool.FUList2.opList0] 434type=OpDesc 435eventq_index=0 436opClass=FloatAdd 437opLat=2 438pipelined=true 439 440[system.cpu.fuPool.FUList2.opList1] 441type=OpDesc 442eventq_index=0 443opClass=FloatCmp 444opLat=2 445pipelined=true 446 447[system.cpu.fuPool.FUList2.opList2] 448type=OpDesc 449eventq_index=0 450opClass=FloatCvt 451opLat=2 452pipelined=true 453 454[system.cpu.fuPool.FUList3] 455type=FUDesc 456children=opList0 opList1 opList2 457count=2 458eventq_index=0 459opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 460 461[system.cpu.fuPool.FUList3.opList0] 462type=OpDesc 463eventq_index=0 464opClass=FloatMult 465opLat=4 466pipelined=true 467 468[system.cpu.fuPool.FUList3.opList1] 469type=OpDesc 470eventq_index=0 471opClass=FloatDiv 472opLat=12 473pipelined=false 474 475[system.cpu.fuPool.FUList3.opList2] 476type=OpDesc 477eventq_index=0 478opClass=FloatSqrt 479opLat=24 480pipelined=false 481 482[system.cpu.fuPool.FUList4] 483type=FUDesc 484children=opList 485count=0 486eventq_index=0 487opList=system.cpu.fuPool.FUList4.opList 488 489[system.cpu.fuPool.FUList4.opList] 490type=OpDesc 491eventq_index=0 492opClass=MemRead 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5] 497type=FUDesc 498children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 499count=4 500eventq_index=0 501opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 502 503[system.cpu.fuPool.FUList5.opList00] 504type=OpDesc 505eventq_index=0 506opClass=SimdAdd 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList5.opList01] 511type=OpDesc 512eventq_index=0 513opClass=SimdAddAcc 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList5.opList02] 518type=OpDesc 519eventq_index=0 520opClass=SimdAlu 521opLat=1 522pipelined=true 523 524[system.cpu.fuPool.FUList5.opList03] 525type=OpDesc 526eventq_index=0 527opClass=SimdCmp 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList5.opList04] 532type=OpDesc 533eventq_index=0 534opClass=SimdCvt 535opLat=1 536pipelined=true 537 538[system.cpu.fuPool.FUList5.opList05] 539type=OpDesc 540eventq_index=0 541opClass=SimdMisc 542opLat=1 543pipelined=true 544 545[system.cpu.fuPool.FUList5.opList06] 546type=OpDesc 547eventq_index=0 548opClass=SimdMult 549opLat=1 550pipelined=true 551 552[system.cpu.fuPool.FUList5.opList07] 553type=OpDesc 554eventq_index=0 555opClass=SimdMultAcc 556opLat=1 557pipelined=true 558 559[system.cpu.fuPool.FUList5.opList08] 560type=OpDesc 561eventq_index=0 562opClass=SimdShift 563opLat=1 564pipelined=true 565 566[system.cpu.fuPool.FUList5.opList09] 567type=OpDesc 568eventq_index=0 569opClass=SimdShiftAcc 570opLat=1 571pipelined=true 572 573[system.cpu.fuPool.FUList5.opList10] 574type=OpDesc 575eventq_index=0 576opClass=SimdSqrt 577opLat=1 578pipelined=true 579 580[system.cpu.fuPool.FUList5.opList11] 581type=OpDesc 582eventq_index=0 583opClass=SimdFloatAdd 584opLat=1 585pipelined=true 586 587[system.cpu.fuPool.FUList5.opList12] 588type=OpDesc 589eventq_index=0 590opClass=SimdFloatAlu 591opLat=1 592pipelined=true 593 594[system.cpu.fuPool.FUList5.opList13] 595type=OpDesc 596eventq_index=0 597opClass=SimdFloatCmp 598opLat=1 599pipelined=true 600 601[system.cpu.fuPool.FUList5.opList14] 602type=OpDesc 603eventq_index=0 604opClass=SimdFloatCvt 605opLat=1 606pipelined=true 607 608[system.cpu.fuPool.FUList5.opList15] 609type=OpDesc 610eventq_index=0 611opClass=SimdFloatDiv 612opLat=1 613pipelined=true 614 615[system.cpu.fuPool.FUList5.opList16] 616type=OpDesc 617eventq_index=0 618opClass=SimdFloatMisc 619opLat=1 620pipelined=true 621 622[system.cpu.fuPool.FUList5.opList17] 623type=OpDesc 624eventq_index=0 625opClass=SimdFloatMult 626opLat=1 627pipelined=true 628 629[system.cpu.fuPool.FUList5.opList18] 630type=OpDesc 631eventq_index=0 632opClass=SimdFloatMultAcc 633opLat=1 634pipelined=true 635 636[system.cpu.fuPool.FUList5.opList19] 637type=OpDesc 638eventq_index=0 639opClass=SimdFloatSqrt 640opLat=1 641pipelined=true 642 643[system.cpu.fuPool.FUList6] 644type=FUDesc 645children=opList 646count=0 647eventq_index=0 648opList=system.cpu.fuPool.FUList6.opList 649 650[system.cpu.fuPool.FUList6.opList] 651type=OpDesc 652eventq_index=0 653opClass=MemWrite 654opLat=1 655pipelined=true 656 657[system.cpu.fuPool.FUList7] 658type=FUDesc 659children=opList0 opList1 660count=4 661eventq_index=0 662opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 663 664[system.cpu.fuPool.FUList7.opList0] 665type=OpDesc 666eventq_index=0 667opClass=MemRead 668opLat=1 669pipelined=true 670 671[system.cpu.fuPool.FUList7.opList1] 672type=OpDesc 673eventq_index=0 674opClass=MemWrite 675opLat=1 676pipelined=true 677 678[system.cpu.fuPool.FUList8] 679type=FUDesc 680children=opList 681count=1 682eventq_index=0 683opList=system.cpu.fuPool.FUList8.opList 684 685[system.cpu.fuPool.FUList8.opList] 686type=OpDesc 687eventq_index=0 688opClass=IprAccess 689opLat=3 690pipelined=false 691 692[system.cpu.icache] 693type=Cache 694children=tags 695addr_ranges=0:18446744073709551615 696assoc=2 697clk_domain=system.cpu_clk_domain 698clusivity=mostly_incl 699demand_mshr_reserve=1 700eventq_index=0 701forward_snoops=true 702hit_latency=2 703is_read_only=true 704max_miss_count=0 705mshrs=4 706prefetch_on_access=false 707prefetcher=Null 708response_latency=2 709sequential_access=false 710size=131072 711system=system 712tags=system.cpu.icache.tags 713tgts_per_mshr=20 714write_buffers=8 715writeback_clean=true 716cpu_side=system.cpu.icache_port 717mem_side=system.cpu.toL2Bus.slave[0] 718 719[system.cpu.icache.tags] 720type=LRU 721assoc=2 722block_size=64 723clk_domain=system.cpu_clk_domain 724eventq_index=0 725hit_latency=2 726sequential_access=false 727size=131072 728 729[system.cpu.interrupts] 730type=ArmInterrupts 731eventq_index=0 732 733[system.cpu.isa] 734type=ArmISA 735decoderFlavour=Generic 736eventq_index=0 737fpsid=1090793632 738id_aa64afr0_el1=0 739id_aa64afr1_el1=0 740id_aa64dfr0_el1=1052678 741id_aa64dfr1_el1=0 742id_aa64isar0_el1=0 743id_aa64isar1_el1=0 744id_aa64mmfr0_el1=15728642 745id_aa64mmfr1_el1=0 746id_aa64pfr0_el1=17 747id_aa64pfr1_el1=0 748id_isar0=34607377 749id_isar1=34677009 750id_isar2=555950401 751id_isar3=17899825 752id_isar4=268501314 753id_isar5=0 754id_mmfr0=270536963 755id_mmfr1=0 756id_mmfr2=19070976 757id_mmfr3=34611729 758id_pfr0=49 759id_pfr1=4113 760midr=1091551472 761pmu=Null 762system=system 763 764[system.cpu.istage2_mmu] 765type=ArmStage2MMU 766children=stage2_tlb 767eventq_index=0 768stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 769sys=system 770tlb=system.cpu.itb 771 772[system.cpu.istage2_mmu.stage2_tlb] 773type=ArmTLB 774children=walker 775eventq_index=0 776is_stage2=true 777size=32 778walker=system.cpu.istage2_mmu.stage2_tlb.walker 779 780[system.cpu.istage2_mmu.stage2_tlb.walker] 781type=ArmTableWalker 782clk_domain=system.cpu_clk_domain 783eventq_index=0 784is_stage2=true 785num_squash_per_cycle=2 786sys=system 787 788[system.cpu.itb] 789type=ArmTLB 790children=walker 791eventq_index=0 792is_stage2=false 793size=64 794walker=system.cpu.itb.walker 795 796[system.cpu.itb.walker] 797type=ArmTableWalker 798clk_domain=system.cpu_clk_domain 799eventq_index=0 800is_stage2=false 801num_squash_per_cycle=2 802sys=system 803port=system.cpu.toL2Bus.slave[2] 804 805[system.cpu.l2cache] 806type=Cache 807children=tags 808addr_ranges=0:18446744073709551615 809assoc=8 810clk_domain=system.cpu_clk_domain 811clusivity=mostly_incl 812demand_mshr_reserve=1 813eventq_index=0 814forward_snoops=true 815hit_latency=20 816is_read_only=false 817max_miss_count=0 818mshrs=20 819prefetch_on_access=false 820prefetcher=Null 821response_latency=20 822sequential_access=false 823size=2097152 824system=system 825tags=system.cpu.l2cache.tags 826tgts_per_mshr=12 827write_buffers=8 828writeback_clean=false 829cpu_side=system.cpu.toL2Bus.master[0] 830mem_side=system.membus.slave[1] 831 832[system.cpu.l2cache.tags] 833type=LRU 834assoc=8 835block_size=64 836clk_domain=system.cpu_clk_domain 837eventq_index=0 838hit_latency=20 839sequential_access=false 840size=2097152 841 842[system.cpu.toL2Bus] 843type=CoherentXBar 844children=snoop_filter 845clk_domain=system.cpu_clk_domain 846eventq_index=0 847forward_latency=0 848frontend_latency=1 849response_latency=1 850snoop_filter=system.cpu.toL2Bus.snoop_filter 851snoop_response_latency=1 852system=system 853use_default_range=false 854width=32 855master=system.cpu.l2cache.cpu_side 856slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port 857 858[system.cpu.toL2Bus.snoop_filter] 859type=SnoopFilter 860eventq_index=0 861lookup_latency=0 862max_capacity=8388608 863system=system 864 865[system.cpu.tracer] 866type=ExeTracer 867eventq_index=0 868 869[system.cpu.workload] 870type=LiveProcess 871cmd=hello 872cwd= 873drivers= 874egid=100 875env= 876errout=cerr 877euid=100 878eventq_index=0
879executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello	879executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
880gid=100 881input=cin 882kvmInSE=false 883max_stack_size=67108864 884output=cout 885pid=100 886ppid=99 887simpoint=0 888system=system 889uid=100 890useArchPT=false 891 892[system.cpu_clk_domain] 893type=SrcClockDomain 894clock=500 895domain_id=-1 896eventq_index=0 897init_perf_level=0 898voltage_domain=system.voltage_domain 899 900[system.dvfs_handler] 901type=DVFSHandler 902domains= 903enable=false 904eventq_index=0 905sys_clk_domain=system.clk_domain 906transition_latency=100000000 907 908[system.membus] 909type=CoherentXBar 910clk_domain=system.clk_domain 911eventq_index=0 912forward_latency=4 913frontend_latency=3 914response_latency=2 915snoop_filter=Null 916snoop_response_latency=4 917system=system 918use_default_range=false 919width=16 920master=system.physmem.port 921slave=system.system_port system.cpu.l2cache.mem_side 922 923[system.physmem] 924type=DRAMCtrl 925IDD0=0.075000 926IDD02=0.000000 927IDD2N=0.050000 928IDD2N2=0.000000 929IDD2P0=0.000000 930IDD2P02=0.000000 931IDD2P1=0.000000 932IDD2P12=0.000000 933IDD3N=0.057000 934IDD3N2=0.000000 935IDD3P0=0.000000 936IDD3P02=0.000000 937IDD3P1=0.000000 938IDD3P12=0.000000 939IDD4R=0.187000 940IDD4R2=0.000000 941IDD4W=0.165000 942IDD4W2=0.000000 943IDD5=0.220000 944IDD52=0.000000 945IDD6=0.000000 946IDD62=0.000000 947VDD=1.500000 948VDD2=0.000000 949activation_limit=4 950addr_mapping=RoRaBaCoCh 951bank_groups_per_rank=0 952banks_per_rank=8 953burst_length=8 954channels=1 955clk_domain=system.clk_domain 956conf_table_reported=true 957device_bus_width=8 958device_rowbuffer_size=1024 959device_size=536870912 960devices_per_rank=8 961dll=true 962eventq_index=0 963in_addr_map=true 964max_accesses_per_row=16 965mem_sched_policy=frfcfs 966min_writes_per_switch=16 967null=false 968page_policy=open_adaptive 969range=0:134217727 970ranks_per_channel=2 971read_buffer_size=32 972static_backend_latency=10000 973static_frontend_latency=10000 974tBURST=5000 975tCCD_L=0 976tCK=1250 977tCL=13750 978tCS=2500 979tRAS=35000 980tRCD=13750 981tREFI=7800000 982tRFC=260000 983tRP=13750 984tRRD=6000 985tRRD_L=0 986tRTP=7500 987tRTW=2500 988tWR=15000 989tWTR=7500 990tXAW=30000 991tXP=0 992tXPDLL=0 993tXS=0 994tXSDLL=0 995write_buffer_size=64 996write_high_thresh_perc=85 997write_low_thresh_perc=50 998port=system.membus.master[0] 999 1000[system.voltage_domain] 1001type=VoltageDomain 1002eventq_index=0 1003voltage=1.000000 1004	880gid=100 881input=cin 882kvmInSE=false 883max_stack_size=67108864 884output=cout 885pid=100 886ppid=99 887simpoint=0 888system=system 889uid=100 890useArchPT=false 891 892[system.cpu_clk_domain] 893type=SrcClockDomain 894clock=500 895domain_id=-1 896eventq_index=0 897init_perf_level=0 898voltage_domain=system.voltage_domain 899 900[system.dvfs_handler] 901type=DVFSHandler 902domains= 903enable=false 904eventq_index=0 905sys_clk_domain=system.clk_domain 906transition_latency=100000000 907 908[system.membus] 909type=CoherentXBar 910clk_domain=system.clk_domain 911eventq_index=0 912forward_latency=4 913frontend_latency=3 914response_latency=2 915snoop_filter=Null 916snoop_response_latency=4 917system=system 918use_default_range=false 919width=16 920master=system.physmem.port 921slave=system.system_port system.cpu.l2cache.mem_side 922 923[system.physmem] 924type=DRAMCtrl 925IDD0=0.075000 926IDD02=0.000000 927IDD2N=0.050000 928IDD2N2=0.000000 929IDD2P0=0.000000 930IDD2P02=0.000000 931IDD2P1=0.000000 932IDD2P12=0.000000 933IDD3N=0.057000 934IDD3N2=0.000000 935IDD3P0=0.000000 936IDD3P02=0.000000 937IDD3P1=0.000000 938IDD3P12=0.000000 939IDD4R=0.187000 940IDD4R2=0.000000 941IDD4W=0.165000 942IDD4W2=0.000000 943IDD5=0.220000 944IDD52=0.000000 945IDD6=0.000000 946IDD62=0.000000 947VDD=1.500000 948VDD2=0.000000 949activation_limit=4 950addr_mapping=RoRaBaCoCh 951bank_groups_per_rank=0 952banks_per_rank=8 953burst_length=8 954channels=1 955clk_domain=system.clk_domain 956conf_table_reported=true 957device_bus_width=8 958device_rowbuffer_size=1024 959device_size=536870912 960devices_per_rank=8 961dll=true 962eventq_index=0 963in_addr_map=true 964max_accesses_per_row=16 965mem_sched_policy=frfcfs 966min_writes_per_switch=16 967null=false 968page_policy=open_adaptive 969range=0:134217727 970ranks_per_channel=2 971read_buffer_size=32 972static_backend_latency=10000 973static_frontend_latency=10000 974tBURST=5000 975tCCD_L=0 976tCK=1250 977tCL=13750 978tCS=2500 979tRAS=35000 980tRCD=13750 981tREFI=7800000 982tRFC=260000 983tRP=13750 984tRRD=6000 985tRRD_L=0 986tRTP=7500 987tRTW=2500 988tWR=15000 989tWTR=7500 990tXAW=30000 991tXP=0 992tXPDLL=0 993tXS=0 994tXSDLL=0 995write_buffer_size=64 996write_high_thresh_perc=85 997write_low_thresh_perc=50 998port=system.membus.master[0] 999 1000[system.voltage_domain] 1001type=VoltageDomain 1002eventq_index=0 1003voltage=1.000000 1004