Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

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config.ini (10451:3a87241adfb8)	config.ini (10736:4433fb00fa7d)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem
	26mmap_using_noreserve=false
26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=system.cpu.checker 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dstage2_mmu=system.cpu.dstage2_mmu 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94istage2_mmu=system.cpu.istage2_mmu 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=1280 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=tournament 153 154[system.cpu.checker] 155type=O3Checker 156children=dstage2_mmu dtb isa istage2_mmu itb tracer 157checker=Null 158clk_domain=system.cpu_clk_domain 159cpu_id=0 160do_checkpoint_insts=true 161do_quiesce=true 162do_statistics_insts=true 163dstage2_mmu=system.cpu.checker.dstage2_mmu 164dtb=system.cpu.checker.dtb 165eventq_index=0 166exitOnError=false 167function_trace=false 168function_trace_start=0 169interrupts=Null 170isa=system.cpu.checker.isa 171istage2_mmu=system.cpu.checker.istage2_mmu 172itb=system.cpu.checker.itb 173max_insts_all_threads=0 174max_insts_any_thread=0 175max_loads_all_threads=0 176max_loads_any_thread=0 177numThreads=1 178profile=0 179progress_interval=0 180simpoint_start_insts= 181socket_id=0 182switched_out=false 183system=system 184tracer=system.cpu.checker.tracer 185updateOnError=true 186warnOnlyOnLoadError=true 187workload=system.cpu.workload 188 189[system.cpu.checker.dstage2_mmu] 190type=ArmStage2MMU 191children=stage2_tlb 192eventq_index=0 193stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb	27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=system.cpu.checker 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=64 103numPhysCCRegs=1280 104numPhysFloatRegs=256 105numPhysIntRegs=256 106numROBEntries=192 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=2 114renameToROBDelay=1 115renameWidth=8 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=BranchPredictor 140BTBEntries=4096 141BTBTagSize=16 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149localCtrBits=2 150localHistoryTableSize=2048 151localPredictorSize=2048 152numThreads=1 153predType=tournament 154 155[system.cpu.checker] 156type=O3Checker 157children=dstage2_mmu dtb isa istage2_mmu itb tracer 158checker=Null 159clk_domain=system.cpu_clk_domain 160cpu_id=0 161do_checkpoint_insts=true 162do_quiesce=true 163do_statistics_insts=true 164dstage2_mmu=system.cpu.checker.dstage2_mmu 165dtb=system.cpu.checker.dtb 166eventq_index=0 167exitOnError=false 168function_trace=false 169function_trace_start=0 170interrupts=Null 171isa=system.cpu.checker.isa 172istage2_mmu=system.cpu.checker.istage2_mmu 173itb=system.cpu.checker.itb 174max_insts_all_threads=0 175max_insts_any_thread=0 176max_loads_all_threads=0 177max_loads_any_thread=0 178numThreads=1 179profile=0 180progress_interval=0 181simpoint_start_insts= 182socket_id=0 183switched_out=false 184system=system 185tracer=system.cpu.checker.tracer 186updateOnError=true 187warnOnlyOnLoadError=true 188workload=system.cpu.workload 189 190[system.cpu.checker.dstage2_mmu] 191type=ArmStage2MMU 192children=stage2_tlb 193eventq_index=0 194stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
	195sys=system
194tlb=system.cpu.checker.dtb 195 196[system.cpu.checker.dstage2_mmu.stage2_tlb] 197type=ArmTLB 198children=walker 199eventq_index=0 200is_stage2=true 201size=32 202walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 203 204[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 205type=ArmTableWalker 206clk_domain=system.cpu_clk_domain 207eventq_index=0 208is_stage2=true 209num_squash_per_cycle=2 210sys=system	196tlb=system.cpu.checker.dtb 197 198[system.cpu.checker.dstage2_mmu.stage2_tlb] 199type=ArmTLB 200children=walker 201eventq_index=0 202is_stage2=true 203size=32 204walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 205 206[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 207type=ArmTableWalker 208clk_domain=system.cpu_clk_domain 209eventq_index=0 210is_stage2=true 211num_squash_per_cycle=2 212sys=system
211port=system.cpu.toL2Bus.slave[9]
212 213[system.cpu.checker.dtb] 214type=ArmTLB 215children=walker 216eventq_index=0 217is_stage2=false 218size=64 219walker=system.cpu.checker.dtb.walker 220 221[system.cpu.checker.dtb.walker] 222type=ArmTableWalker 223clk_domain=system.cpu_clk_domain 224eventq_index=0 225is_stage2=false 226num_squash_per_cycle=2 227sys=system	213 214[system.cpu.checker.dtb] 215type=ArmTLB 216children=walker 217eventq_index=0 218is_stage2=false 219size=64 220walker=system.cpu.checker.dtb.walker 221 222[system.cpu.checker.dtb.walker] 223type=ArmTableWalker 224clk_domain=system.cpu_clk_domain 225eventq_index=0 226is_stage2=false 227num_squash_per_cycle=2 228sys=system
228port=system.cpu.toL2Bus.slave[7]	229port=system.cpu.toL2Bus.slave[5]
229 230[system.cpu.checker.isa] 231type=ArmISA 232eventq_index=0 233fpsid=1090793632 234id_aa64afr0_el1=0 235id_aa64afr1_el1=0 236id_aa64dfr0_el1=1052678 237id_aa64dfr1_el1=0 238id_aa64isar0_el1=0 239id_aa64isar1_el1=0 240id_aa64mmfr0_el1=15728642 241id_aa64mmfr1_el1=0 242id_aa64pfr0_el1=17 243id_aa64pfr1_el1=0 244id_isar0=34607377 245id_isar1=34677009 246id_isar2=555950401 247id_isar3=17899825 248id_isar4=268501314 249id_isar5=0 250id_mmfr0=270536963 251id_mmfr1=0 252id_mmfr2=19070976 253id_mmfr3=34611729 254id_pfr0=49 255id_pfr1=4113 256midr=1091551472	230 231[system.cpu.checker.isa] 232type=ArmISA 233eventq_index=0 234fpsid=1090793632 235id_aa64afr0_el1=0 236id_aa64afr1_el1=0 237id_aa64dfr0_el1=1052678 238id_aa64dfr1_el1=0 239id_aa64isar0_el1=0 240id_aa64isar1_el1=0 241id_aa64mmfr0_el1=15728642 242id_aa64mmfr1_el1=0 243id_aa64pfr0_el1=17 244id_aa64pfr1_el1=0 245id_isar0=34607377 246id_isar1=34677009 247id_isar2=555950401 248id_isar3=17899825 249id_isar4=268501314 250id_isar5=0 251id_mmfr0=270536963 252id_mmfr1=0 253id_mmfr2=19070976 254id_mmfr3=34611729 255id_pfr0=49 256id_pfr1=4113 257midr=1091551472
	258pmu=Null
257system=system 258 259[system.cpu.checker.istage2_mmu] 260type=ArmStage2MMU 261children=stage2_tlb 262eventq_index=0 263stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb	259system=system 260 261[system.cpu.checker.istage2_mmu] 262type=ArmStage2MMU 263children=stage2_tlb 264eventq_index=0 265stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
	266sys=system
264tlb=system.cpu.checker.itb 265 266[system.cpu.checker.istage2_mmu.stage2_tlb] 267type=ArmTLB 268children=walker 269eventq_index=0 270is_stage2=true 271size=32 272walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 273 274[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 275type=ArmTableWalker 276clk_domain=system.cpu_clk_domain 277eventq_index=0 278is_stage2=true 279num_squash_per_cycle=2 280sys=system	267tlb=system.cpu.checker.itb 268 269[system.cpu.checker.istage2_mmu.stage2_tlb] 270type=ArmTLB 271children=walker 272eventq_index=0 273is_stage2=true 274size=32 275walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 276 277[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 278type=ArmTableWalker 279clk_domain=system.cpu_clk_domain 280eventq_index=0 281is_stage2=true 282num_squash_per_cycle=2 283sys=system
281port=system.cpu.toL2Bus.slave[8]
282 283[system.cpu.checker.itb] 284type=ArmTLB 285children=walker 286eventq_index=0 287is_stage2=false 288size=64 289walker=system.cpu.checker.itb.walker 290 291[system.cpu.checker.itb.walker] 292type=ArmTableWalker 293clk_domain=system.cpu_clk_domain 294eventq_index=0 295is_stage2=false 296num_squash_per_cycle=2 297sys=system	284 285[system.cpu.checker.itb] 286type=ArmTLB 287children=walker 288eventq_index=0 289is_stage2=false 290size=64 291walker=system.cpu.checker.itb.walker 292 293[system.cpu.checker.itb.walker] 294type=ArmTableWalker 295clk_domain=system.cpu_clk_domain 296eventq_index=0 297is_stage2=false 298num_squash_per_cycle=2 299sys=system
298port=system.cpu.toL2Bus.slave[6]	300port=system.cpu.toL2Bus.slave[4]
299 300[system.cpu.checker.tracer] 301type=ExeTracer 302eventq_index=0 303 304[system.cpu.dcache] 305type=BaseCache 306children=tags 307addr_ranges=0:18446744073709551615 308assoc=2 309clk_domain=system.cpu_clk_domain	301 302[system.cpu.checker.tracer] 303type=ExeTracer 304eventq_index=0 305 306[system.cpu.dcache] 307type=BaseCache 308children=tags 309addr_ranges=0:18446744073709551615 310assoc=2 311clk_domain=system.cpu_clk_domain
	312demand_mshr_reserve=1
310eventq_index=0 311forward_snoops=true 312hit_latency=2 313is_top_level=true 314max_miss_count=0 315mshrs=4 316prefetch_on_access=false 317prefetcher=Null 318response_latency=2 319sequential_access=false 320size=262144 321system=system 322tags=system.cpu.dcache.tags 323tgts_per_mshr=20 324two_queue=false 325write_buffers=8 326cpu_side=system.cpu.dcache_port 327mem_side=system.cpu.toL2Bus.slave[1] 328 329[system.cpu.dcache.tags] 330type=LRU 331assoc=2 332block_size=64 333clk_domain=system.cpu_clk_domain 334eventq_index=0 335hit_latency=2 336sequential_access=false 337size=262144 338 339[system.cpu.dstage2_mmu] 340type=ArmStage2MMU 341children=stage2_tlb 342eventq_index=0 343stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb	313eventq_index=0 314forward_snoops=true 315hit_latency=2 316is_top_level=true 317max_miss_count=0 318mshrs=4 319prefetch_on_access=false 320prefetcher=Null 321response_latency=2 322sequential_access=false 323size=262144 324system=system 325tags=system.cpu.dcache.tags 326tgts_per_mshr=20 327two_queue=false 328write_buffers=8 329cpu_side=system.cpu.dcache_port 330mem_side=system.cpu.toL2Bus.slave[1] 331 332[system.cpu.dcache.tags] 333type=LRU 334assoc=2 335block_size=64 336clk_domain=system.cpu_clk_domain 337eventq_index=0 338hit_latency=2 339sequential_access=false 340size=262144 341 342[system.cpu.dstage2_mmu] 343type=ArmStage2MMU 344children=stage2_tlb 345eventq_index=0 346stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
	347sys=system
344tlb=system.cpu.dtb 345 346[system.cpu.dstage2_mmu.stage2_tlb] 347type=ArmTLB 348children=walker 349eventq_index=0 350is_stage2=true 351size=32 352walker=system.cpu.dstage2_mmu.stage2_tlb.walker 353 354[system.cpu.dstage2_mmu.stage2_tlb.walker] 355type=ArmTableWalker 356clk_domain=system.cpu_clk_domain 357eventq_index=0 358is_stage2=true 359num_squash_per_cycle=2 360sys=system	348tlb=system.cpu.dtb 349 350[system.cpu.dstage2_mmu.stage2_tlb] 351type=ArmTLB 352children=walker 353eventq_index=0 354is_stage2=true 355size=32 356walker=system.cpu.dstage2_mmu.stage2_tlb.walker 357 358[system.cpu.dstage2_mmu.stage2_tlb.walker] 359type=ArmTableWalker 360clk_domain=system.cpu_clk_domain 361eventq_index=0 362is_stage2=true 363num_squash_per_cycle=2 364sys=system
361port=system.cpu.toL2Bus.slave[5]
362 363[system.cpu.dtb] 364type=ArmTLB 365children=walker 366eventq_index=0 367is_stage2=false 368size=64 369walker=system.cpu.dtb.walker 370 371[system.cpu.dtb.walker] 372type=ArmTableWalker 373clk_domain=system.cpu_clk_domain 374eventq_index=0 375is_stage2=false 376num_squash_per_cycle=2 377sys=system 378port=system.cpu.toL2Bus.slave[3] 379 380[system.cpu.fuPool] 381type=FUPool 382children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 383FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 384eventq_index=0 385 386[system.cpu.fuPool.FUList0] 387type=FUDesc 388children=opList 389count=6 390eventq_index=0 391opList=system.cpu.fuPool.FUList0.opList 392 393[system.cpu.fuPool.FUList0.opList] 394type=OpDesc 395eventq_index=0 396issueLat=1 397opClass=IntAlu 398opLat=1 399 400[system.cpu.fuPool.FUList1] 401type=FUDesc 402children=opList0 opList1 403count=2 404eventq_index=0 405opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 406 407[system.cpu.fuPool.FUList1.opList0] 408type=OpDesc 409eventq_index=0 410issueLat=1 411opClass=IntMult 412opLat=3 413 414[system.cpu.fuPool.FUList1.opList1] 415type=OpDesc 416eventq_index=0 417issueLat=19 418opClass=IntDiv 419opLat=20 420 421[system.cpu.fuPool.FUList2] 422type=FUDesc 423children=opList0 opList1 opList2 424count=4 425eventq_index=0 426opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 427 428[system.cpu.fuPool.FUList2.opList0] 429type=OpDesc 430eventq_index=0 431issueLat=1 432opClass=FloatAdd 433opLat=2 434 435[system.cpu.fuPool.FUList2.opList1] 436type=OpDesc 437eventq_index=0 438issueLat=1 439opClass=FloatCmp 440opLat=2 441 442[system.cpu.fuPool.FUList2.opList2] 443type=OpDesc 444eventq_index=0 445issueLat=1 446opClass=FloatCvt 447opLat=2 448 449[system.cpu.fuPool.FUList3] 450type=FUDesc 451children=opList0 opList1 opList2 452count=2 453eventq_index=0 454opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 455 456[system.cpu.fuPool.FUList3.opList0] 457type=OpDesc 458eventq_index=0 459issueLat=1 460opClass=FloatMult 461opLat=4 462 463[system.cpu.fuPool.FUList3.opList1] 464type=OpDesc 465eventq_index=0 466issueLat=12 467opClass=FloatDiv 468opLat=12 469 470[system.cpu.fuPool.FUList3.opList2] 471type=OpDesc 472eventq_index=0 473issueLat=24 474opClass=FloatSqrt 475opLat=24 476 477[system.cpu.fuPool.FUList4] 478type=FUDesc 479children=opList 480count=0 481eventq_index=0 482opList=system.cpu.fuPool.FUList4.opList 483 484[system.cpu.fuPool.FUList4.opList] 485type=OpDesc 486eventq_index=0 487issueLat=1 488opClass=MemRead 489opLat=1 490 491[system.cpu.fuPool.FUList5] 492type=FUDesc 493children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 494count=4 495eventq_index=0 496opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 497 498[system.cpu.fuPool.FUList5.opList00] 499type=OpDesc 500eventq_index=0 501issueLat=1 502opClass=SimdAdd 503opLat=1 504 505[system.cpu.fuPool.FUList5.opList01] 506type=OpDesc 507eventq_index=0 508issueLat=1 509opClass=SimdAddAcc 510opLat=1 511 512[system.cpu.fuPool.FUList5.opList02] 513type=OpDesc 514eventq_index=0 515issueLat=1 516opClass=SimdAlu 517opLat=1 518 519[system.cpu.fuPool.FUList5.opList03] 520type=OpDesc 521eventq_index=0 522issueLat=1 523opClass=SimdCmp 524opLat=1 525 526[system.cpu.fuPool.FUList5.opList04] 527type=OpDesc 528eventq_index=0 529issueLat=1 530opClass=SimdCvt 531opLat=1 532 533[system.cpu.fuPool.FUList5.opList05] 534type=OpDesc 535eventq_index=0 536issueLat=1 537opClass=SimdMisc 538opLat=1 539 540[system.cpu.fuPool.FUList5.opList06] 541type=OpDesc 542eventq_index=0 543issueLat=1 544opClass=SimdMult 545opLat=1 546 547[system.cpu.fuPool.FUList5.opList07] 548type=OpDesc 549eventq_index=0 550issueLat=1 551opClass=SimdMultAcc 552opLat=1 553 554[system.cpu.fuPool.FUList5.opList08] 555type=OpDesc 556eventq_index=0 557issueLat=1 558opClass=SimdShift 559opLat=1 560 561[system.cpu.fuPool.FUList5.opList09] 562type=OpDesc 563eventq_index=0 564issueLat=1 565opClass=SimdShiftAcc 566opLat=1 567 568[system.cpu.fuPool.FUList5.opList10] 569type=OpDesc 570eventq_index=0 571issueLat=1 572opClass=SimdSqrt 573opLat=1 574 575[system.cpu.fuPool.FUList5.opList11] 576type=OpDesc 577eventq_index=0 578issueLat=1 579opClass=SimdFloatAdd 580opLat=1 581 582[system.cpu.fuPool.FUList5.opList12] 583type=OpDesc 584eventq_index=0 585issueLat=1 586opClass=SimdFloatAlu 587opLat=1 588 589[system.cpu.fuPool.FUList5.opList13] 590type=OpDesc 591eventq_index=0 592issueLat=1 593opClass=SimdFloatCmp 594opLat=1 595 596[system.cpu.fuPool.FUList5.opList14] 597type=OpDesc 598eventq_index=0 599issueLat=1 600opClass=SimdFloatCvt 601opLat=1 602 603[system.cpu.fuPool.FUList5.opList15] 604type=OpDesc 605eventq_index=0 606issueLat=1 607opClass=SimdFloatDiv 608opLat=1 609 610[system.cpu.fuPool.FUList5.opList16] 611type=OpDesc 612eventq_index=0 613issueLat=1 614opClass=SimdFloatMisc 615opLat=1 616 617[system.cpu.fuPool.FUList5.opList17] 618type=OpDesc 619eventq_index=0 620issueLat=1 621opClass=SimdFloatMult 622opLat=1 623 624[system.cpu.fuPool.FUList5.opList18] 625type=OpDesc 626eventq_index=0 627issueLat=1 628opClass=SimdFloatMultAcc 629opLat=1 630 631[system.cpu.fuPool.FUList5.opList19] 632type=OpDesc 633eventq_index=0 634issueLat=1 635opClass=SimdFloatSqrt 636opLat=1 637 638[system.cpu.fuPool.FUList6] 639type=FUDesc 640children=opList 641count=0 642eventq_index=0 643opList=system.cpu.fuPool.FUList6.opList 644 645[system.cpu.fuPool.FUList6.opList] 646type=OpDesc 647eventq_index=0 648issueLat=1 649opClass=MemWrite 650opLat=1 651 652[system.cpu.fuPool.FUList7] 653type=FUDesc 654children=opList0 opList1 655count=4 656eventq_index=0 657opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 658 659[system.cpu.fuPool.FUList7.opList0] 660type=OpDesc 661eventq_index=0 662issueLat=1 663opClass=MemRead 664opLat=1 665 666[system.cpu.fuPool.FUList7.opList1] 667type=OpDesc 668eventq_index=0 669issueLat=1 670opClass=MemWrite 671opLat=1 672 673[system.cpu.fuPool.FUList8] 674type=FUDesc 675children=opList 676count=1 677eventq_index=0 678opList=system.cpu.fuPool.FUList8.opList 679 680[system.cpu.fuPool.FUList8.opList] 681type=OpDesc 682eventq_index=0 683issueLat=3 684opClass=IprAccess 685opLat=3 686 687[system.cpu.icache] 688type=BaseCache 689children=tags 690addr_ranges=0:18446744073709551615 691assoc=2 692clk_domain=system.cpu_clk_domain	365 366[system.cpu.dtb] 367type=ArmTLB 368children=walker 369eventq_index=0 370is_stage2=false 371size=64 372walker=system.cpu.dtb.walker 373 374[system.cpu.dtb.walker] 375type=ArmTableWalker 376clk_domain=system.cpu_clk_domain 377eventq_index=0 378is_stage2=false 379num_squash_per_cycle=2 380sys=system 381port=system.cpu.toL2Bus.slave[3] 382 383[system.cpu.fuPool] 384type=FUPool 385children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 386FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 387eventq_index=0 388 389[system.cpu.fuPool.FUList0] 390type=FUDesc 391children=opList 392count=6 393eventq_index=0 394opList=system.cpu.fuPool.FUList0.opList 395 396[system.cpu.fuPool.FUList0.opList] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=IntAlu 401opLat=1 402 403[system.cpu.fuPool.FUList1] 404type=FUDesc 405children=opList0 opList1 406count=2 407eventq_index=0 408opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 409 410[system.cpu.fuPool.FUList1.opList0] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=IntMult 415opLat=3 416 417[system.cpu.fuPool.FUList1.opList1] 418type=OpDesc 419eventq_index=0 420issueLat=19 421opClass=IntDiv 422opLat=20 423 424[system.cpu.fuPool.FUList2] 425type=FUDesc 426children=opList0 opList1 opList2 427count=4 428eventq_index=0 429opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 430 431[system.cpu.fuPool.FUList2.opList0] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=FloatAdd 436opLat=2 437 438[system.cpu.fuPool.FUList2.opList1] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=FloatCmp 443opLat=2 444 445[system.cpu.fuPool.FUList2.opList2] 446type=OpDesc 447eventq_index=0 448issueLat=1 449opClass=FloatCvt 450opLat=2 451 452[system.cpu.fuPool.FUList3] 453type=FUDesc 454children=opList0 opList1 opList2 455count=2 456eventq_index=0 457opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 458 459[system.cpu.fuPool.FUList3.opList0] 460type=OpDesc 461eventq_index=0 462issueLat=1 463opClass=FloatMult 464opLat=4 465 466[system.cpu.fuPool.FUList3.opList1] 467type=OpDesc 468eventq_index=0 469issueLat=12 470opClass=FloatDiv 471opLat=12 472 473[system.cpu.fuPool.FUList3.opList2] 474type=OpDesc 475eventq_index=0 476issueLat=24 477opClass=FloatSqrt 478opLat=24 479 480[system.cpu.fuPool.FUList4] 481type=FUDesc 482children=opList 483count=0 484eventq_index=0 485opList=system.cpu.fuPool.FUList4.opList 486 487[system.cpu.fuPool.FUList4.opList] 488type=OpDesc 489eventq_index=0 490issueLat=1 491opClass=MemRead 492opLat=1 493 494[system.cpu.fuPool.FUList5] 495type=FUDesc 496children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 497count=4 498eventq_index=0 499opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 500 501[system.cpu.fuPool.FUList5.opList00] 502type=OpDesc 503eventq_index=0 504issueLat=1 505opClass=SimdAdd 506opLat=1 507 508[system.cpu.fuPool.FUList5.opList01] 509type=OpDesc 510eventq_index=0 511issueLat=1 512opClass=SimdAddAcc 513opLat=1 514 515[system.cpu.fuPool.FUList5.opList02] 516type=OpDesc 517eventq_index=0 518issueLat=1 519opClass=SimdAlu 520opLat=1 521 522[system.cpu.fuPool.FUList5.opList03] 523type=OpDesc 524eventq_index=0 525issueLat=1 526opClass=SimdCmp 527opLat=1 528 529[system.cpu.fuPool.FUList5.opList04] 530type=OpDesc 531eventq_index=0 532issueLat=1 533opClass=SimdCvt 534opLat=1 535 536[system.cpu.fuPool.FUList5.opList05] 537type=OpDesc 538eventq_index=0 539issueLat=1 540opClass=SimdMisc 541opLat=1 542 543[system.cpu.fuPool.FUList5.opList06] 544type=OpDesc 545eventq_index=0 546issueLat=1 547opClass=SimdMult 548opLat=1 549 550[system.cpu.fuPool.FUList5.opList07] 551type=OpDesc 552eventq_index=0 553issueLat=1 554opClass=SimdMultAcc 555opLat=1 556 557[system.cpu.fuPool.FUList5.opList08] 558type=OpDesc 559eventq_index=0 560issueLat=1 561opClass=SimdShift 562opLat=1 563 564[system.cpu.fuPool.FUList5.opList09] 565type=OpDesc 566eventq_index=0 567issueLat=1 568opClass=SimdShiftAcc 569opLat=1 570 571[system.cpu.fuPool.FUList5.opList10] 572type=OpDesc 573eventq_index=0 574issueLat=1 575opClass=SimdSqrt 576opLat=1 577 578[system.cpu.fuPool.FUList5.opList11] 579type=OpDesc 580eventq_index=0 581issueLat=1 582opClass=SimdFloatAdd 583opLat=1 584 585[system.cpu.fuPool.FUList5.opList12] 586type=OpDesc 587eventq_index=0 588issueLat=1 589opClass=SimdFloatAlu 590opLat=1 591 592[system.cpu.fuPool.FUList5.opList13] 593type=OpDesc 594eventq_index=0 595issueLat=1 596opClass=SimdFloatCmp 597opLat=1 598 599[system.cpu.fuPool.FUList5.opList14] 600type=OpDesc 601eventq_index=0 602issueLat=1 603opClass=SimdFloatCvt 604opLat=1 605 606[system.cpu.fuPool.FUList5.opList15] 607type=OpDesc 608eventq_index=0 609issueLat=1 610opClass=SimdFloatDiv 611opLat=1 612 613[system.cpu.fuPool.FUList5.opList16] 614type=OpDesc 615eventq_index=0 616issueLat=1 617opClass=SimdFloatMisc 618opLat=1 619 620[system.cpu.fuPool.FUList5.opList17] 621type=OpDesc 622eventq_index=0 623issueLat=1 624opClass=SimdFloatMult 625opLat=1 626 627[system.cpu.fuPool.FUList5.opList18] 628type=OpDesc 629eventq_index=0 630issueLat=1 631opClass=SimdFloatMultAcc 632opLat=1 633 634[system.cpu.fuPool.FUList5.opList19] 635type=OpDesc 636eventq_index=0 637issueLat=1 638opClass=SimdFloatSqrt 639opLat=1 640 641[system.cpu.fuPool.FUList6] 642type=FUDesc 643children=opList 644count=0 645eventq_index=0 646opList=system.cpu.fuPool.FUList6.opList 647 648[system.cpu.fuPool.FUList6.opList] 649type=OpDesc 650eventq_index=0 651issueLat=1 652opClass=MemWrite 653opLat=1 654 655[system.cpu.fuPool.FUList7] 656type=FUDesc 657children=opList0 opList1 658count=4 659eventq_index=0 660opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 661 662[system.cpu.fuPool.FUList7.opList0] 663type=OpDesc 664eventq_index=0 665issueLat=1 666opClass=MemRead 667opLat=1 668 669[system.cpu.fuPool.FUList7.opList1] 670type=OpDesc 671eventq_index=0 672issueLat=1 673opClass=MemWrite 674opLat=1 675 676[system.cpu.fuPool.FUList8] 677type=FUDesc 678children=opList 679count=1 680eventq_index=0 681opList=system.cpu.fuPool.FUList8.opList 682 683[system.cpu.fuPool.FUList8.opList] 684type=OpDesc 685eventq_index=0 686issueLat=3 687opClass=IprAccess 688opLat=3 689 690[system.cpu.icache] 691type=BaseCache 692children=tags 693addr_ranges=0:18446744073709551615 694assoc=2 695clk_domain=system.cpu_clk_domain
	696demand_mshr_reserve=1
693eventq_index=0 694forward_snoops=true 695hit_latency=2 696is_top_level=true 697max_miss_count=0 698mshrs=4 699prefetch_on_access=false 700prefetcher=Null 701response_latency=2 702sequential_access=false 703size=131072 704system=system 705tags=system.cpu.icache.tags 706tgts_per_mshr=20 707two_queue=false 708write_buffers=8 709cpu_side=system.cpu.icache_port 710mem_side=system.cpu.toL2Bus.slave[0] 711 712[system.cpu.icache.tags] 713type=LRU 714assoc=2 715block_size=64 716clk_domain=system.cpu_clk_domain 717eventq_index=0 718hit_latency=2 719sequential_access=false 720size=131072 721 722[system.cpu.interrupts] 723type=ArmInterrupts 724eventq_index=0 725 726[system.cpu.isa] 727type=ArmISA 728eventq_index=0 729fpsid=1090793632 730id_aa64afr0_el1=0 731id_aa64afr1_el1=0 732id_aa64dfr0_el1=1052678 733id_aa64dfr1_el1=0 734id_aa64isar0_el1=0 735id_aa64isar1_el1=0 736id_aa64mmfr0_el1=15728642 737id_aa64mmfr1_el1=0 738id_aa64pfr0_el1=17 739id_aa64pfr1_el1=0 740id_isar0=34607377 741id_isar1=34677009 742id_isar2=555950401 743id_isar3=17899825 744id_isar4=268501314 745id_isar5=0 746id_mmfr0=270536963 747id_mmfr1=0 748id_mmfr2=19070976 749id_mmfr3=34611729 750id_pfr0=49 751id_pfr1=4113 752midr=1091551472	697eventq_index=0 698forward_snoops=true 699hit_latency=2 700is_top_level=true 701max_miss_count=0 702mshrs=4 703prefetch_on_access=false 704prefetcher=Null 705response_latency=2 706sequential_access=false 707size=131072 708system=system 709tags=system.cpu.icache.tags 710tgts_per_mshr=20 711two_queue=false 712write_buffers=8 713cpu_side=system.cpu.icache_port 714mem_side=system.cpu.toL2Bus.slave[0] 715 716[system.cpu.icache.tags] 717type=LRU 718assoc=2 719block_size=64 720clk_domain=system.cpu_clk_domain 721eventq_index=0 722hit_latency=2 723sequential_access=false 724size=131072 725 726[system.cpu.interrupts] 727type=ArmInterrupts 728eventq_index=0 729 730[system.cpu.isa] 731type=ArmISA 732eventq_index=0 733fpsid=1090793632 734id_aa64afr0_el1=0 735id_aa64afr1_el1=0 736id_aa64dfr0_el1=1052678 737id_aa64dfr1_el1=0 738id_aa64isar0_el1=0 739id_aa64isar1_el1=0 740id_aa64mmfr0_el1=15728642 741id_aa64mmfr1_el1=0 742id_aa64pfr0_el1=17 743id_aa64pfr1_el1=0 744id_isar0=34607377 745id_isar1=34677009 746id_isar2=555950401 747id_isar3=17899825 748id_isar4=268501314 749id_isar5=0 750id_mmfr0=270536963 751id_mmfr1=0 752id_mmfr2=19070976 753id_mmfr3=34611729 754id_pfr0=49 755id_pfr1=4113 756midr=1091551472
	757pmu=Null
753system=system 754 755[system.cpu.istage2_mmu] 756type=ArmStage2MMU 757children=stage2_tlb 758eventq_index=0 759stage2_tlb=system.cpu.istage2_mmu.stage2_tlb	758system=system 759 760[system.cpu.istage2_mmu] 761type=ArmStage2MMU 762children=stage2_tlb 763eventq_index=0 764stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
	765sys=system
760tlb=system.cpu.itb 761 762[system.cpu.istage2_mmu.stage2_tlb] 763type=ArmTLB 764children=walker 765eventq_index=0 766is_stage2=true 767size=32 768walker=system.cpu.istage2_mmu.stage2_tlb.walker 769 770[system.cpu.istage2_mmu.stage2_tlb.walker] 771type=ArmTableWalker 772clk_domain=system.cpu_clk_domain 773eventq_index=0 774is_stage2=true 775num_squash_per_cycle=2 776sys=system	766tlb=system.cpu.itb 767 768[system.cpu.istage2_mmu.stage2_tlb] 769type=ArmTLB 770children=walker 771eventq_index=0 772is_stage2=true 773size=32 774walker=system.cpu.istage2_mmu.stage2_tlb.walker 775 776[system.cpu.istage2_mmu.stage2_tlb.walker] 777type=ArmTableWalker 778clk_domain=system.cpu_clk_domain 779eventq_index=0 780is_stage2=true 781num_squash_per_cycle=2 782sys=system
777port=system.cpu.toL2Bus.slave[4]
778 779[system.cpu.itb] 780type=ArmTLB 781children=walker 782eventq_index=0 783is_stage2=false 784size=64 785walker=system.cpu.itb.walker 786 787[system.cpu.itb.walker] 788type=ArmTableWalker 789clk_domain=system.cpu_clk_domain 790eventq_index=0 791is_stage2=false 792num_squash_per_cycle=2 793sys=system 794port=system.cpu.toL2Bus.slave[2] 795 796[system.cpu.l2cache] 797type=BaseCache 798children=tags 799addr_ranges=0:18446744073709551615 800assoc=8 801clk_domain=system.cpu_clk_domain	783 784[system.cpu.itb] 785type=ArmTLB 786children=walker 787eventq_index=0 788is_stage2=false 789size=64 790walker=system.cpu.itb.walker 791 792[system.cpu.itb.walker] 793type=ArmTableWalker 794clk_domain=system.cpu_clk_domain 795eventq_index=0 796is_stage2=false 797num_squash_per_cycle=2 798sys=system 799port=system.cpu.toL2Bus.slave[2] 800 801[system.cpu.l2cache] 802type=BaseCache 803children=tags 804addr_ranges=0:18446744073709551615 805assoc=8 806clk_domain=system.cpu_clk_domain
	807demand_mshr_reserve=1
802eventq_index=0 803forward_snoops=true 804hit_latency=20 805is_top_level=false 806max_miss_count=0 807mshrs=20 808prefetch_on_access=false 809prefetcher=Null 810response_latency=20 811sequential_access=false 812size=2097152 813system=system 814tags=system.cpu.l2cache.tags 815tgts_per_mshr=12 816two_queue=false 817write_buffers=8 818cpu_side=system.cpu.toL2Bus.master[0] 819mem_side=system.membus.slave[1] 820 821[system.cpu.l2cache.tags] 822type=LRU 823assoc=8 824block_size=64 825clk_domain=system.cpu_clk_domain 826eventq_index=0 827hit_latency=20 828sequential_access=false 829size=2097152 830 831[system.cpu.toL2Bus] 832type=CoherentXBar 833clk_domain=system.cpu_clk_domain 834eventq_index=0	808eventq_index=0 809forward_snoops=true 810hit_latency=20 811is_top_level=false 812max_miss_count=0 813mshrs=20 814prefetch_on_access=false 815prefetcher=Null 816response_latency=20 817sequential_access=false 818size=2097152 819system=system 820tags=system.cpu.l2cache.tags 821tgts_per_mshr=12 822two_queue=false 823write_buffers=8 824cpu_side=system.cpu.toL2Bus.master[0] 825mem_side=system.membus.slave[1] 826 827[system.cpu.l2cache.tags] 828type=LRU 829assoc=8 830block_size=64 831clk_domain=system.cpu_clk_domain 832eventq_index=0 833hit_latency=20 834sequential_access=false 835size=2097152 836 837[system.cpu.toL2Bus] 838type=CoherentXBar 839clk_domain=system.cpu_clk_domain 840eventq_index=0
835header_cycles=1	841forward_latency=0 842frontend_latency=1 843response_latency=1
836snoop_filter=Null	844snoop_filter=Null
	845snoop_response_latency=1
837system=system 838use_default_range=false 839width=32 840master=system.cpu.l2cache.cpu_side	846system=system 847use_default_range=false 848width=32 849master=system.cpu.l2cache.cpu_side
841slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port	850slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
842 843[system.cpu.tracer] 844type=ExeTracer 845eventq_index=0 846 847[system.cpu.workload] 848type=LiveProcess 849cmd=hello 850cwd=	851 852[system.cpu.tracer] 853type=ExeTracer 854eventq_index=0 855 856[system.cpu.workload] 857type=LiveProcess 858cmd=hello 859cwd=
	860drivers=
851egid=100 852env= 853errout=cerr 854euid=100 855eventq_index=0 856executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 857gid=100 858input=cin	861egid=100 862env= 863errout=cerr 864euid=100 865eventq_index=0 866executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 867gid=100 868input=cin
	869kvmInSE=false
859max_stack_size=67108864 860output=cout 861pid=100 862ppid=99 863simpoint=0 864system=system 865uid=100 866useArchPT=false 867 868[system.cpu_clk_domain] 869type=SrcClockDomain 870clock=500 871domain_id=-1 872eventq_index=0 873init_perf_level=0 874voltage_domain=system.voltage_domain 875 876[system.dvfs_handler] 877type=DVFSHandler 878domains= 879enable=false 880eventq_index=0 881sys_clk_domain=system.clk_domain 882transition_latency=100000000 883 884[system.membus] 885type=CoherentXBar 886clk_domain=system.clk_domain 887eventq_index=0	870max_stack_size=67108864 871output=cout 872pid=100 873ppid=99 874simpoint=0 875system=system 876uid=100 877useArchPT=false 878 879[system.cpu_clk_domain] 880type=SrcClockDomain 881clock=500 882domain_id=-1 883eventq_index=0 884init_perf_level=0 885voltage_domain=system.voltage_domain 886 887[system.dvfs_handler] 888type=DVFSHandler 889domains= 890enable=false 891eventq_index=0 892sys_clk_domain=system.clk_domain 893transition_latency=100000000 894 895[system.membus] 896type=CoherentXBar 897clk_domain=system.clk_domain 898eventq_index=0
888header_cycles=1	899forward_latency=4 900frontend_latency=3 901response_latency=2
889snoop_filter=Null	902snoop_filter=Null
	903snoop_response_latency=4
890system=system 891use_default_range=false	904system=system 905use_default_range=false
892width=8	906width=16
893master=system.physmem.port 894slave=system.system_port system.cpu.l2cache.mem_side 895 896[system.physmem] 897type=DRAMCtrl 898IDD0=0.075000 899IDD02=0.000000 900IDD2N=0.050000 901IDD2N2=0.000000 902IDD2P0=0.000000 903IDD2P02=0.000000 904IDD2P1=0.000000 905IDD2P12=0.000000 906IDD3N=0.057000 907IDD3N2=0.000000 908IDD3P0=0.000000 909IDD3P02=0.000000 910IDD3P1=0.000000 911IDD3P12=0.000000 912IDD4R=0.187000 913IDD4R2=0.000000 914IDD4W=0.165000 915IDD4W2=0.000000 916IDD5=0.220000 917IDD52=0.000000 918IDD6=0.000000 919IDD62=0.000000 920VDD=1.500000 921VDD2=0.000000 922activation_limit=4	907master=system.physmem.port 908slave=system.system_port system.cpu.l2cache.mem_side 909 910[system.physmem] 911type=DRAMCtrl 912IDD0=0.075000 913IDD02=0.000000 914IDD2N=0.050000 915IDD2N2=0.000000 916IDD2P0=0.000000 917IDD2P02=0.000000 918IDD2P1=0.000000 919IDD2P12=0.000000 920IDD3N=0.057000 921IDD3N2=0.000000 922IDD3P0=0.000000 923IDD3P02=0.000000 924IDD3P1=0.000000 925IDD3P12=0.000000 926IDD4R=0.187000 927IDD4R2=0.000000 928IDD4W=0.165000 929IDD4W2=0.000000 930IDD5=0.220000 931IDD52=0.000000 932IDD6=0.000000 933IDD62=0.000000 934VDD=1.500000 935VDD2=0.000000 936activation_limit=4
923addr_mapping=RoRaBaChCo	937addr_mapping=RoRaBaCoCh
924bank_groups_per_rank=0 925banks_per_rank=8 926burst_length=8 927channels=1 928clk_domain=system.clk_domain 929conf_table_reported=true 930device_bus_width=8 931device_rowbuffer_size=1024	938bank_groups_per_rank=0 939banks_per_rank=8 940burst_length=8 941channels=1 942clk_domain=system.clk_domain 943conf_table_reported=true 944device_bus_width=8 945device_rowbuffer_size=1024
	946device_size=536870912
932devices_per_rank=8 933dll=true 934eventq_index=0 935in_addr_map=true 936max_accesses_per_row=16 937mem_sched_policy=frfcfs 938min_writes_per_switch=16 939null=false 940page_policy=open_adaptive 941range=0:134217727 942ranks_per_channel=2 943read_buffer_size=32 944static_backend_latency=10000 945static_frontend_latency=10000 946tBURST=5000 947tCCD_L=0 948tCK=1250 949tCL=13750 950tCS=2500 951tRAS=35000 952tRCD=13750 953tREFI=7800000 954tRFC=260000 955tRP=13750 956tRRD=6000 957tRRD_L=0 958tRTP=7500 959tRTW=2500 960tWR=15000 961tWTR=7500 962tXAW=30000 963tXP=0 964tXPDLL=0 965tXS=0 966tXSDLL=0 967write_buffer_size=64 968write_high_thresh_perc=85 969write_low_thresh_perc=50 970port=system.membus.master[0] 971 972[system.voltage_domain] 973type=VoltageDomain 974eventq_index=0 975voltage=1.000000 976	947devices_per_rank=8 948dll=true 949eventq_index=0 950in_addr_map=true 951max_accesses_per_row=16 952mem_sched_policy=frfcfs 953min_writes_per_switch=16 954null=false 955page_policy=open_adaptive 956range=0:134217727 957ranks_per_channel=2 958read_buffer_size=32 959static_backend_latency=10000 960static_frontend_latency=10000 961tBURST=5000 962tCCD_L=0 963tCK=1250 964tCL=13750 965tCS=2500 966tRAS=35000 967tRCD=13750 968tREFI=7800000 969tRFC=260000 970tRP=13750 971tRRD=6000 972tRRD_L=0 973tRTP=7500 974tRTW=2500 975tWR=15000 976tWTR=7500 977tXAW=30000 978tXP=0 979tXPDLL=0 980tXS=0 981tXSDLL=0 982write_buffer_size=64 983write_high_thresh_perc=85 984write_low_thresh_perc=50 985port=system.membus.master[0] 986 987[system.voltage_domain] 988type=VoltageDomain 989eventq_index=0 990voltage=1.000000 991