| stats.txt (11687:b3d5f0e9e258) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated |
| 4sim_ticks 32719500 # Number of ticks simulated 5final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 32617500 # Number of ticks simulated 5final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 128948 # Simulator instruction rate (inst/s) 8host_op_rate 150916 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 915725978 # Simulator tick rate (ticks/s) 10host_mem_usage 269308 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host | 7host_inst_rate 159604 # Simulator instruction rate (inst/s) 8host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1129633158 # Simulator tick rate (ticks/s) 10host_mem_usage 268376 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 26880 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::total 421 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 421 # Number of read requests accepted | 24system.physmem.num_reads::total 420 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 420 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 91 # Per bank write bursts 46system.physmem.perBankRdBursts::1 52 # Per bank write bursts 47system.physmem.perBankRdBursts::2 20 # Per bank write bursts 48system.physmem.perBankRdBursts::3 43 # Per bank write bursts | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 91 # Per bank write bursts 46system.physmem.perBankRdBursts::1 52 # Per bank write bursts 47system.physmem.perBankRdBursts::2 20 # Per bank write bursts 48system.physmem.perBankRdBursts::3 43 # Per bank write bursts |
| 49system.physmem.perBankRdBursts::4 22 # Per bank write bursts | 49system.physmem.perBankRdBursts::4 21 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::5 41 # Per bank write bursts 51system.physmem.perBankRdBursts::6 36 # Per bank write bursts 52system.physmem.perBankRdBursts::7 12 # Per bank write bursts 53system.physmem.perBankRdBursts::8 5 # Per bank write bursts 54system.physmem.perBankRdBursts::9 6 # Per bank write bursts 55system.physmem.perBankRdBursts::10 27 # Per bank write bursts 56system.physmem.perBankRdBursts::11 42 # Per bank write bursts 57system.physmem.perBankRdBursts::12 9 # Per bank write bursts --- 13 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 50system.physmem.perBankRdBursts::5 41 # Per bank write bursts 51system.physmem.perBankRdBursts::6 36 # Per bank write bursts 52system.physmem.perBankRdBursts::7 12 # Per bank write bursts 53system.physmem.perBankRdBursts::8 5 # Per bank write bursts 54system.physmem.perBankRdBursts::9 6 # Per bank write bursts 55system.physmem.perBankRdBursts::10 27 # Per bank write bursts 56system.physmem.perBankRdBursts::11 42 # Per bank write bursts 57system.physmem.perBankRdBursts::12 9 # Per bank write bursts --- 13 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 32621500 # Total gap between requests | 79system.physmem.totGap 32519500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 421 # Read request sizes (log2) | 86system.physmem.readPktSize::6 420 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see --- 80 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation | 95system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see --- 80 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation |
| 191system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation | 191system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation |
| 196system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation | 196system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation |
| 197system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation | 197system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation |
| 201system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation | 201system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation |
| 204system.physmem.totQLat 5175000 # Total ticks spent queuing 205system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst | 204system.physmem.totQLat 5148000 # Total ticks spent queuing 205system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 6.43 # Data bus utilization in percentage 216system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 6.44 # Data bus utilization in percentage 216system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 347 # Number of row buffer hits during reads | 220system.physmem.readRowHits 346 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 77485.75 # Average gap between requests 225system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined | 224system.physmem.avgGap 77427.38 # Average gap between requests 225system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) | 226system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ) | 228system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ) | 231system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) | 232system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ) | 233system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) |
| 234system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 234system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ) 237system.physmem_0.averagePower 615.992054 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank | 236system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) 237system.physmem_0.averagePower 616.275926 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states |
| 243system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states | 243system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states |
| 245system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) | 245system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ) | 250system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ) 256system.physmem_1.averagePower 556.500000 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank | 255system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) 256system.physmem_1.averagePower 557.213152 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states | 258system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states |
| 261system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states | 261system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states |
| 262system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states | 262system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states |
| 263system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 1968 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 322 # Number of BTB hits | 263system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 1965 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 324 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. | 271system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. |
| 273system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. | 273system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. | 274system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. |
| 275system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. | 275system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. |
| 276system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. | 276system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. |
| 278system.cpu_clk_domain.clock 500 # Clock period in ticks | 278system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 279system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 279system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 280system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 280system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 309system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 309system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 310system.cpu.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dtb.read_accesses 0 # DTB read accesses 334system.cpu.dtb.write_accesses 0 # DTB write accesses 335system.cpu.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.dtb.hits 0 # DTB hits 337system.cpu.dtb.misses 0 # DTB misses 338system.cpu.dtb.accesses 0 # DTB accesses | 310system.cpu.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 331system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dtb.read_accesses 0 # DTB read accesses 334system.cpu.dtb.write_accesses 0 # DTB write accesses 335system.cpu.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.dtb.hits 0 # DTB hits 337system.cpu.dtb.misses 0 # DTB misses 338system.cpu.dtb.accesses 0 # DTB accesses |
| 339system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 339system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 340system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 340system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 361system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 369system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 369system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 370system.cpu.itb.walker.walks 0 # Table walker walks requested 371system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.itb.read_accesses 0 # DTB read accesses 394system.cpu.itb.write_accesses 0 # DTB write accesses 395system.cpu.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.itb.hits 0 # DTB hits 397system.cpu.itb.misses 0 # DTB misses 398system.cpu.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 13 # Number of system calls | 370system.cpu.itb.walker.walks 0 # Table walker walks requested 371system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 392system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.itb.read_accesses 0 # DTB read accesses 394system.cpu.itb.write_accesses 0 # DTB write accesses 395system.cpu.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.itb.hits 0 # DTB hits 397system.cpu.itb.misses 0 # DTB misses 398system.cpu.itb.accesses 0 # DTB accesses 399system.cpu.workload.num_syscalls 13 # Number of system calls |
| 400system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states 401system.cpu.numCycles 65439 # number of cpu cycles simulated | 400system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states 401system.cpu.numCycles 65235 # number of cpu cycles simulated |
| 402system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 404system.cpu.committedInsts 4605 # Number of instructions committed 405system.cpu.committedOps 5391 # Number of ops (including micro ops) committed | 402system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 404system.cpu.committedInsts 4605 # Number of instructions committed 405system.cpu.committedOps 5391 # Number of ops (including micro ops) committed |
| 406system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit | 406system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit |
| 407system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 407system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 408system.cpu.cpi 14.210423 # CPI: cycles per instruction 409system.cpu.ipc 0.070371 # IPC: instructions per cycle | 408system.cpu.cpi 14.166124 # CPI: cycles per instruction 409system.cpu.ipc 0.070591 # IPC: instructions per cycle |
| 410system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 411system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction 412system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction 413system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction 414system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction 415system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction 416system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction 417system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 441system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction 442system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction 443system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction 444system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 445system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 446system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 447system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::total 5391 # Class of committed instruction | 410system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 411system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction 412system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction 413system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction 414system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction 415system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction 416system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction 417system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 441system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction 442system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction 443system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction 444system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 445system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 446system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 447system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::total 5391 # Class of committed instruction |
| 449system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped 451system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 449system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped 451system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 452system.cpu.dcache.tags.replacements 0 # number of replacements | 452system.cpu.dcache.tags.replacements 0 # number of replacements |
| 453system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use | 453system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use |
| 454system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 454system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 458system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy | 458system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy |
| 461system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 464system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 465system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses 466system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses | 461system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 464system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 465system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses 466system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses |
| 467system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 467system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 468system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits 469system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits 470system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 471system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 472system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 473system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 474system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 475system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 86 unchanged lines hidden (view full) --- 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058 # average ReadReq mshr miss latency 563system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058 # average ReadReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070 # average WriteReq mshr miss latency 565system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070 # average WriteReq mshr miss latency 566system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency 568system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency | 468system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits 469system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits 470system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 471system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 472system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 473system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 474system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 475system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 86 unchanged lines hidden (view full) --- 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058 # average ReadReq mshr miss latency 563system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058 # average ReadReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070 # average WriteReq mshr miss latency 565system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070 # average WriteReq mshr miss latency 566system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency 568system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency |
| 570system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 570system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 571system.cpu.icache.tags.replacements 4 # number of replacements | 571system.cpu.icache.tags.replacements 4 # number of replacements |
| 572system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use 573system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks. 574system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 575system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks. | 572system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use 573system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. 574system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. 575system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. |
| 576system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 576system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 577system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor 578system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy 579system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy 580system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id | 577system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor 578system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy 579system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy 580system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id |
| 581system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id | 581system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id |
| 582system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id 583system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id 584system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses 585system.cpu.icache.tags.data_accesses 4896 # Number of data accesses 586system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states 587system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits 588system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits 589system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits 590system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits 591system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits 592system.cpu.icache.overall_hits::total 1965 # number of overall hits 593system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 594system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 595system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 596system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 597system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 598system.cpu.icache.overall_misses::total 322 # number of overall misses 599system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles 600system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles 601system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles 602system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles 603system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles 604system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles | 582system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id 583system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id 584system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses 585system.cpu.icache.tags.data_accesses 4895 # Number of data accesses 586system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states 587system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits 588system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits 589system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits 590system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits 591system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits 592system.cpu.icache.overall_hits::total 1966 # number of overall hits 593system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses 594system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses 595system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses 596system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses 597system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses 598system.cpu.icache.overall_misses::total 321 # number of overall misses 599system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles 600system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles 601system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles 602system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles 603system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles 604system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles |
| 605system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) 606system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) 607system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses 608system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses 609system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses 610system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses | 605system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) 606system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) 607system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses 608system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses 609system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses 610system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses |
| 611system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses 612system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses 613system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses 614system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses 615system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses 616system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses 617system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency 618system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency 619system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency 620system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency 621system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency 622system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency | 611system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses 612system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses 613system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses 614system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses 615system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses 616system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses 617system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency 618system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency 619system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency 620system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency 621system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency 622system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency |
| 623system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 624system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 625system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 626system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 627system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 628system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 629system.cpu.icache.writebacks::writebacks 4 # number of writebacks 630system.cpu.icache.writebacks::total 4 # number of writebacks | 623system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 624system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 625system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 626system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 627system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 628system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 629system.cpu.icache.writebacks::writebacks 4 # number of writebacks 630system.cpu.icache.writebacks::total 4 # number of writebacks |
| 631system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 632system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 633system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 634system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 635system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 636system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses 637system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles 639system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles 640system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles 641system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles 642system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles 643system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses 644system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses 645system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses 646system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses 647system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses 648system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses 649system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency 650system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency 651system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency 652system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency 653system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency 654system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency 655system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 631system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses 632system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses 633system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses 634system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses 635system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses 636system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses 637system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles 638system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles 639system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles 640system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles 641system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles 642system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles 643system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses 644system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses 645system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses 646system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses 647system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses 648system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses 649system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency 650system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency 651system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency 652system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency 653system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency 654system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency 655system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 656system.cpu.l2cache.tags.replacements 0 # number of replacements | 656system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 657system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use | 657system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use |
| 658system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. | 658system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. |
| 659system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. 660system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. | 659system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. 660system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. |
| 661system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 661system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 662system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor 663system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor 664system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy 665system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy 666system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id | 662system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor 663system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor 664system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy 665system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy 666system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy 667system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id |
| 668system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id | 668system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id |
| 669system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id 670system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id 671system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses 672system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses 673system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states | 669system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id 670system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id 671system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses 672system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses 673system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states |
| 674system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits 675system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits 676system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits 677system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits 678system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits 679system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits 680system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 682system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 683system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 684system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 685system.cpu.l2cache.overall_hits::total 39 # number of overall hits 686system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 687system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses | 674system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits 675system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits 676system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits 677system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits 678system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits 679system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits 680system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 681system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits 682system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 683system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits 684system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits 685system.cpu.l2cache.overall_hits::total 39 # number of overall hits 686system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 687system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses |
| 688system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses 689system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses | 688system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses 689system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses |
| 690system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses 691system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses | 690system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses 691system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses |
| 692system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses | 692system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses |
| 693system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses | 693system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses |
| 694system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 695system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses | 694system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses 695system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses |
| 696system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses | 696system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses |
| 697system.cpu.l2cache.overall_misses::total 429 # number of overall misses | 697system.cpu.l2cache.overall_misses::total 428 # number of overall misses |
| 698system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles | 698system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles 699system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles |
| 700system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles 701system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles | 700system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles 701system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles |
| 702system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles 703system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles | 702system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles 703system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles |
| 704system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles | 704system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles |
| 705system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles | 705system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles |
| 706system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles 707system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles | 706system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles 707system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles |
| 708system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles | 708system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles |
| 709system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles | 709system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles |
| 710system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) 711system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) | 710system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) 711system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) 712system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) |
| 714system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) 715system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) | 714system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) 715system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) |
| 716system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 717system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) | 716system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 717system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) |
| 718system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses | 718system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses |
| 719system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses | 719system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses |
| 720system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses 721system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses | 720system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses 721system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses |
| 722system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses | 722system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses |
| 723system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses | 723system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses |
| 724system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 725system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 724system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 725system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 726system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses 727system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses | 726system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses 727system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses |
| 728system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses 729system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses | 728system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses 729system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses |
| 730system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses | 730system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses |
| 731system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses | 731system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses |
| 732system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 733system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses | 732system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses 733system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses |
| 734system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses | 734system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses |
| 735system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses | 735system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses |
| 736system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency 737system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency | 736system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency 737system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency |
| 738system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency 739system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency | 738system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency 739system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency |
| 740system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency 741system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency | 740system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency 741system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency |
| 742system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency | 742system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency |
| 743system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency | 743system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency |
| 744system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency 745system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency | 744system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency 745system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency |
| 746system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency | 746system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency |
| 747system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency | 747system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency |
| 748system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 749system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 753system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 755system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits 756system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 757system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 758system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 759system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 760system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 761system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses | 748system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 749system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 752system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 753system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 754system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 755system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits 756system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 757system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 758system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 759system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 760system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 761system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses |
| 762system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses 763system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses | 762system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses 763system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses |
| 764system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses 765system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses | 764system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses 765system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses |
| 766system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses | 766system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses |
| 767system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses | 767system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses |
| 768system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses | 768system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses |
| 770system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses | 770system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses |
| 771system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses | 771system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses |
| 772system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles | 772system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles 773system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles |
| 774system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles 775system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles | 774system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles 775system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles |
| 776system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles 777system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles | 776system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles 777system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles |
| 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles | 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles |
| 779system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles | 779system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles |
| 780system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles | 780system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles |
| 782system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles | 782system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles |
| 783system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles | 783system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles |
| 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 784system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 786system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses 787system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses | 786system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses 787system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses |
| 788system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses 789system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses | 788system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses 789system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses |
| 790system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses | 790system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses |
| 791system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses | 791system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses |
| 792system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 793system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses | 792system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses 793system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses |
| 794system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses | 794system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses |
| 795system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses | 795system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses |
| 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency | 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency |
| 798system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency 799system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency | 798system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency 799system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency |
| 800system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency 801system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency | 800system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency 801system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency |
| 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency | 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency |
| 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency | 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency |
| 804system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency | 804system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency |
| 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency | 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency |
| 807system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency 808system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. | 807system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency 808system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. |
| 809system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. 810system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 811system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 812system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 813system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 809system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. 810system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 811system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 812system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 813system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 814system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states 815system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution | 814system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states 815system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution |
| 816system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 817system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 818system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution | 816system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 817system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 818system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution |
| 819system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution | 819system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution |
| 820system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution | 820system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution |
| 821system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) | 821system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) |
| 822system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) | 822system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) |
| 823system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes) 824system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes) | 823system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 824system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) |
| 825system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) | 825system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) |
| 826system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) | 826system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) |
| 827system.cpu.toL2Bus.snoops 0 # Total snoops (count) 828system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 827system.cpu.toL2Bus.snoops 0 # Total snoops (count) 828system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 829system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram 831system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram | 829system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram 830system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram 831system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram |
| 832system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 832system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 833system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram 834system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram | 833system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram 834system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram |
| 835system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 836system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 837system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 838system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 835system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 836system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 837system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 838system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 839system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 840system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) | 839system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram 840system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) |
| 841system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) | 841system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 842system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) | 842system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) |
| 843system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 844system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 845system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 843system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 844system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 845system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 846system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. | 846system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. |
| 847system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 848system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 849system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 850system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 851system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 847system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 848system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 849system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 850system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 851system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 852system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states 853system.membus.trans_dist::ReadResp 378 # Transaction distribution | 852system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states 853system.membus.trans_dist::ReadResp 377 # Transaction distribution |
| 854system.membus.trans_dist::ReadExReq 43 # Transaction distribution 855system.membus.trans_dist::ReadExResp 43 # Transaction distribution | 854system.membus.trans_dist::ReadExReq 43 # Transaction distribution 855system.membus.trans_dist::ReadExResp 43 # Transaction distribution |
| 856system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution 857system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 858system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 859system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) 860system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) | 856system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution 857system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) 858system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) 859system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) 860system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) |
| 861system.membus.snoops 0 # Total snoops (count) 862system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 861system.membus.snoops 0 # Total snoops (count) 862system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 863system.membus.snoop_fanout::samples 421 # Request fanout histogram | 863system.membus.snoop_fanout::samples 420 # Request fanout histogram |
| 864system.membus.snoop_fanout::mean 0 # Request fanout histogram 865system.membus.snoop_fanout::stdev 0 # Request fanout histogram 866system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 864system.membus.snoop_fanout::mean 0 # Request fanout histogram 865system.membus.snoop_fanout::stdev 0 # Request fanout histogram 866system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 867system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram | 867system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram |
| 868system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 869system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 870system.membus.snoop_fanout::min_value 0 # Request fanout histogram 871system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 868system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 869system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 870system.membus.snoop_fanout::min_value 0 # Request fanout histogram 871system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 872system.membus.snoop_fanout::total 421 # Request fanout histogram 873system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks) | 872system.membus.snoop_fanout::total 420 # Request fanout histogram 873system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) |
| 874system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) | 874system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) |
| 875system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks) | 875system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks) |
| 876system.membus.respLayer1.utilization 6.8 # Layer utilization (%) 877 878---------- End Simulation Statistics ---------- | 876system.membus.respLayer1.utilization 6.8 # Layer utilization (%) 877 878---------- End Simulation Statistics ---------- |