| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated |
| 4sim_ticks 30083500 # Number of ticks simulated 5final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 30404500 # Number of ticks simulated 5final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 80042 # Simulator instruction rate (inst/s) 8host_op_rate 93682 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 522670316 # Simulator tick rate (ticks/s) 10host_mem_usage 264608 # Number of bytes of host memory used | 7host_inst_rate 82707 # Simulator instruction rate (inst/s) 8host_op_rate 96800 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 545818868 # Simulator tick rate (ticks/s) 10host_mem_usage 269760 # Number of bytes of host memory used |
| 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 421 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 421 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 421 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 421 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 29992500 # Total gap between requests | 79system.physmem.totGap 30312500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 421 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 421 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation 204system.physmem.totQLat 2221000 # Total ticks spent queuing 205system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 204system.physmem.totQLat 2201250 # Total ticks spent queuing 205system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 7.00 # Data bus utilization in percentage 216system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 6.92 # Data bus utilization in percentage 216system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 350 # Number of row buffer hits during reads | 220system.physmem.readRowHits 349 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 71241.09 # Average gap between requests 225system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined | 224system.physmem.avgGap 72001.19 # Average gap between requests 225system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) | 226system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ) | 228system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ) | 231system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) | 232system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ) 234system.physmem_0.averagePower 849.295873 # Core power per rank (mW) | 233system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) 234system.physmem_0.averagePower 848.348875 # Core power per rank (mW) |
| 235system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states 236system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states 236system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states |
| 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) | 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) |
| 245system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ) 248system.physmem_1.averagePower 783.273247 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states | 245system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ) 248system.physmem_1.averagePower 782.690871 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states |
| 250system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 250system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states |
| 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 254system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 255system.cpu.branchPred.lookups 1968 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 1660 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 322 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 19.397590 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks | 255system.cpu.branchPred.lookups 1968 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 1660 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 322 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 19.397590 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses | 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses |
| 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 13 # Number of system calls | 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 13 # Number of system calls |
| 390system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 60167 # number of cpu cycles simulated | 390system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 60809 # number of cpu cycles simulated |
| 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 4605 # Number of instructions committed 395system.cpu.committedOps 5391 # Number of ops (including micro ops) committed 396system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 4605 # Number of instructions committed 395system.cpu.committedOps 5391 # Number of ops (including micro ops) committed 396system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 398system.cpu.cpi 13.065581 # CPI: cycles per instruction 399system.cpu.ipc 0.076537 # IPC: instructions per cycle | 398system.cpu.cpi 13.204995 # CPI: cycles per instruction 399system.cpu.ipc 0.075729 # IPC: instructions per cycle |
| 400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction 402system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 427system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction 430system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 5391 # Class of committed instruction | 400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction 402system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 427system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction 430system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 5391 # Class of committed instruction |
| 435system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 435system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 438system.cpu.dcache.tags.replacements 0 # number of replacements | 438system.cpu.dcache.tags.replacements 0 # number of replacements |
| 439system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use | 439system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use |
| 440system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 440system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 444system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy | 444system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy |
| 447system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id | 447system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id |
| 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id | 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id |
| 450system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 451system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses 452system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses | 450system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 451system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses 452system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses |
| 453system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 453system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 454system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits 455system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits 456system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 457system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 458system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 459system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 460system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 461system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 466system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses 467system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses 468system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 469system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 470system.cpu.dcache.demand_misses::cpu.data 176 # number of demand (read+write) misses 471system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses 472system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses 473system.cpu.dcache.overall_misses::total 176 # number of overall misses | 454system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits 455system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits 456system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 457system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 458system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 459system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 460system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 461system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 4 unchanged lines hidden (view full) --- 466system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses 467system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses 468system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 469system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 470system.cpu.dcache.demand_misses::cpu.data 176 # number of demand (read+write) misses 471system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses 472system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses 473system.cpu.dcache.overall_misses::total 176 # number of overall misses |
| 474system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles 475system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles 478system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles 479system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles 480system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles 481system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles | 474system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles 475system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles 477system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles 478system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles 479system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles 480system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles 481system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles |
| 482system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 486system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 494system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094047 # miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_miss_rate::total 0.094047 # miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 498system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 # miss rate for demand accesses 499system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses 500system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses 501system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses | 482system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 486system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 494system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094047 # miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_miss_rate::total 0.094047 # miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 498system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 # miss rate for demand accesses 499system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses 500system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses 501system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses |
| 502system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency 503system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency 504system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency 505system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency 506system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency 507system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency 509system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency | 502system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency 503system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency 504system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency 505system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency 506system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency 507system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency 508system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency 509system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency |
| 510system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 511system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 515system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 524system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 525system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 526system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 528system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 529system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 530system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 531system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses | 510system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 511system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 512system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 515system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 517system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 524system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 525system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 526system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 528system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 529system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 530system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 531system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses |
| 532system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles 533system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles 537system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles 539system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles | 532system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles 533system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles 537system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles 539system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles |
| 540system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses 541system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses 542system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 543system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 544system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for demand accesses 545system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses 546system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses 547system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses | 540system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses 541system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses 542system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 543system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 544system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for demand accesses 545system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses 546system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses 547system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses |
| 548system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency 550system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency 556system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 548system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency 550system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency 556system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 557system.cpu.icache.tags.replacements 4 # number of replacements | 557system.cpu.icache.tags.replacements 4 # number of replacements |
| 558system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use | 558system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use |
| 559system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 559system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 563system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy | 563system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy |
| 566system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id | 566system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id |
| 567system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id | 567system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id |
| 569system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id 570system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses 571system.cpu.icache.tags.data_accesses 4892 # Number of data accesses | 569system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id 570system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses 571system.cpu.icache.tags.data_accesses 4892 # Number of data accesses |
| 572system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 572system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 573system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits 574system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits 575system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits 576system.cpu.icache.demand_hits::total 1963 # number of demand (read+write) hits 577system.cpu.icache.overall_hits::cpu.inst 1963 # number of overall hits 578system.cpu.icache.overall_hits::total 1963 # number of overall hits 579system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 580system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 581system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 582system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 583system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 584system.cpu.icache.overall_misses::total 322 # number of overall misses | 573system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits 574system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits 575system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits 576system.cpu.icache.demand_hits::total 1963 # number of demand (read+write) hits 577system.cpu.icache.overall_hits::cpu.inst 1963 # number of overall hits 578system.cpu.icache.overall_hits::total 1963 # number of overall hits 579system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 580system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 581system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 582system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 583system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 584system.cpu.icache.overall_misses::total 322 # number of overall misses |
| 585system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles 586system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles 587system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles 588system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles 589system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles 590system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles | 585system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles 586system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles 587system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles 588system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles 589system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles 590system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles |
| 591system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) 592system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses 594system.cpu.icache.demand_accesses::total 2285 # number of demand (read+write) accesses 595system.cpu.icache.overall_accesses::cpu.inst 2285 # number of overall (read+write) accesses 596system.cpu.icache.overall_accesses::total 2285 # number of overall (read+write) accesses 597system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140919 # miss rate for ReadReq accesses 598system.cpu.icache.ReadReq_miss_rate::total 0.140919 # miss rate for ReadReq accesses 599system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 # miss rate for demand accesses 600system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses 601system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses 602system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses | 591system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) 592system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) 593system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses 594system.cpu.icache.demand_accesses::total 2285 # number of demand (read+write) accesses 595system.cpu.icache.overall_accesses::cpu.inst 2285 # number of overall (read+write) accesses 596system.cpu.icache.overall_accesses::total 2285 # number of overall (read+write) accesses 597system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140919 # miss rate for ReadReq accesses 598system.cpu.icache.ReadReq_miss_rate::total 0.140919 # miss rate for ReadReq accesses 599system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 # miss rate for demand accesses 600system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses 601system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses 602system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses |
| 603system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency 604system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency 605system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency 606system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency 607system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency | 603system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency 604system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency 605system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency 606system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency 607system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency 608system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency |
| 609system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 610system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 611system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 613system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 614system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 615system.cpu.icache.writebacks::writebacks 4 # number of writebacks 616system.cpu.icache.writebacks::total 4 # number of writebacks 617system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 618system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 619system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 620system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 621system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 622system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses | 609system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 610system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 611system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 612system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 613system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 614system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 615system.cpu.icache.writebacks::writebacks 4 # number of writebacks 616system.cpu.icache.writebacks::total 4 # number of writebacks 617system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 618system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 619system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 620system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 621system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 622system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses |
| 623system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles 624system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles 625system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles 626system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles 627system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles 628system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles | 623system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles 624system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles 625system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles 626system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles 627system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles 628system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles |
| 629system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses 630system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses 631system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses 632system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses 633system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses 634system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses | 629system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses 630system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses 631system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses 632system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses 633system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses 634system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses |
| 635system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency 637system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency 639system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency 641system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 635system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency 637system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency 639system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency 641system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 642system.cpu.l2cache.tags.replacements 0 # number of replacements | 642system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 643system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use | 643system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use |
| 644system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. | 644system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. |
| 645system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 646system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks. | 645system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. 646system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. |
| 647system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 647system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 648system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor 649system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy 651system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy 652system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id 654system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 655system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 656system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id | 648system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor 649system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy 651system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy 652system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id 654system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 655system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 656system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id |
| 657system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses 658system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses | 657system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses 658system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses |
| 659system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 659system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 660system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits 661system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits 662system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits 663system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits 664system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits 665system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits 666system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 667system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits --- 8 unchanged lines hidden (view full) --- 676system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses 677system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses 678system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 679system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses 680system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 681system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 682system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses 683system.cpu.l2cache.overall_misses::total 429 # number of overall misses | 660system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits 661system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits 662system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits 663system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits 664system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits 665system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits 666system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 667system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits --- 8 unchanged lines hidden (view full) --- 676system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses 677system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses 678system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 679system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses 680system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 681system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 682system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses 683system.cpu.l2cache.overall_misses::total 429 # number of overall misses |
| 684system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles 685system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles 686system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles 687system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles 688system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles 689system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles 690system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles 691system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles 692system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles 693system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles 694system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles 695system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles | 684system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles 685system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles 686system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles 687system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles 688system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles 689system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles 690system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles 691system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles 692system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles 693system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles 694system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles 695system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles |
| 696system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) 697system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) 698system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 699system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 700system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) 701system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) 702system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 703system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 714system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses 715system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses 716system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses 717system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses 718system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 719system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses 720system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses 721system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses | 696system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) 697system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) 698system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 699system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 700system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) 701system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) 702system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 703system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 714system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses 715system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses 716system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses 717system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses 718system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 719system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses 720system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses 721system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses |
| 722system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency 723system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency 724system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency 725system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency 726system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency 727system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency 728system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency 729system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency 730system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency 731system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency 732system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency | 722system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency 723system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency 724system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency 725system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency 726system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency 727system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency 728system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency 729system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency 730system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency 731system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency 732system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency 733system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency |
| 734system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 741system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 750system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses 751system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses 752system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 753system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 754system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 755system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 756system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 757system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses | 734system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 741system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits --- 8 unchanged lines hidden (view full) --- 750system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses 751system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses 752system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 753system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 754system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 755system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 756system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 757system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses |
| 758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles 759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles 760system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles 761system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles 762system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles 763system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles 764system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles 767system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles | 758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles 759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles 760system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles 761system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles 762system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles 763system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles 764system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles 767system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles |
| 770system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 772system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses 774system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses 775system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses 776system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 777system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 778system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 779system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 780system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 781system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses | 770system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 772system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses 774system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses 775system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses 776system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 777system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 778system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 779system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 780system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 781system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses |
| 782system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency 783system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency 784system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency 785system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency 786system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency 787system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency 788system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency 789system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency 790system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency 791system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency 792system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency 793system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency | 782system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency 783system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency 784system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency 785system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency 786system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency 787system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency 788system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency 789system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency 790system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency 791system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency 792system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency 793system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency |
| 794system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. 795system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. 796system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 797system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 798system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 799system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 794system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. 795system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. 796system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 797system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 798system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 799system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 800system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 800system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 801system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 802system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 803system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 804system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 805system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution 806system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 807system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) 808system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 824system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 825system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 826system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 827system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 828system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) 829system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 830system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 831system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 801system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 802system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 803system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 804system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 805system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution 806system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 807system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes) 808system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 824system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 825system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 826system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 827system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 828system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) 829system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 830system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 831system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 832system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states | 832system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. 833system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 834system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 835system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 836system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 837system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 838system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states |
| 833system.membus.trans_dist::ReadResp 378 # Transaction distribution 834system.membus.trans_dist::ReadExReq 43 # Transaction distribution 835system.membus.trans_dist::ReadExResp 43 # Transaction distribution 836system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution 837system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 838system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 839system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) 840system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 847system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 848system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 849system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 850system.membus.snoop_fanout::min_value 0 # Request fanout histogram 851system.membus.snoop_fanout::max_value 0 # Request fanout histogram 852system.membus.snoop_fanout::total 421 # Request fanout histogram 853system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) 854system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) | 839system.membus.trans_dist::ReadResp 378 # Transaction distribution 840system.membus.trans_dist::ReadExReq 43 # Transaction distribution 841system.membus.trans_dist::ReadExResp 43 # Transaction distribution 842system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution 843system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 844system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 845system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) 846system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 853system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 854system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 855system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 856system.membus.snoop_fanout::min_value 0 # Request fanout histogram 857system.membus.snoop_fanout::max_value 0 # Request fanout histogram 858system.membus.snoop_fanout::total 421 # Request fanout histogram 859system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) 860system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) |
| 855system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks) | 861system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) |
| 856system.membus.respLayer1.utilization 7.4 # Layer utilization (%) 857 858---------- End Simulation Statistics ---------- | 862system.membus.respLayer1.utilization 7.4 # Layer utilization (%) 863 864---------- End Simulation Statistics ---------- |