| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29977500 # Number of ticks simulated 5final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29977500 # Number of ticks simulated 5final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 146522 # Simulator instruction rate (inst/s) 8host_op_rate 171470 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 953185288 # Simulator tick rate (ticks/s) 10host_mem_usage 264656 # Number of bytes of host memory used | 7host_inst_rate 147440 # Simulator instruction rate (inst/s) 8host_op_rate 172555 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 959274014 # Simulator tick rate (ticks/s) 10host_mem_usage 309288 # Number of bytes of host memory used |
| 11host_seconds 0.03 # Real time elapsed on the host 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.03 # Real time elapsed on the host 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ) 247system.physmem_1.averagePower 784.269066 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 421 # Number of read requests responded to by this memory --- 221 unchanged lines hidden (view full) --- 246system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ) 248system.physmem_1.averagePower 784.269066 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states 250system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 254system.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 253system.cpu.branchPred.lookups 1949 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 316 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 125 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks | 255system.cpu.branchPred.lookups 1949 # Number of BP lookups 256system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 316 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 125 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses | 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses |
| 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls | 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 13 # Number of system calls |
| 390system.cpu.pwrStateResidencyTicks::ON 29977500 # Cumulative time (in ticks) in various power states |
|
| 384system.cpu.numCycles 59955 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 387system.cpu.committedInsts 4605 # Number of instructions committed 388system.cpu.committedOps 5391 # Number of ops (including micro ops) committed 389system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit 390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 391system.cpu.cpi 13.019544 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 422system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction 423system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction 424system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction 425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 427system.cpu.op_class_0::total 5391 # Class of committed instruction 428system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked 429system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped | 391system.cpu.numCycles 59955 # number of cpu cycles simulated 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 4605 # Number of instructions committed 395system.cpu.committedOps 5391 # Number of ops (including micro ops) committed 396system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 398system.cpu.cpi 13.019544 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction 430system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 5391 # Class of committed instruction 435system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped |
| 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 430system.cpu.dcache.tags.replacements 0 # number of replacements 431system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use 432system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks. 433system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 434system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks. 435system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor 437system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 440system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 442system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 443system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses 444system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses | 438system.cpu.dcache.tags.replacements 0 # number of replacements 439system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy 447system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 450system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 451system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses 452system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses |
| 453system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 445system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 446system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 447system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 448system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 449system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 450system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 451system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 452system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 86 unchanged lines hidden (view full) --- 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency | 454system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 455system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 456system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 457system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 458system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 459system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 460system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 461system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 86 unchanged lines hidden (view full) --- 548system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency 550system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency 552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency 554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency |
| 556system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 547system.cpu.icache.tags.replacements 4 # number of replacements 548system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use 549system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. 550system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks. 551system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks. 552system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 553system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor 554system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy 555system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id 557system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 558system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 559system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id 560system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses 561system.cpu.icache.tags.data_accesses 4821 # Number of data accesses | 557system.cpu.icache.tags.replacements 4 # number of replacements 558system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use 559system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. 560system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks. 561system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks. 562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 563system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor 564system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy 565system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy 566system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id 567system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 568system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 569system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id 570system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses 571system.cpu.icache.tags.data_accesses 4821 # Number of data accesses |
| 572system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 562system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits 563system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits 564system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits 565system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits 566system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits 567system.cpu.icache.overall_hits::total 1926 # number of overall hits 568system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses 569system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 622system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses 623system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses 624system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency 625system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency 626system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 627system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency 628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 629system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency | 573system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits 574system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits 575system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits 576system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits 577system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits 578system.cpu.icache.overall_hits::total 1926 # number of overall hits 579system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses 580system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 633system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses 634system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses 635system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency 636system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency 637system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 638system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency 639system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 640system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency |
| 641system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 630system.cpu.l2cache.tags.replacements 0 # number of replacements 631system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use 632system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. 633system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 634system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks. 635system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 636system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor 637system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor 638system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy 639system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy 640system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy 641system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id 642system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 643system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 644system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id 645system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses 646system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses | 642system.cpu.l2cache.tags.replacements 0 # number of replacements 643system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use 644system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. 645system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 646system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks. 647system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 648system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor 649system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor 650system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy 651system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy 652system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy 653system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id 654system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 655system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 656system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id 657system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses 658system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses |
| 659system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 647system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits 648system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits 649system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 650system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 651system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits 652system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits 653system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 654system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits --- 124 unchanged lines hidden (view full) --- 779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency 781system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. 782system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. 783system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 784system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 785system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 786system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 660system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits 661system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits 662system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits 663system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 664system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits 665system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits 666system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 667system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits --- 124 unchanged lines hidden (view full) --- 792system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency 793system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency 794system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. 795system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. 796system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 797system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 798system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 799system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 800system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 787system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution 788system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 789system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 790system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 791system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution 792system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 793system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes) 794system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 809system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 810system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram 811system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) 812system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 813system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks) 814system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 815system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 816system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 801system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution 802system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 803system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 804system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 805system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution 806system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 807system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes) 808system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 823system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 824system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram 825system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) 826system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 827system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks) 828system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 829system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 830system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 831system.membus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states |
|
| 817system.membus.trans_dist::ReadResp 378 # Transaction distribution 818system.membus.trans_dist::ReadExReq 43 # Transaction distribution 819system.membus.trans_dist::ReadExResp 43 # Transaction distribution 820system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution 821system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 822system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 823system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) 824system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 832system.membus.trans_dist::ReadResp 378 # Transaction distribution 833system.membus.trans_dist::ReadExReq 43 # Transaction distribution 834system.membus.trans_dist::ReadExResp 43 # Transaction distribution 835system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution 836system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 837system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 838system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) 839system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |