| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29977500 # Number of ticks simulated 5final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29977500 # Number of ticks simulated 5final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 167534 # Simulator instruction rate (inst/s) 8host_op_rate 196036 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1088591965 # Simulator tick rate (ticks/s) 10host_mem_usage 269228 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host | 7host_inst_rate 89930 # Simulator instruction rate (inst/s) 8host_op_rate 105235 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 584953104 # Simulator tick rate (ticks/s) 10host_mem_usage 268772 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory --- 479 unchanged lines hidden (view full) --- 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency 501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory --- 479 unchanged lines hidden (view full) --- 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency 501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 509system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 510system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 511system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits 512system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits 513system.cpu.dcache.demand_mshr_hits::cpu.data 36 # number of demand (read+write) MSHR hits 514system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits 515system.cpu.dcache.overall_mshr_hits::cpu.data 36 # number of overall MSHR hits 516system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 541system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency 542system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency 543system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency 544system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency 545system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 546system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency 547system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 548system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency | 507system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits 508system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 509system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits 510system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits 511system.cpu.dcache.demand_mshr_hits::cpu.data 36 # number of demand (read+write) MSHR hits 512system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits 513system.cpu.dcache.overall_mshr_hits::cpu.data 36 # number of overall MSHR hits 514system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency |
| 549system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 550system.cpu.icache.tags.replacements 4 # number of replacements 551system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use 552system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. 553system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks. 554system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks. 555system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 556system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor 557system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 599system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency 600system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency 601system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 602system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 603system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 604system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 605system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 606system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 547system.cpu.icache.tags.replacements 4 # number of replacements 548system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use 549system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks. 550system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks. 551system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks. 552system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 553system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor 554system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 596system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency 597system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency 598system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 599system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 600system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 601system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 602system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 603system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 607system.cpu.icache.fast_writes 0 # number of fast writes performed 608system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 609system.cpu.icache.writebacks::writebacks 4 # number of writebacks 610system.cpu.icache.writebacks::total 4 # number of writebacks 611system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses 612system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses 613system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses 614system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses 615system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses 616system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 627system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses 628system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses 629system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency 630system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency 631system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 632system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency 633system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 634system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency | 604system.cpu.icache.writebacks::writebacks 4 # number of writebacks 605system.cpu.icache.writebacks::total 4 # number of writebacks 606system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses 607system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses 608system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses 609system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses 610system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses 611system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 622system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses 623system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses 624system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency 625system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency 626system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 627system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency 628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency 629system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency |
| 635system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 636system.cpu.l2cache.tags.replacements 0 # number of replacements 637system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use 638system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. 639system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 640system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks. 641system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 642system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor 643system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor --- 81 unchanged lines hidden (view full) --- 725system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency 726system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency 727system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 728system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 729system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 730system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 731system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 732system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 630system.cpu.l2cache.tags.replacements 0 # number of replacements 631system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use 632system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. 633system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 634system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks. 635system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 636system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor 637system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor --- 81 unchanged lines hidden (view full) --- 719system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency 720system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency 721system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 725system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 733system.cpu.l2cache.fast_writes 0 # number of fast writes performed 734system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 735system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 736system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits 737system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 738system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 739system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 740system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 741system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 742system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses --- 38 unchanged lines hidden (view full) --- 781system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency 782system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency 783system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency 784system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency 785system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency 786system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency 787system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency 788system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency | 727system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits 728system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits 729system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 730system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 731system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 732system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 733system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 734system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses --- 38 unchanged lines hidden (view full) --- 773system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency 774system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency 775system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency 776system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency 778system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency 779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency |
| 789system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 790system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. 791system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. 792system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 793system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 794system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 795system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 796system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution 797system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution --- 53 unchanged lines hidden --- | 781system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter. 782system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data. 783system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 784system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 785system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 786system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 787system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution 788system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution --- 53 unchanged lines hidden --- |