stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
---|---|
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated |
4sim_ticks 29941500 # Number of ticks simulated 5final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 29949500 # Number of ticks simulated 5final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 58660 # Simulator instruction rate (inst/s) 8host_op_rate 68656 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 381226078 # Simulator tick rate (ticks/s) 10host_mem_usage 304332 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host | 7host_inst_rate 110305 # Simulator instruction rate (inst/s) 8host_op_rate 129095 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 716958322 # Simulator tick rate (ticks/s) 10host_mem_usage 313816 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory | 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory |
24system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s) |
32system.physmem.readReqs 421 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 421 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
78system.physmem.totGap 29851000 # Total gap between requests | 78system.physmem.totGap 29858000 # Total gap between requests |
79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 421 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 421 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
93system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see |
95system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 92 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation | 95system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 92 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation |
203system.physmem.totQLat 2218000 # Total ticks spent queuing 204system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 2201000 # Total ticks spent queuing 204system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM |
205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers |
206system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst |
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
208system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s |
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
211system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s |
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 7.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 350 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 7.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 350 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
223system.physmem.avgGap 70904.99 # Average gap between requests | 223system.physmem.avgGap 70921.62 # Average gap between requests |
224system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) --- 140 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls | 224system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) --- 140 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls |
380system.cpu.numCycles 59883 # number of cpu cycles simulated | 380system.cpu.numCycles 59899 # number of cpu cycles simulated |
381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 4605 # Number of instructions committed 384system.cpu.committedOps 5391 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 4605 # Number of instructions committed 384system.cpu.committedOps 5391 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
387system.cpu.cpi 13.003909 # CPI: cycles per instruction 388system.cpu.ipc 0.076900 # IPC: instructions per cycle | 387system.cpu.cpi 13.007383 # CPI: cycles per instruction 388system.cpu.ipc 0.076879 # IPC: instructions per cycle |
389system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked | 389system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked |
390system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped | 390system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped |
391system.cpu.dcache.tags.replacements 0 # number of replacements | 391system.cpu.dcache.tags.replacements 0 # number of replacements |
392system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use | 392system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use |
393system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 393system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. 394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 395system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
397system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor | 397system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor |
398system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 404system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses 405system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses --- 12 unchanged lines hidden (view full) --- 418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses 423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses 425system.cpu.dcache.overall_misses::total 182 # number of overall misses | 398system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy 400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 404system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses 405system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses --- 12 unchanged lines hidden (view full) --- 418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses 423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses 425system.cpu.dcache.overall_misses::total 182 # number of overall misses |
426system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles 427system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles | 426system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles 427system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles |
428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles | 428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles |
430system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles | 430system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles |
434system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 450system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses 451system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses 452system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses 453system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses | 434system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 450system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses 451system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses 452system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses 453system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses |
454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency 455system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency | 454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency 455system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency |
456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency | 456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency |
458system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency 459system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency | 458system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency 459system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency |
462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 468system.cpu.dcache.fast_writes 0 # number of fast writes performed 469system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses | 462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 468system.cpu.dcache.fast_writes 0 # number of fast writes performed 469system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses |
486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles | 486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles |
488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles | 488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles |
490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles 493system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles | 490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles 493system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles |
494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses | 494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses |
502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency | 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency |
504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency | 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency |
506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency 507system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency 509system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency | 506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency 507system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency 509system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency |
510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 511system.cpu.icache.tags.replacements 3 # number of replacements | 510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 511system.cpu.icache.tags.replacements 3 # number of replacements |
512system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use | 512system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use |
513system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. 514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 515system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. 516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 513system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. 514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 515system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. 516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
517system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor 518system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy 519system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy | 517system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor 518system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy 519system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy |
520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id 521system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 522system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id 523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id 524system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses 525system.cpu.icache.tags.data_accesses 4806 # Number of data accesses 526system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits 527system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits 528system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits 529system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits 530system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits 531system.cpu.icache.overall_hits::total 1920 # number of overall hits 532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 537system.cpu.icache.overall_misses::total 322 # number of overall misses | 520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id 521system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 522system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id 523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id 524system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses 525system.cpu.icache.tags.data_accesses 4806 # Number of data accesses 526system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits 527system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits 528system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits 529system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits 530system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits 531system.cpu.icache.overall_hits::total 1920 # number of overall hits 532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 537system.cpu.icache.overall_misses::total 322 # number of overall misses |
538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles 539system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles 540system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles 541system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles 542system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles 543system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles | 538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles 539system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles 540system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles 541system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles 542system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles 543system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles |
544system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) 546system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses 547system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses 548system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses 549system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses 550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses 552system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses 553system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses 554system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses 555system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses | 544system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) 546system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses 547system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses 548system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses 549system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses 550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses 552system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses 553system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses 554system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses 555system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses |
556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency 557system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency 558system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency 559system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency 561system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency | 556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency 557system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency 558system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency 559system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency 561system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency |
562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 568system.cpu.icache.fast_writes 0 # number of fast writes performed 569system.cpu.icache.cache_copies 0 # number of cache copies performed 570system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 571system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 572system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 573system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 574system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 575system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses | 562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 568system.cpu.icache.fast_writes 0 # number of fast writes performed 569system.cpu.icache.cache_copies 0 # number of cache copies performed 570system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 571system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 572system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 573system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 574system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 575system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses |
576system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles | 576system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles |
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588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency | 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency |
594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.l2cache.tags.replacements 0 # number of replacements | 594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.l2cache.tags.replacements 0 # number of replacements |
596system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use | 596system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use |
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601system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor 603system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy | 601system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor 603system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy |
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636system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles 637system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles | 636system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles 637system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles |
638system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles 639system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles | 638system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles 639system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles |
640system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles | 640system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles |
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642system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles 643system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles | 642system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles 643system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles |
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645system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles | 645system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles |
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672system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency 673system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency | 672system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency 673system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency |
674system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency 675system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency | 674system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency 675system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency |
676system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency | 676system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency |
677system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency | 677system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency |
678system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency 679system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency | 678system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency 679system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency |
680system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency | 680system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency |
681system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency | 681system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency |
682system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu.l2cache.fast_writes 0 # number of fast writes performed 689system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 702system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 703system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 704system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 705system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 706system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 707system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses 708system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles 709system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles | 682system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu.l2cache.fast_writes 0 # number of fast writes performed 689system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 702system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 703system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 704system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 705system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 706system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 707system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses 708system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles 709system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles |
710system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles 711system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles | 710system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles 711system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles |
712system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles 713system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles | 712system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles 713system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles |
714system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles | 714system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles |
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718system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles | 718system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles |
719system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles | 719system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles |
720system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 721system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 722system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses 723system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses 724system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses 725system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 728system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 731system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses 732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency 733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency | 720system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 721system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 722system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses 723system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses 724system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses 725system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 728system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 731system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses 732system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency 733system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency |
734system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency 735system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency | 734system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency 735system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency |
736system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency 737system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency | 736system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency 737system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency |
738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency | 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency |
739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency | 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency |
740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency | 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency |
742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency | 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency |
743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency | 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency |
744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
745system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. 746system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data. 747system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 748system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 749system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 750system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
745system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 746system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution 747system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 748system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 749system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution 750system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 751system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) 752system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 753system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 754system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) 755system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 756system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) 757system.cpu.toL2Bus.snoops 0 # Total snoops (count) 758system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram | 751system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 752system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution 753system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 754system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 755system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution 756system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 757system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) 758system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 759system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 760system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) 761system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 762system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) 763system.cpu.toL2Bus.snoops 0 # Total snoops (count) 764system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram |
759system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 760system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 765system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram 766system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram |
761system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 767system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
762system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 763system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram | 768system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram |
764system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 765system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 770system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 771system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
766system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 772system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
767system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 768system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram 769system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 770system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 771system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) 772system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 773system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 774system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 786system.membus.snoop_fanout::stdev 0 # Request fanout histogram 787system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 788system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 789system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 790system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 791system.membus.snoop_fanout::min_value 0 # Request fanout histogram 792system.membus.snoop_fanout::max_value 0 # Request fanout histogram 793system.membus.snoop_fanout::total 421 # Request fanout histogram | 773system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram 775system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 776system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 777system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) 778system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) 779system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) 780system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) --- 11 unchanged lines hidden (view full) --- 792system.membus.snoop_fanout::stdev 0 # Request fanout histogram 793system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 794system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 795system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 796system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 797system.membus.snoop_fanout::min_value 0 # Request fanout histogram 798system.membus.snoop_fanout::max_value 0 # Request fanout histogram 799system.membus.snoop_fanout::total 421 # Request fanout histogram |
794system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks) | 800system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks) |
795system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 796system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) 797system.membus.respLayer1.utilization 7.5 # Layer utilization (%) 798 799---------- End Simulation Statistics ---------- | 801system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 802system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) 803system.membus.respLayer1.utilization 7.5 # Layer utilization (%) 804 805---------- End Simulation Statistics ---------- |