| stats.txt (10827:7f5467f2f8b8) | stats.txt (10852:5b58b4cccfd7) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated |
| 4sim_ticks 30321500 # Number of ticks simulated 5final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 30323500 # Number of ticks simulated 5final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 50258 # Simulator instruction rate (inst/s) 8host_op_rate 58824 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 330783185 # Simulator tick rate (ticks/s) 10host_mem_usage 302404 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host | 7host_inst_rate 117134 # Simulator instruction rate (inst/s) 8host_op_rate 137081 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 770805796 # Simulator tick rate (ticks/s) 10host_mem_usage 310084 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
| 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory | 12sim_insts 4605 # Number of instructions simulated 13sim_ops 5391 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 421 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 421 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 30230000 # Total gap between requests | 78system.physmem.totGap 30232000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 421 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 7.94% 69.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 421 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 108 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 5 7.94% 69.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation |
| 203system.physmem.totQLat 2532750 # Total ticks spent queuing 204system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 2542750 # Total ticks spent queuing 204system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 6.94 # Data bus utilization in percentage 215system.physmem.busUtilRead 6.94 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 349 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 6.94 # Data bus utilization in percentage 215system.physmem.busUtilRead 6.94 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 349 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 71805.23 # Average gap between requests | 223system.physmem.avgGap 71809.98 # Average gap between requests |
| 224system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) --- 140 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls | 224system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) --- 140 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls |
| 380system.cpu.numCycles 60643 # number of cpu cycles simulated | 380system.cpu.numCycles 60647 # number of cpu cycles simulated |
| 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 4605 # Number of instructions committed 384system.cpu.committedOps 5391 # Number of ops (including micro ops) committed | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 4605 # Number of instructions committed 384system.cpu.committedOps 5391 # Number of ops (including micro ops) committed |
| 385system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit | 385system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit |
| 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 387system.cpu.cpi 13.168947 # CPI: cycles per instruction 388system.cpu.ipc 0.075936 # IPC: instructions per cycle 389system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 13.169815 # CPI: cycles per instruction 388system.cpu.ipc 0.075931 # IPC: instructions per cycle 389system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped |
| 391system.cpu.dcache.tags.replacements 0 # number of replacements | 391system.cpu.dcache.tags.replacements 0 # number of replacements |
| 392system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks. | 392system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. |
| 394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. | 394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. |
| 395system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks. | 395system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. |
| 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 397system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy | 397system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy |
| 400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id | 400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id |
| 404system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses 405system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses 406system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits 407system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits | 404system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses 405system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses 406system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits 407system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits |
| 408system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 409system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 410system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 411system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 412system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 413system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 408system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 409system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 410system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 411system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 412system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 413system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 414system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits 415system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits 416system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits 417system.cpu.dcache.overall_hits::total 1895 # number of overall hits | 414system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits 415system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits 416system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits 417system.cpu.dcache.overall_hits::total 1896 # number of overall hits |
| 418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses 423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses 425system.cpu.dcache.overall_misses::total 182 # number of overall misses | 418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses 423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses 425system.cpu.dcache.overall_misses::total 182 # number of overall misses |
| 426system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles 427system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles | 426system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles 427system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles |
| 428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles | 428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles |
| 430system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles 434system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) | 430system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles 434system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses) |
| 436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 442system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses 443system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses 444system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses 445system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses | 442system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses 443system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses 444system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses 445system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses |
| 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses | 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses |
| 450system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses 451system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses 452system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses 453system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses 454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency 455system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency | 450system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses 451system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses 452system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses 453system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses 454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency 455system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency |
| 456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency | 456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency |
| 458system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency 459system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency | 458system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency 459system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency |
| 462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 468system.cpu.dcache.fast_writes 0 # number of fast writes performed 469system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses | 462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 468system.cpu.dcache.fast_writes 0 # number of fast writes performed 469system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses |
| 486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles | 486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles |
| 488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles | 488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles |
| 490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles 493system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles 494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses | 490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9741508 # number of overall MSHR miss cycles 493system.cpu.dcache.overall_mshr_miss_latency::total 9741508 # number of overall MSHR miss cycles 494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses |
| 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses | 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses |
| 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.070294 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.070294 # mshr miss rate for overall accesses 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63723.378641 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63723.378641 # average ReadReq mshr miss latency | 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718 # average ReadReq mshr miss latency |
| 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency | 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency |
| 506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency 507system.cpu.dcache.demand_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency 509system.cpu.dcache.overall_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency | 506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency 507system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency 509system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency |
| 510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 511system.cpu.icache.tags.replacements 3 # number of replacements | 510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 511system.cpu.icache.tags.replacements 3 # number of replacements |
| 512system.cpu.icache.tags.tagsinuse 161.427928 # Cycle average of tags in use | 512system.cpu.icache.tags.tagsinuse 161.448164 # Cycle average of tags in use |
| 513system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. 514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 515system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. 516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 513system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. 514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. 515system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. 516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 517system.cpu.icache.tags.occ_blocks::cpu.inst 161.427928 # Average occupied blocks per requestor 518system.cpu.icache.tags.occ_percent::cpu.inst 0.078822 # Average percentage of cache occupancy 519system.cpu.icache.tags.occ_percent::total 0.078822 # Average percentage of cache occupancy | 517system.cpu.icache.tags.occ_blocks::cpu.inst 161.448164 # Average occupied blocks per requestor 518system.cpu.icache.tags.occ_percent::cpu.inst 0.078832 # Average percentage of cache occupancy 519system.cpu.icache.tags.occ_percent::total 0.078832 # Average percentage of cache occupancy |
| 520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id | 520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id |
| 521system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 522system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id | 521system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 522system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id |
| 523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id 524system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses 525system.cpu.icache.tags.data_accesses 4784 # Number of data accesses 526system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits 527system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits 528system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits 529system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits 530system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits 531system.cpu.icache.overall_hits::total 1909 # number of overall hits 532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 537system.cpu.icache.overall_misses::total 322 # number of overall misses | 523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id 524system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses 525system.cpu.icache.tags.data_accesses 4784 # Number of data accesses 526system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits 527system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits 528system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits 529system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits 530system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits 531system.cpu.icache.overall_hits::total 1909 # number of overall hits 532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 537system.cpu.icache.overall_misses::total 322 # number of overall misses |
| 538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23868000 # number of ReadReq miss cycles 539system.cpu.icache.ReadReq_miss_latency::total 23868000 # number of ReadReq miss cycles 540system.cpu.icache.demand_miss_latency::cpu.inst 23868000 # number of demand (read+write) miss cycles 541system.cpu.icache.demand_miss_latency::total 23868000 # number of demand (read+write) miss cycles 542system.cpu.icache.overall_miss_latency::cpu.inst 23868000 # number of overall miss cycles 543system.cpu.icache.overall_miss_latency::total 23868000 # number of overall miss cycles | 538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23879500 # number of ReadReq miss cycles 539system.cpu.icache.ReadReq_miss_latency::total 23879500 # number of ReadReq miss cycles 540system.cpu.icache.demand_miss_latency::cpu.inst 23879500 # number of demand (read+write) miss cycles 541system.cpu.icache.demand_miss_latency::total 23879500 # number of demand (read+write) miss cycles 542system.cpu.icache.overall_miss_latency::cpu.inst 23879500 # number of overall miss cycles 543system.cpu.icache.overall_miss_latency::total 23879500 # number of overall miss cycles |
| 544system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) 546system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses 547system.cpu.icache.demand_accesses::total 2231 # number of demand (read+write) accesses 548system.cpu.icache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses 549system.cpu.icache.overall_accesses::total 2231 # number of overall (read+write) accesses 550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.144330 # miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_miss_rate::total 0.144330 # miss rate for ReadReq accesses 552system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 # miss rate for demand accesses 553system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses 554system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses 555system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses | 544system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) 546system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses 547system.cpu.icache.demand_accesses::total 2231 # number of demand (read+write) accesses 548system.cpu.icache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses 549system.cpu.icache.overall_accesses::total 2231 # number of overall (read+write) accesses 550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.144330 # miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_miss_rate::total 0.144330 # miss rate for ReadReq accesses 552system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 # miss rate for demand accesses 553system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses 554system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses 555system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses |
| 556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74124.223602 # average ReadReq miss latency 557system.cpu.icache.ReadReq_avg_miss_latency::total 74124.223602 # average ReadReq miss latency 558system.cpu.icache.demand_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency 559system.cpu.icache.demand_avg_miss_latency::total 74124.223602 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency 561system.cpu.icache.overall_avg_miss_latency::total 74124.223602 # average overall miss latency | 556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888 # average ReadReq miss latency 557system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888 # average ReadReq miss latency 558system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency 559system.cpu.icache.demand_avg_miss_latency::total 74159.937888 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency 561system.cpu.icache.overall_avg_miss_latency::total 74159.937888 # average overall miss latency |
| 562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 568system.cpu.icache.fast_writes 0 # number of fast writes performed 569system.cpu.icache.cache_copies 0 # number of cache copies performed 570system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 571system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 572system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 573system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 574system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 575system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses | 562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 568system.cpu.icache.fast_writes 0 # number of fast writes performed 569system.cpu.icache.cache_copies 0 # number of cache copies performed 570system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 571system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 572system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 573system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 574system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 575system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses |
| 576system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23250000 # number of ReadReq MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_latency::total 23250000 # number of ReadReq MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23250000 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::total 23250000 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23250000 # number of overall MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::total 23250000 # number of overall MSHR miss cycles | 576system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23261500 # number of ReadReq MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_latency::total 23261500 # number of ReadReq MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23261500 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::total 23261500 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23261500 # number of overall MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::total 23261500 # number of overall MSHR miss cycles |
| 582system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses 583system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses 584system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses 585system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses 586system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses 587system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses | 582system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses 583system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses 584system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses 585system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses 586system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses 587system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses |
| 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72204.968944 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72204.968944 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency | 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency |
| 594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.l2cache.tags.replacements 0 # number of replacements | 594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 596system.cpu.l2cache.tags.tagsinuse 195.047415 # Cycle average of tags in use | 596system.cpu.l2cache.tags.tagsinuse 195.068888 # Cycle average of tags in use |
| 597system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 598system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 599system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. 600system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 597system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 598system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 599system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. 600system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 601system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.972747 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.data 41.074668 # Average occupied blocks per requestor | 601system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.992766 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.data 41.076122 # Average occupied blocks per requestor |
| 603system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004699 # Average percentage of cache occupancy | 603system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004699 # Average percentage of cache occupancy |
| 604system.cpu.l2cache.tags.occ_percent::cpu.data 0.001253 # Average percentage of cache occupancy 605system.cpu.l2cache.tags.occ_percent::total 0.005952 # Average percentage of cache occupancy | 604system.cpu.l2cache.tags.occ_percent::cpu.data 0.001254 # Average percentage of cache occupancy 605system.cpu.l2cache.tags.occ_percent::total 0.005953 # Average percentage of cache occupancy |
| 606system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id 607system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 608system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 609system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id 610system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses 611system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses 612system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 613system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 624system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 625system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 626system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 627system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses 628system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 629system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 630system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses 631system.cpu.l2cache.overall_misses::total 429 # number of overall misses | 606system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id 607system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 608system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 609system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id 610system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses 611system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses 612system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 613system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 624system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 625system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 626system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 627system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses 628system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 629system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 630system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses 631system.cpu.l2cache.overall_misses::total 429 # number of overall misses |
| 632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22749500 # number of ReadReq miss cycles 633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6226500 # number of ReadReq miss cycles 634system.cpu.l2cache.ReadReq_miss_latency::total 28976000 # number of ReadReq miss cycles | 632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22761000 # number of ReadReq miss cycles 633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6225250 # number of ReadReq miss cycles 634system.cpu.l2cache.ReadReq_miss_latency::total 28986250 # number of ReadReq miss cycles |
| 635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles | 635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles |
| 637system.cpu.l2cache.demand_miss_latency::cpu.inst 22749500 # number of demand (read+write) miss cycles 638system.cpu.l2cache.demand_miss_latency::cpu.data 9362750 # number of demand (read+write) miss cycles 639system.cpu.l2cache.demand_miss_latency::total 32112250 # number of demand (read+write) miss cycles 640system.cpu.l2cache.overall_miss_latency::cpu.inst 22749500 # number of overall miss cycles 641system.cpu.l2cache.overall_miss_latency::cpu.data 9362750 # number of overall miss cycles 642system.cpu.l2cache.overall_miss_latency::total 32112250 # number of overall miss cycles | 637system.cpu.l2cache.demand_miss_latency::cpu.inst 22761000 # number of demand (read+write) miss cycles 638system.cpu.l2cache.demand_miss_latency::cpu.data 9361500 # number of demand (read+write) miss cycles 639system.cpu.l2cache.demand_miss_latency::total 32122500 # number of demand (read+write) miss cycles 640system.cpu.l2cache.overall_miss_latency::cpu.inst 22761000 # number of overall miss cycles 641system.cpu.l2cache.overall_miss_latency::cpu.data 9361500 # number of overall miss cycles 642system.cpu.l2cache.overall_miss_latency::total 32122500 # number of overall miss cycles |
| 643system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) 644system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) 645system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 648system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses 649system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 650system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 657system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 659system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses 661system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 662system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses 664system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses | 643system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) 644system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) 645system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 648system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses 649system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 650system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 657system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 659system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses 661system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 662system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses 664system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses |
| 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74588.524590 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76870.370370 # average ReadReq miss latency 667system.cpu.l2cache.ReadReq_avg_miss_latency::total 75067.357513 # average ReadReq miss latency | 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272 # average ReadReq miss latency 667system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917 # average ReadReq miss latency |
| 668system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency 669system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency | 668system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency 669system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency |
| 670system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency 672system.cpu.l2cache.demand_avg_miss_latency::total 74853.729604 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency 675system.cpu.l2cache.overall_avg_miss_latency::total 74853.729604 # average overall miss latency | 670system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency 672system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency 675system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378 # average overall miss latency |
| 676system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.l2cache.fast_writes 0 # number of fast writes performed 683system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 693system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 694system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 695system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 696system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 698system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 699system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 700system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses | 676system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.l2cache.fast_writes 0 # number of fast writes performed 683system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 693system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 694system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 695system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 696system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 698system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 699system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 700system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses |
| 701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18927000 # number of ReadReq MSHR miss cycles 702system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4781000 # number of ReadReq MSHR miss cycles 703system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23708000 # number of ReadReq MSHR miss cycles | 701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18938500 # number of ReadReq MSHR miss cycles 702system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4780750 # number of ReadReq MSHR miss cycles 703system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23719250 # number of ReadReq MSHR miss cycles |
| 704system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles 705system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles | 704system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles 705system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles |
| 706system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18927000 # number of demand (read+write) MSHR miss cycles 707system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379750 # number of demand (read+write) MSHR miss cycles 708system.cpu.l2cache.demand_mshr_miss_latency::total 26306750 # number of demand (read+write) MSHR miss cycles 709system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18927000 # number of overall MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379750 # number of overall MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency::total 26306750 # number of overall MSHR miss cycles | 706system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18938500 # number of demand (read+write) MSHR miss cycles 707system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379500 # number of demand (read+write) MSHR miss cycles 708system.cpu.l2cache.demand_mshr_miss_latency::total 26318000 # number of demand (read+write) MSHR miss cycles 709system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18938500 # number of overall MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379500 # number of overall MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency::total 26318000 # number of overall MSHR miss cycles |
| 712system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses 715system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 716system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 717system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 718system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 719system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 720system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 722system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses | 712system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses 715system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 716system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 717system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 718system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 719system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 720system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 722system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses |
| 723system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62055.737705 # average ReadReq mshr miss latency 724system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65493.150685 # average ReadReq mshr miss latency 725system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62719.576720 # average ReadReq mshr miss latency | 723system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623 # average ReadReq mshr miss latency 724system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027 # average ReadReq mshr miss latency 725system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624 # average ReadReq mshr miss latency |
| 726system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency 727system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency | 726system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency 727system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency |
| 728system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency 729system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency 730system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency 731system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency 732system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency 733system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency | 728system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency 729system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency 730system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency 731system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency 732system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency 733system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency |
| 734system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 735system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution 736system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 737system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 738system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 739system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) 740system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 741system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 753system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 754system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 755system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 756system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 757system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) 758system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 759system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) 760system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) | 734system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 735system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution 736system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 737system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 738system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 739system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) 740system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 741system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 753system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 754system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 755system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 756system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 757system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) 758system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 759system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) 760system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) |
| 761system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) | 761system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks) |
| 762system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 763system.membus.trans_dist::ReadReq 378 # Transaction distribution 764system.membus.trans_dist::ReadResp 378 # Transaction distribution 765system.membus.trans_dist::ReadExReq 43 # Transaction distribution 766system.membus.trans_dist::ReadExResp 43 # Transaction distribution 767system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 768system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 769system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 774system.membus.snoop_fanout::stdev 0 # Request fanout histogram 775system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 776system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 777system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 778system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 779system.membus.snoop_fanout::min_value 0 # Request fanout histogram 780system.membus.snoop_fanout::max_value 0 # Request fanout histogram 781system.membus.snoop_fanout::total 421 # Request fanout histogram | 762system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 763system.membus.trans_dist::ReadReq 378 # Transaction distribution 764system.membus.trans_dist::ReadResp 378 # Transaction distribution 765system.membus.trans_dist::ReadExReq 43 # Transaction distribution 766system.membus.trans_dist::ReadExResp 43 # Transaction distribution 767system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 768system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 769system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 774system.membus.snoop_fanout::stdev 0 # Request fanout histogram 775system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 776system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 777system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 778system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 779system.membus.snoop_fanout::min_value 0 # Request fanout histogram 780system.membus.snoop_fanout::max_value 0 # Request fanout histogram 781system.membus.snoop_fanout::total 421 # Request fanout histogram |
| 782system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) | 782system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) |
| 783system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) | 783system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) |
| 784system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks) | 784system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks) |
| 785system.membus.respLayer1.utilization 7.4 # Layer utilization (%) 786 787---------- End Simulation Statistics ---------- | 785system.membus.respLayer1.utilization 7.4 # Layer utilization (%) 786 787---------- End Simulation Statistics ---------- |