| stats.txt (10636:9ac724889705) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27981000 # Number of ticks simulated 5final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 30427500 # Number of ticks simulated 5final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 40383 # Simulator instruction rate (inst/s) 8host_op_rate 47269 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 245344554 # Simulator tick rate (ticks/s) 10host_mem_usage 297404 # Number of bytes of host memory used 11host_seconds 0.11 # Real time elapsed on the host | 7host_inst_rate 90683 # Simulator instruction rate (inst/s) 8host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 599001910 # Simulator tick rate (ticks/s) 10host_mem_usage 308040 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 4604 # Number of instructions simulated 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory | 12sim_insts 4604 # Number of instructions simulated 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory 18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 421 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 421 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 27895500 # Total gap between requests | 78system.physmem.totGap 30336000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 421 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 95 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 421 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 95 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation |
| 190system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation | 190system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation |
| 201system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation | 202system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation |
| 202system.physmem.totQLat 2478000 # Total ticks spent queuing 203system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 2605000 # Total ticks spent queuing 204system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers |
| 205system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst |
| 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s |
| 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 210system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s |
| 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 213system.physmem.busUtil 7.52 # Data bus utilization in percentage 214system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 6.92 # Data bus utilization in percentage 215system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads |
| 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 218system.physmem.readRowHits 350 # Number of row buffer hits during reads | 219system.physmem.readRowHits 348 # Number of row buffer hits during reads |
| 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 220system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads |
| 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 222system.physmem.avgGap 66260.10 # Average gap between requests 223system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined 224system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 226system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 72057.01 # Average gap between requests 224system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) |
| 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 229system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 230system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) |
| 231system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) 232system.physmem_0.averagePower 856.107753 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states | 232system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) 233system.physmem_0.averagePower 848.018629 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states |
| 234system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 236system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 238system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) 240system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) |
| 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) |
| 243system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) 246system.physmem_1.averagePower 786.272135 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states | 244system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) 247system.physmem_1.averagePower 782.664197 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states |
| 248system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 250system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 252system.cpu.branchPred.lookups 1926 # Number of BP lookups | 253system.cpu.branchPred.lookups 1927 # Number of BP lookups |
| 253system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect | 254system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect |
| 255system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups | 256system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups |
| 256system.cpu.branchPred.BTBHits 326 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 257system.cpu.branchPred.BTBHits 326 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 258system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage | 259system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage |
| 259system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 261system.cpu_clk_domain.clock 500 # Clock period in ticks 262system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 263system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst --- 104 unchanged lines hidden (view full) --- 371system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 372system.cpu.itb.read_accesses 0 # DTB read accesses 373system.cpu.itb.write_accesses 0 # DTB write accesses 374system.cpu.itb.inst_accesses 0 # ITB inst accesses 375system.cpu.itb.hits 0 # DTB hits 376system.cpu.itb.misses 0 # DTB misses 377system.cpu.itb.accesses 0 # DTB accesses 378system.cpu.workload.num_syscalls 13 # Number of system calls | 260system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst --- 104 unchanged lines hidden (view full) --- 372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses 375system.cpu.itb.inst_accesses 0 # ITB inst accesses 376system.cpu.itb.hits 0 # DTB hits 377system.cpu.itb.misses 0 # DTB misses 378system.cpu.itb.accesses 0 # DTB accesses 379system.cpu.workload.num_syscalls 13 # Number of system calls |
| 379system.cpu.numCycles 55962 # number of cpu cycles simulated | 380system.cpu.numCycles 60855 # number of cpu cycles simulated |
| 380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 382system.cpu.committedInsts 4604 # Number of instructions committed 383system.cpu.committedOps 5390 # Number of ops (including micro ops) committed 384system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit 385system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 383system.cpu.committedInsts 4604 # Number of instructions committed 384system.cpu.committedOps 5390 # Number of ops (including micro ops) committed 385system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit 386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 386system.cpu.cpi 12.155083 # CPI: cycles per instruction 387system.cpu.ipc 0.082270 # IPC: instructions per cycle 388system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked 389system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped | 387system.cpu.cpi 13.217854 # CPI: cycles per instruction 388system.cpu.ipc 0.075655 # IPC: instructions per cycle 389system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked 390system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped |
| 390system.cpu.dcache.tags.replacements 0 # number of replacements | 391system.cpu.dcache.tags.replacements 0 # number of replacements |
| 391system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use 392system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks. | 392system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use 393system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. |
| 393system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. | 394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. |
| 394system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. | 395system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. |
| 395system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 396system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor 397system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy 398system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy | 397system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor 398system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy 399system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy |
| 399system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id | 400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id |
| 400system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 401system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id | 401system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 402system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id |
| 402system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id | 403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id |
| 403system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses 404system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses 405system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits 406system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits | 404system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses 405system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses 406system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits 407system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits |
| 407system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 408system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 409system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 410system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 411system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 412system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 408system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits 409system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 410system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 411system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 412system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 413system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 413system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits 414system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits 415system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits 416system.cpu.dcache.overall_hits::total 1900 # number of overall hits | 414system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 415system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 416system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 417system.cpu.dcache.overall_hits::total 1899 # number of overall hits |
| 417system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 418system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 419system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 420system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 421system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses 422system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 423system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses 424system.cpu.dcache.overall_misses::total 182 # number of overall misses | 418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses 419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses 421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses 423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses 425system.cpu.dcache.overall_misses::total 182 # number of overall misses |
| 425system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles 426system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles 427system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles 428system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles 429system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles 430system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles 431system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles 432system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles 433system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses) 434system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) | 426system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles 427system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles 428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles 429system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles 430system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles 431system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles 432system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles 433system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles 434system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) |
| 435system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 441system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses 442system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses 443system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses 444system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses 445system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses | 442system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses 443system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses 444system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses 445system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses 446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses 447system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses |
| 447system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses | 448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses 449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses |
| 449system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses 450system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses 451system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses 452system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses 453system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency 454system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency 455system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency 456system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency 457system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency 458system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency 459system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency | 450system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses 451system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses 452system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses 453system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses 454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency 455system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency 456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency 457system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency 458system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency 459system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency 460system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency 461system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency |
| 461system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 462system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 463system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 465system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 467system.cpu.dcache.fast_writes 0 # number of fast writes performed 468system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 477system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 478system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 479system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 481system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 482system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 483system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 484system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses | 462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 468system.cpu.dcache.fast_writes 0 # number of fast writes performed 469system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses 483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses 485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses |
| 485system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles 486system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles 488system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles 490system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles 493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses | 486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles 488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles 490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles 493system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles 494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses |
| 495system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses | 496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses |
| 497system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses 498system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses 499system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses 500system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses 501system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency 503system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency | 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency 507system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency 509system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency |
| 509system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 510system.cpu.icache.tags.replacements 3 # number of replacements | 510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 511system.cpu.icache.tags.replacements 3 # number of replacements |
| 511system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use 512system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. | 512system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use 513system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. |
| 513system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. | 514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. |
| 514system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks. | 515system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. |
| 515system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 516system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor 517system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy 518system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy | 517system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor 518system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy 519system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy |
| 519system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id | 520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id |
| 520system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 521system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id | 521system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 522system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id |
| 522system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id | 523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id |
| 523system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses 524system.cpu.icache.tags.data_accesses 4804 # Number of data accesses 525system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits 526system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits 527system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits 528system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits 529system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits 530system.cpu.icache.overall_hits::total 1919 # number of overall hits | 524system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses 525system.cpu.icache.tags.data_accesses 4806 # Number of data accesses 526system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits 527system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits 528system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits 529system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits 530system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits 531system.cpu.icache.overall_hits::total 1920 # number of overall hits |
| 531system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 532system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 533system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 534system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 535system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 536system.cpu.icache.overall_misses::total 322 # number of overall misses | 532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses 533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses 534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses 535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses 536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses 537system.cpu.icache.overall_misses::total 322 # number of overall misses |
| 537system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles 538system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles 539system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles 540system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles 541system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles 542system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles 543system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses) 544system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses 546system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses 547system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses 548system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses 549system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses 550system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses 551system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses 552system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses 553system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses 554system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses 555system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency 556system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency 557system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency 558system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency 559system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency | 538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles 539system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles 540system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles 541system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles 542system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles 543system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles 544system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) 546system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses 547system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses 548system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses 549system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses 550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses 552system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses 553system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses 554system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses 555system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses 556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency 557system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency 558system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency 559system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency 561system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency |
| 561system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 562system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 563system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 565system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 566system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 567system.cpu.icache.fast_writes 0 # number of fast writes performed 568system.cpu.icache.cache_copies 0 # number of cache copies performed 569system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 570system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 571system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 572system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 573system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 574system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses | 562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 568system.cpu.icache.fast_writes 0 # number of fast writes performed 569system.cpu.icache.cache_copies 0 # number of cache copies performed 570system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses 571system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses 572system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses 573system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses 574system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses 575system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses |
| 575system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles 576system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles 577system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles 581system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses 582system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses 583system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses 584system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses 585system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses 586system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses 587system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency 589system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency 591system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency | 576system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles 582system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses 583system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses 584system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses 585system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses 586system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses 587system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency |
| 593system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu.l2cache.tags.replacements 0 # number of replacements | 594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 595system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 595system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use | 596system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use |
| 596system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 597system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 598system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. 599system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 597system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 598system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. 599system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. 600system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 600system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor 601system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy 603system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy 604system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy | 601system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor 603system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy 604system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy 605system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy |
| 605system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id | 606system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id |
| 606system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 607system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id | 607system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 608system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id |
| 608system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id 609system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses 610system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses 611system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 612system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 613system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 614system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 615system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 623system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 624system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 625system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 626system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses 627system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 628system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 629system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses 630system.cpu.l2cache.overall_misses::total 429 # number of overall misses | 609system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id 610system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses 611system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses 612system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits 613system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits 614system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 615system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits 616system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits --- 7 unchanged lines hidden (view full) --- 624system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 625system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 626system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses 627system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses 628system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 629system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses 630system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses 631system.cpu.l2cache.overall_misses::total 429 # number of overall misses |
| 631system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles 632system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles 633system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles 634system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles 635system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles 636system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles 637system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles 638system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles 639system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles 640system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles 641system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles | 632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles 633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles 634system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles 635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles 637system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles 638system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles 639system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles 640system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles 641system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles 642system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles |
| 642system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) 643system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) 644system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) 645system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses 648system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 649system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 656system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 657system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 658system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 661system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses | 643system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) 644system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) 645system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 648system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses 649system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 650system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 657system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 659system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses 661system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses 662system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses 664system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses |
| 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency 668system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency | 665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency 666system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency 667system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency 668system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency 669system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency 670system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency 671system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency 672system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency 674system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency 675system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency |
| 675system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 681system.cpu.l2cache.fast_writes 0 # number of fast writes performed 682system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 692system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 693system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 694system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 695system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 696system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 698system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 699system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses | 676system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.l2cache.fast_writes 0 # number of fast writes performed 683system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 693system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 694system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 695system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses 696system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses 697system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses 698system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses 699system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses 700system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses |
| 700system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles 701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles 702system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles 703system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles 704system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles 705system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles 706system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles 707system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles 708system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles 709system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles | 701system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles 702system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles 703system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles 704system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles 705system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles 706system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles 707system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles 708system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles 709system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles 710system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles |
| 711system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses 712system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses 714system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 715system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 716system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 717system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 718system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 719system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 720system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 721system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses | 712system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses 713system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses 714system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses 715system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 716system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 717system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses 718system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses 719system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses 720system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses 721system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses 722system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses |
| 722system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency 723system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency 724system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency 725system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency 726system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency 727system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency 728system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency 729system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency 730system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency 731system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency 732system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency | 723system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency 724system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency 725system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency 726system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency 727system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency 728system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency 729system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency 730system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency 731system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency 732system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency 733system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency |
| 733system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 734system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution 735system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 736system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 737system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 738system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) 739system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 740system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) 741system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) 742system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 743system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) 744system.cpu.toL2Bus.snoops 0 # Total snoops (count) 745system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram | 734system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 735system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution 736system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution 737system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 738system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 739system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) 740system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 741system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) 742system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) 743system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 744system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) 745system.cpu.toL2Bus.snoops 0 # Total snoops (count) 746system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram |
| 746system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram | 747system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram |
| 747system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 748system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 749system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 751system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 748system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 749system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 750system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 751system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 752system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 752system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 753system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 754system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram 755system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram | 753system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram 754system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 756system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 755system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 757system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 758system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram | 756system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 757system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram |
| 759system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 760system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) 761system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) | 758system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram 759system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) 760system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 762system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks) 763system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 764system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) | 761system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) 762system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 763system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) |
| 765system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 766system.membus.trans_dist::ReadReq 378 # Transaction distribution 767system.membus.trans_dist::ReadResp 378 # Transaction distribution 768system.membus.trans_dist::ReadExReq 43 # Transaction distribution 769system.membus.trans_dist::ReadExResp 43 # Transaction distribution 770system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 771system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 772system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 777system.membus.snoop_fanout::stdev 0 # Request fanout histogram 778system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 779system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 780system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 781system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 782system.membus.snoop_fanout::min_value 0 # Request fanout histogram 783system.membus.snoop_fanout::max_value 0 # Request fanout histogram 784system.membus.snoop_fanout::total 421 # Request fanout histogram | 764system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 765system.membus.trans_dist::ReadReq 378 # Transaction distribution 766system.membus.trans_dist::ReadResp 378 # Transaction distribution 767system.membus.trans_dist::ReadExReq 43 # Transaction distribution 768system.membus.trans_dist::ReadExResp 43 # Transaction distribution 769system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) 770system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) 771system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 776system.membus.snoop_fanout::stdev 0 # Request fanout histogram 777system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 778system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram 779system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 780system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 781system.membus.snoop_fanout::min_value 0 # Request fanout histogram 782system.membus.snoop_fanout::max_value 0 # Request fanout histogram 783system.membus.snoop_fanout::total 421 # Request fanout histogram |
| 785system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) 786system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) 787system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks) 788system.membus.respLayer1.utilization 14.1 # Layer utilization (%) | 784system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) 785system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 786system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) 787system.membus.respLayer1.utilization 7.4 # Layer utilization (%) |
| 789 790---------- End Simulation Statistics ---------- | 788 789---------- End Simulation Statistics ---------- |