| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27981000 # Number of ticks simulated 5final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27981000 # Number of ticks simulated 5final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 65720 # Simulator instruction rate (inst/s) 8host_op_rate 76928 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 399296424 # Simulator tick rate (ticks/s) 10host_mem_usage 250660 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 95550 # Simulator instruction rate (inst/s) 8host_op_rate 111835 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 580422337 # Simulator tick rate (ticks/s) 10host_mem_usage 309164 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 4604 # Number of instructions simulated 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory 17system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory --- 192 unchanged lines hidden (view full) --- 212system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 213system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 214system.physmem.readRowHits 350 # Number of row buffer hits during reads 215system.physmem.writeRowHits 0 # Number of row buffer hits during writes 216system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads 217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 218system.physmem.avgGap 66260.10 # Average gap between requests 219system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined | 12sim_insts 4604 # Number of instructions simulated 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory 17system.physmem.bytes_read::total 26944 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory --- 192 unchanged lines hidden (view full) --- 212system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 213system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 214system.physmem.readRowHits 350 # Number of row buffer hits during reads 215system.physmem.writeRowHits 0 # Number of row buffer hits during writes 216system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads 217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 218system.physmem.avgGap 66260.10 # Average gap between requests 219system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined |
| 220system.physmem.memoryStateTime::IDLE 12000 # Time in different power states 221system.physmem.memoryStateTime::REF 780000 # Time in different power states 222system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 223system.physmem.memoryStateTime::ACT 22840500 # Time in different power states 224system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 225system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) 226system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) 227system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) 228system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) 229system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) 230system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) 231system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 232system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 233system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) 234system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) 235system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ) 236system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ) 237system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ) 238system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ) 239system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ) 240system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ) 241system.physmem.averagePower::0 856.107753 # Core power per rank (mW) 242system.physmem.averagePower::1 786.272135 # Core power per rank (mW) | 220system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 221system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 222system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) 223system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 224system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 225system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) 226system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) 227system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) 228system.physmem_0.averagePower 856.107753 # Core power per rank (mW) 229system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states 230system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 231system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 232system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states 233system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 234system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) 235system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) 236system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) 237system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 238system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 239system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) 240system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) 241system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) 242system.physmem_1.averagePower 786.272135 # Core power per rank (mW) 243system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states 244system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 245system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 246system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states 247system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 243system.cpu.branchPred.lookups 1926 # Number of BP lookups 244system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted 245system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect 246system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups 247system.cpu.branchPred.BTBHits 326 # Number of BTB hits 248system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 249system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage 250system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. 251system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 252system.cpu_clk_domain.clock 500 # Clock period in ticks | 248system.cpu.branchPred.lookups 1926 # Number of BP lookups 249system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted 250system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect 251system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups 252system.cpu.branchPred.BTBHits 326 # Number of BTB hits 253system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 254system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage 255system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. 256system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 257system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 258system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 259system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 260system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 261system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 262system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 263system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 253system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 254system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 255system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 256system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 257system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 258system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 259system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 266system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 267system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 268system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 269system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 270system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 271system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 272system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 273system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 266system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 267system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 268system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 269system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 270system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 271system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 272system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 273system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 279system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 280system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 281system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 282system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 283system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 284system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 285system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 286system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 287system.cpu.dtb.walker.walks 0 # Table walker walks requested 288system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 289system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 290system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 291system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 274system.cpu.dtb.inst_hits 0 # ITB inst hits 275system.cpu.dtb.inst_misses 0 # ITB inst misses 276system.cpu.dtb.read_hits 0 # DTB read hits 277system.cpu.dtb.read_misses 0 # DTB read misses 278system.cpu.dtb.write_hits 0 # DTB write hits 279system.cpu.dtb.write_misses 0 # DTB write misses 280system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 281system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 287system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 288system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 289system.cpu.dtb.read_accesses 0 # DTB read accesses 290system.cpu.dtb.write_accesses 0 # DTB write accesses 291system.cpu.dtb.inst_accesses 0 # ITB inst accesses 292system.cpu.dtb.hits 0 # DTB hits 293system.cpu.dtb.misses 0 # DTB misses 294system.cpu.dtb.accesses 0 # DTB accesses | 295system.cpu.dtb.inst_hits 0 # ITB inst hits 296system.cpu.dtb.inst_misses 0 # ITB inst misses 297system.cpu.dtb.read_hits 0 # DTB read hits 298system.cpu.dtb.read_misses 0 # DTB read misses 299system.cpu.dtb.write_hits 0 # DTB write hits 300system.cpu.dtb.write_misses 0 # DTB write misses 301system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 302system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 308system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 309system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 310system.cpu.dtb.read_accesses 0 # DTB read accesses 311system.cpu.dtb.write_accesses 0 # DTB write accesses 312system.cpu.dtb.inst_accesses 0 # ITB inst accesses 313system.cpu.dtb.hits 0 # DTB hits 314system.cpu.dtb.misses 0 # DTB misses 315system.cpu.dtb.accesses 0 # DTB accesses |
| 316system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 317system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 320system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 323system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 295system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 296system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 297system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 298system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 299system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 300system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 301system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 302system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 308system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 309system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 310system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 311system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 312system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 313system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 314system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 315system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 324system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 325system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 326system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 327system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 328system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 329system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 330system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 331system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 337system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 338system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 339system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 340system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 341system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 342system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 343system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 344system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 345system.cpu.itb.walker.walks 0 # Table walker walks requested 346system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 349system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 352system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 316system.cpu.itb.inst_hits 0 # ITB inst hits 317system.cpu.itb.inst_misses 0 # ITB inst misses 318system.cpu.itb.read_hits 0 # DTB read hits 319system.cpu.itb.read_misses 0 # DTB read misses 320system.cpu.itb.write_hits 0 # DTB write hits 321system.cpu.itb.write_misses 0 # DTB write misses 322system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 323system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 394 unchanged lines hidden --- | 353system.cpu.itb.inst_hits 0 # ITB inst hits 354system.cpu.itb.inst_misses 0 # ITB inst misses 355system.cpu.itb.read_hits 0 # DTB read hits 356system.cpu.itb.read_misses 0 # DTB read misses 357system.cpu.itb.write_hits 0 # DTB write hits 358system.cpu.itb.write_misses 0 # DTB write misses 359system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 360system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 394 unchanged lines hidden --- |