| stats.txt (10433:821cbe4a183b) | stats.txt (10488:7c27480a5031) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27911000 # Number of ticks simulated 5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3437 # Simulator instruction rate (inst/s) 8host_op_rate 4023 # Simulator op (including micro ops) rate (op/s) --- 357 unchanged lines hidden (view full) --- 366system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit 367system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 368system.cpu.cpi 12.124674 # CPI: cycles per instruction 369system.cpu.ipc 0.082476 # IPC: instructions per cycle 370system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked 371system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped 372system.cpu.icache.tags.replacements 3 # number of replacements 373system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27911000 # Number of ticks simulated 5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 3437 # Simulator instruction rate (inst/s) 8host_op_rate 4023 # Simulator op (including micro ops) rate (op/s) --- 357 unchanged lines hidden (view full) --- 366system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit 367system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 368system.cpu.cpi 12.124674 # CPI: cycles per instruction 369system.cpu.ipc 0.082476 # IPC: instructions per cycle 370system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked 371system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped 372system.cpu.icache.tags.replacements 3 # number of replacements 373system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use |
| 374system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. | 374system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks. |
| 375system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. | 375system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. |
| 376system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks. | 376system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks. |
| 377system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 378system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor 379system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy 380system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy 381system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id 382system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 383system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 384system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id | 377system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 378system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor 379system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy 380system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy 381system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id 382system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 383system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 384system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id |
| 385system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses 386system.cpu.icache.tags.data_accesses 4801 # Number of data accesses 387system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits 388system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits 389system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits 390system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits 391system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits 392system.cpu.icache.overall_hits::total 1919 # number of overall hits | 385system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses 386system.cpu.icache.tags.data_accesses 4799 # Number of data accesses 387system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits 388system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits 389system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits 390system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits 391system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits 392system.cpu.icache.overall_hits::total 1918 # number of overall hits |
| 393system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses 394system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses 395system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses 396system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses 397system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses 398system.cpu.icache.overall_misses::total 321 # number of overall misses 399system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles 400system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles 401system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles 402system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles 403system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles 404system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles | 393system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses 394system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses 395system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses 396system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses 397system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses 398system.cpu.icache.overall_misses::total 321 # number of overall misses 399system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles 400system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles 401system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles 402system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles 403system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles 404system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles |
| 405system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses) 406system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses) 407system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses 408system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses 409system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses 410system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses 411system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses 412system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses 413system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses 414system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses 415system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses 416system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses | 405system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses) 406system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses) 407system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses 408system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses 409system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses 410system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses 411system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses 412system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses 413system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses 414system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses 415system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses 416system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses |
| 417system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency 418system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency 419system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency 420system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency 421system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency 422system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency 423system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 424system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 10 unchanged lines hidden (view full) --- 435system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses 436system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses 437system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles 438system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles 439system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles 440system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles 441system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles 442system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles | 417system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency 418system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency 419system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency 420system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency 421system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency 422system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency 423system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 424system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 10 unchanged lines hidden (view full) --- 435system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses 436system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses 437system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles 438system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles 439system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles 440system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles 441system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles 442system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles |
| 443system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses 444system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses 445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses 446system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses 447system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses 448system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses | 443system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses 444system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses 445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses 446system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses 447system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses 448system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses |
| 449system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency 450system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency 451system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency 452system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency 453system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency 454system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency 455system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution --- 261 unchanged lines hidden --- | 449system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency 450system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency 451system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency 452system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency 453system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency 454system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency 455system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution --- 261 unchanged lines hidden --- |