| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27911000 # Number of ticks simulated 5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27911000 # Number of ticks simulated 5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66829 # Simulator instruction rate (inst/s) 8host_op_rate 78212 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 404876453 # Simulator tick rate (ticks/s) 10host_mem_usage 278412 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 116522 # Simulator instruction rate (inst/s) 8host_op_rate 136369 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 705946329 # Simulator tick rate (ticks/s) 10host_mem_usage 304192 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host |
| 12sim_insts 4604 # Number of instructions simulated 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory 17system.physmem.bytes_read::total 26880 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory --- 170 unchanged lines hidden (view full) --- 190system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation | 12sim_insts 4604 # Number of instructions simulated 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory 17system.physmem.bytes_read::total 26880 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory --- 170 unchanged lines hidden (view full) --- 190system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation |
| 198system.physmem.totQLat 2525000 # Total ticks spent queuing 199system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM | 198system.physmem.totQLat 2575500 # Total ticks spent queuing 199system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM |
| 200system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers | 200system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers |
| 201system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst | 201system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst |
| 202system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 202system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 203system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst | 203system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst |
| 204system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s 205system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 206system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s 207system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 208system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 209system.physmem.busUtil 7.52 # Data bus utilization in percentage 210system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads 211system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 218system.physmem.avgGap 66251.19 # Average gap between requests 219system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined 220system.physmem.memoryStateTime::IDLE 12000 # Time in different power states 221system.physmem.memoryStateTime::REF 780000 # Time in different power states 222system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 223system.physmem.memoryStateTime::ACT 22840500 # Time in different power states 224system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 204system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s 205system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 206system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s 207system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 208system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 209system.physmem.busUtil 7.52 # Data bus utilization in percentage 210system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads 211system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 218system.physmem.avgGap 66251.19 # Average gap between requests 219system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined 220system.physmem.memoryStateTime::IDLE 12000 # Time in different power states 221system.physmem.memoryStateTime::REF 780000 # Time in different power states 222system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 223system.physmem.memoryStateTime::ACT 22840500 # Time in different power states 224system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 225system.membus.throughput 963061159 # Throughput (bytes/s) | |
| 226system.membus.trans_dist::ReadReq 377 # Transaction distribution 227system.membus.trans_dist::ReadResp 377 # Transaction distribution 228system.membus.trans_dist::ReadExReq 43 # Transaction distribution 229system.membus.trans_dist::ReadExResp 43 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) | 225system.membus.trans_dist::ReadReq 377 # Transaction distribution 226system.membus.trans_dist::ReadResp 377 # Transaction distribution 227system.membus.trans_dist::ReadExReq 43 # Transaction distribution 228system.membus.trans_dist::ReadExResp 43 # Transaction distribution 229system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) 230system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) |
| 232system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) 233system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) 234system.membus.data_through_bus 26880 # Total data (bytes) 235system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 231system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) 232system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) 233system.membus.snoops 0 # Total snoops (count) 234system.membus.snoop_fanout::samples 420 # Request fanout histogram 235system.membus.snoop_fanout::mean 0 # Request fanout histogram 236system.membus.snoop_fanout::stdev 0 # Request fanout histogram 237system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 238system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram 239system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::min_value 0 # Request fanout histogram 242system.membus.snoop_fanout::max_value 0 # Request fanout histogram 243system.membus.snoop_fanout::total 420 # Request fanout histogram |
| 236system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 237system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 238system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) 239system.membus.respLayer1.utilization 14.1 # Layer utilization (%) 240system.cpu_clk_domain.clock 500 # Clock period in ticks | 244system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 245system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 246system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) 247system.membus.respLayer1.utilization 14.1 # Layer utilization (%) 248system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 241system.cpu.branchPred.lookups 1905 # Number of BP lookups 242system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted | 249system.cpu.branchPred.lookups 1903 # Number of BP lookups 250system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted |
| 243system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect | 251system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect |
| 244system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups | 252system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups |
| 245system.cpu.branchPred.BTBHits 325 # Number of BTB hits 246system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 253system.cpu.branchPred.BTBHits 325 # Number of BTB hits 254system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 247system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage 248system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target. | 255system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage 256system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. |
| 249system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 250system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 251system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 252system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 253system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 254system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 255system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 256system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 79 unchanged lines hidden (view full) --- 336system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 337system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 338system.cpu.committedInsts 4604 # Number of instructions committed 339system.cpu.committedOps 5390 # Number of ops (including micro ops) committed 340system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit 341system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 342system.cpu.cpi 12.124674 # CPI: cycles per instruction 343system.cpu.ipc 0.082476 # IPC: instructions per cycle | 257system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 258system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 259system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 260system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 261system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 262system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 263system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 264system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 79 unchanged lines hidden (view full) --- 344system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 345system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 346system.cpu.committedInsts 4604 # Number of instructions committed 347system.cpu.committedOps 5390 # Number of ops (including micro ops) committed 348system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit 349system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 350system.cpu.cpi 12.124674 # CPI: cycles per instruction 351system.cpu.ipc 0.082476 # IPC: instructions per cycle |
| 344system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked 345system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped | 352system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked 353system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped |
| 346system.cpu.icache.tags.replacements 3 # number of replacements | 354system.cpu.icache.tags.replacements 3 # number of replacements |
| 347system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use 348system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks. | 355system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use 356system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. |
| 349system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. | 357system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. |
| 350system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks. | 358system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks. |
| 351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 359system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 352system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor 353system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy 354system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy | 360system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor 361system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy 362system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy |
| 355system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 358system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id | 363system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 366system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id |
| 359system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses 360system.cpu.icache.tags.data_accesses 4809 # Number of data accesses 361system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits 362system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits 363system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits 364system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits 365system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits 366system.cpu.icache.overall_hits::total 1923 # number of overall hits | 367system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses 368system.cpu.icache.tags.data_accesses 4801 # Number of data accesses 369system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits 370system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits 371system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits 372system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits 373system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits 374system.cpu.icache.overall_hits::total 1919 # number of overall hits |
| 367system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses 368system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses 369system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses 370system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses 371system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses 372system.cpu.icache.overall_misses::total 321 # number of overall misses | 375system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses 376system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses 377system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses 378system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses 379system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses 380system.cpu.icache.overall_misses::total 321 # number of overall misses |
| 373system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles 374system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles 375system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles 376system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles 377system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles 378system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles 379system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses) 381system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses 382system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses 383system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses 384system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses 385system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses 386system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses 387system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses 388system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses 389system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses 390system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses 391system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency 392system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency 393system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency 394system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency 395system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency 396system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency | 381system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles 382system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles 383system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles 384system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles 385system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles 386system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles 387system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses) 388system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses) 389system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses 390system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses 391system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses 392system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses 393system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses 394system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses 395system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses 396system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses 397system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses 398system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses 399system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency 400system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency 401system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency 402system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency 403system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency 404system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency |
| 397system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 400system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 401system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 402system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 403system.cpu.icache.fast_writes 0 # number of fast writes performed 404system.cpu.icache.cache_copies 0 # number of cache copies performed 405system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses 406system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses 407system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses 408system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses 409system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses 410system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses | 405system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 406system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 407system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 408system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 409system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 410system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 411system.cpu.icache.fast_writes 0 # number of fast writes performed 412system.cpu.icache.cache_copies 0 # number of cache copies performed 413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses 414system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses 415system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses 416system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses 417system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses 418system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses |
| 411system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles 412system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles 413system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles 414system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles 415system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles 416system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses 418system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses 419system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses 420system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses 421system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses 422system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses 423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency 425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency 427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency | 419system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles 421system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles 422system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles 423system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles 424system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles 425system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses 426system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses 427system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses 428system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses 429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses 430system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency 432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency 434system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency 436system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency |
| 429system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 437system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 430system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s) | |
| 431system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 435system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) | 438system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 442system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) 443system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 444system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) |
| 438system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) 439system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes) 442system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 445system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) 448system.cpu.toL2Bus.snoops 0 # Total snoops (count) 449system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram |
| 443system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks) 444system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 445system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks) 446system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 447system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) 448system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 449system.cpu.l2cache.tags.replacements 0 # number of replacements | 464system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks) 465system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 466system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks) 467system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 468system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) 469system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 470system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 450system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use | 471system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use |
| 451system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 452system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. 453system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks. 454system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 472system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 473system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. 474system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks. 475system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 455system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor | 476system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor |
| 456system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy 457system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy 458system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 460system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 461system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id 462system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses 463system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses --- 6 unchanged lines hidden (view full) --- 470system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 471system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses 472system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses 473system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 474system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses 475system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses 476system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses 477system.cpu.l2cache.overall_misses::total 428 # number of overall misses | 477system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy 478system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy 479system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id 480system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 481system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 482system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id 483system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses 484system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses --- 6 unchanged lines hidden (view full) --- 491system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 492system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses 493system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses 494system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 495system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses 496system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses 497system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses 498system.cpu.l2cache.overall_misses::total 428 # number of overall misses |
| 478system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles 479system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles | 499system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles 500system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles |
| 480system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles 481system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles | 501system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles 502system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles |
| 482system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles 483system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles 484system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles 485system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles | 503system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles 504system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles 505system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles 506system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles |
| 486system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses) 487system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 488system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) 489system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 490system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses 491system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses 492system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses 493system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses 494system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses 495system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses 496system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 497system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 498system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses 499system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses 500system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses 501system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses | 507system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses) 508system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 509system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) 510system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 511system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses 512system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses 513system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses 514system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses 515system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses 516system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses 517system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 518system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 519system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses 520system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses 521system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses 522system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses |
| 502system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency 503system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency | 523system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency 524system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency |
| 504system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency 505system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency | 525system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency 526system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency |
| 506system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency 507system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency 508system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency 509system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency | 527system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency 528system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency 529system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency 530system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency |
| 510system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 511system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 512system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 513system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 514system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 515system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 516system.cpu.l2cache.fast_writes 0 # number of fast writes performed 517system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 524system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses 525system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses 526system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses 527system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 528system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses 529system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses 530system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses 531system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses | 531system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 532system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 533system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 534system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 535system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 536system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 537system.cpu.l2cache.fast_writes 0 # number of fast writes performed 538system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 6 unchanged lines hidden (view full) --- 545system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses 546system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses 548system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 549system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses 550system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses 551system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses 552system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses |
| 532system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles 533system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles | 553system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles 554system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles |
| 534system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles 535system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles | 555system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles 556system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles |
| 536system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles 537system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles 538system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles 539system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles | 557system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles 558system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles 559system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles 560system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles |
| 540system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses 541system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses 542system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 543system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 544system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses 545system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses 546system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses 547system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses | 561system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses 562system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses 563system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 564system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 565system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses 566system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses 567system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses 568system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses |
| 548system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency 549system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency | 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency |
| 550system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency 551system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency | 571system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency 572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency |
| 552system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency 553system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency 554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency 555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency | 573system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency 574system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency 575system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency 576system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency |
| 556system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 557system.cpu.dcache.tags.replacements 0 # number of replacements | 577system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 578system.cpu.dcache.tags.replacements 0 # number of replacements |
| 558system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use | 579system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use |
| 559system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks. 560system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 561system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. 562system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 580system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 563system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor 564system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy 565system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy | 584system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy |
| 566system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 567system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 568system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 569system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 570system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses 571system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses 572system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 584system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 588system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses 589system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 590system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses 591system.cpu.dcache.overall_misses::total 182 # number of overall misses | 587system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses 593system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits 594system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 605system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses 606system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 607system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses 608system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 609system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses 610system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 611system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses 612system.cpu.dcache.overall_misses::total 182 # number of overall misses |
| 592system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles 593system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles | 613system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles 614system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles |
| 594system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles 595system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles | 615system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles 616system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles |
| 596system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles 597system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles 598system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles 599system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles | 617system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles 618system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles 619system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles 620system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles |
| 600system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses) 601system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses) 602system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) 603system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 604system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) 605system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 606system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) 607system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 612system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses 613system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses 614system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses 615system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 616system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses 617system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses 618system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses 619system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses | 621system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses) 622system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses) 623system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) 624system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 625system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) 626system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 627system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) 628system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 633system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses 634system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses 635system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses 636system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 637system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses 638system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses 639system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses 640system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses |
| 620system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency 621system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency | 641system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency 642system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency |
| 622system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency 623system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency | 643system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency 644system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency |
| 624system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency 625system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency 626system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency 627system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency | 645system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency 646system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency 647system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency 648system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency |
| 628system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 629system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 630system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 632system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 634system.cpu.dcache.fast_writes 0 # number of fast writes performed 635system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 644system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses 645system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 646system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 648system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses 649system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 650system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses 651system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses | 649system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 653system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.cpu.dcache.fast_writes 0 # number of fast writes performed 656system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 665system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses 666system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 667system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 669system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses 670system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 671system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses 672system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses |
| 652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles 653system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles | 673system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles 674system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles |
| 654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles | 675system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles 676system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles |
| 656system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles | 677system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles 678system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles 679system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles 680system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles |
| 660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses 661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses 665system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses 666system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses 667system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses | 681system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses 682system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses 683system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses 684system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 685system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses 686system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses 687system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses 688system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses |
| 668system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency | 689system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency 690system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency |
| 670system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency | 691system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency 692system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency |
| 672system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency 674system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency | 693system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency 694system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency 695system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency 696system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency |
| 676system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 677 678---------- End Simulation Statistics ---------- | 697system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 698 699---------- End Simulation Statistics ---------- |