| stats.txt (10260:384d554cea8c) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3final_tick 27963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 75358 # Simulator instruction rate (inst/s) 5host_mem_usage 292860 # Number of bytes of host memory used 6host_op_rate 93985 # Simulator op (including micro ops) rate (op/s) 7host_seconds 0.06 # Real time elapsed on the host 8host_tick_rate 457698243 # Simulator tick rate (ticks/s) | 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 27911000 # Number of ticks simulated 5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66829 # Simulator instruction rate (inst/s) 8host_op_rate 78212 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 404876453 # Simulator tick rate (ticks/s) 10host_mem_usage 278412 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
|
| 10sim_insts 4604 # Number of instructions simulated | 12sim_insts 4604 # Number of instructions simulated |
| 11sim_ops 5742 # Number of ops (including micro ops) simulated 12sim_seconds 0.000028 # Number of seconds simulated 13sim_ticks 27963000 # Number of ticks simulated | 13sim_ops 5390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 21.219512 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 348 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 1640 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 1370 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 2005 # Number of BP lookups 23system.cpu.branchPred.usedRAS 202 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 4604 # Number of instructions committed 25system.cpu.committedOps 5742 # Number of ops (including micro ops) committed 26system.cpu.cpi 12.147263 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 1318 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 1318 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60367.304348 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 60367.304348 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60667.563107 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60667.563107 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 1203 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 1203 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6942240 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 6942240 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.087253 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.087253 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6248759 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 6248759 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.078149 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.078149 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.179104 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.179104 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66843.023256 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66843.023256 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4600500 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 4600500 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2874250 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 2874250 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 2231 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 63421.648352 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 2049 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 2049 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 11542740 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 11542740 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.081578 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.081578 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9123009 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 9123009 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.065442 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 2231 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63421.648352 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 63421.648352 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62486.363014 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 62486.363014 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 2049 # number of overall hits 117system.cpu.dcache.overall_hits::total 2049 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 11542740 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 11542740 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.081578 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.081578 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses 123system.cpu.dcache.overall_misses::total 182 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9123009 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 9123009 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.065442 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.065442 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 134system.cpu.dcache.tags.avg_refs 14.184932 # Average number of references to valid blocks. 135system.cpu.dcache.tags.data_accesses 4652 # Number of data accesses 136system.cpu.dcache.tags.occ_blocks::cpu.inst 86.831207 # Average occupied blocks per requestor 137system.cpu.dcache.tags.occ_percent::cpu.inst 0.021199 # Average percentage of cache occupancy 138system.cpu.dcache.tags.occ_percent::total 0.021199 # Average percentage of cache occupancy 139system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 140system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 141system.cpu.dcache.tags.replacements 0 # number of replacements 142system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 143system.cpu.dcache.tags.tag_accesses 4652 # Number of tag accesses 144system.cpu.dcache.tags.tagsinuse 86.831207 # Cycle average of tags in use 145system.cpu.dcache.tags.total_refs 2071 # Total number of references to valid blocks. 146system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 147system.cpu.discardedOps 1297 # Number of ops (including micro ops) which were discarded before commit 148system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 149system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 150system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 151system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 152system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 153system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 154system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 155system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 156system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 157system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 158system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 159system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 160system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 161system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 162system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 163system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 164system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 165system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 166system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 167system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 168system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 169system.cpu.dtb.accesses 0 # DTB accesses 170system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 171system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 172system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 173system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 174system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 175system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 176system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 177system.cpu.dtb.hits 0 # DTB hits 178system.cpu.dtb.inst_accesses 0 # ITB inst accesses 179system.cpu.dtb.inst_hits 0 # ITB inst hits 180system.cpu.dtb.inst_misses 0 # ITB inst misses 181system.cpu.dtb.misses 0 # DTB misses 182system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 183system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 184system.cpu.dtb.read_accesses 0 # DTB read accesses 185system.cpu.dtb.read_hits 0 # DTB read hits 186system.cpu.dtb.read_misses 0 # DTB read misses 187system.cpu.dtb.write_accesses 0 # DTB write accesses 188system.cpu.dtb.write_hits 0 # DTB write hits 189system.cpu.dtb.write_misses 0 # DTB write misses 190system.cpu.icache.ReadReq_accesses::cpu.inst 2307 # number of ReadReq accesses(hits+misses) 191system.cpu.icache.ReadReq_accesses::total 2307 # number of ReadReq accesses(hits+misses) 192system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66806.250000 # average ReadReq miss latency 193system.cpu.icache.ReadReq_avg_miss_latency::total 66806.250000 # average ReadReq miss latency 194system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64396.875000 # average ReadReq mshr miss latency 195system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64396.875000 # average ReadReq mshr miss latency 196system.cpu.icache.ReadReq_hits::cpu.inst 1987 # number of ReadReq hits 197system.cpu.icache.ReadReq_hits::total 1987 # number of ReadReq hits 198system.cpu.icache.ReadReq_miss_latency::cpu.inst 21378000 # number of ReadReq miss cycles 199system.cpu.icache.ReadReq_miss_latency::total 21378000 # number of ReadReq miss cycles 200system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138708 # miss rate for ReadReq accesses 201system.cpu.icache.ReadReq_miss_rate::total 0.138708 # miss rate for ReadReq accesses 202system.cpu.icache.ReadReq_misses::cpu.inst 320 # number of ReadReq misses 203system.cpu.icache.ReadReq_misses::total 320 # number of ReadReq misses 204system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20607000 # number of ReadReq MSHR miss cycles 205system.cpu.icache.ReadReq_mshr_miss_latency::total 20607000 # number of ReadReq MSHR miss cycles 206system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for ReadReq accesses 207system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138708 # mshr miss rate for ReadReq accesses 208system.cpu.icache.ReadReq_mshr_misses::cpu.inst 320 # number of ReadReq MSHR misses 209system.cpu.icache.ReadReq_mshr_misses::total 320 # number of ReadReq MSHR misses 210system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 211system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 212system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 213system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 214system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 215system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 216system.cpu.icache.cache_copies 0 # number of cache copies performed 217system.cpu.icache.demand_accesses::cpu.inst 2307 # number of demand (read+write) accesses 218system.cpu.icache.demand_accesses::total 2307 # number of demand (read+write) accesses 219system.cpu.icache.demand_avg_miss_latency::cpu.inst 66806.250000 # average overall miss latency 220system.cpu.icache.demand_avg_miss_latency::total 66806.250000 # average overall miss latency 221system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64396.875000 # average overall mshr miss latency 222system.cpu.icache.demand_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency 223system.cpu.icache.demand_hits::cpu.inst 1987 # number of demand (read+write) hits 224system.cpu.icache.demand_hits::total 1987 # number of demand (read+write) hits 225system.cpu.icache.demand_miss_latency::cpu.inst 21378000 # number of demand (read+write) miss cycles 226system.cpu.icache.demand_miss_latency::total 21378000 # number of demand (read+write) miss cycles 227system.cpu.icache.demand_miss_rate::cpu.inst 0.138708 # miss rate for demand accesses 228system.cpu.icache.demand_miss_rate::total 0.138708 # miss rate for demand accesses 229system.cpu.icache.demand_misses::cpu.inst 320 # number of demand (read+write) misses 230system.cpu.icache.demand_misses::total 320 # number of demand (read+write) misses 231system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20607000 # number of demand (read+write) MSHR miss cycles 232system.cpu.icache.demand_mshr_miss_latency::total 20607000 # number of demand (read+write) MSHR miss cycles 233system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for demand accesses 234system.cpu.icache.demand_mshr_miss_rate::total 0.138708 # mshr miss rate for demand accesses 235system.cpu.icache.demand_mshr_misses::cpu.inst 320 # number of demand (read+write) MSHR misses 236system.cpu.icache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses 237system.cpu.icache.fast_writes 0 # number of fast writes performed 238system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 239system.cpu.icache.overall_accesses::cpu.inst 2307 # number of overall (read+write) accesses 240system.cpu.icache.overall_accesses::total 2307 # number of overall (read+write) accesses 241system.cpu.icache.overall_avg_miss_latency::cpu.inst 66806.250000 # average overall miss latency 242system.cpu.icache.overall_avg_miss_latency::total 66806.250000 # average overall miss latency 243system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64396.875000 # average overall mshr miss latency 244system.cpu.icache.overall_avg_mshr_miss_latency::total 64396.875000 # average overall mshr miss latency 245system.cpu.icache.overall_hits::cpu.inst 1987 # number of overall hits 246system.cpu.icache.overall_hits::total 1987 # number of overall hits 247system.cpu.icache.overall_miss_latency::cpu.inst 21378000 # number of overall miss cycles 248system.cpu.icache.overall_miss_latency::total 21378000 # number of overall miss cycles 249system.cpu.icache.overall_miss_rate::cpu.inst 0.138708 # miss rate for overall accesses 250system.cpu.icache.overall_miss_rate::total 0.138708 # miss rate for overall accesses 251system.cpu.icache.overall_misses::cpu.inst 320 # number of overall misses 252system.cpu.icache.overall_misses::total 320 # number of overall misses 253system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20607000 # number of overall MSHR miss cycles 254system.cpu.icache.overall_mshr_miss_latency::total 20607000 # number of overall MSHR miss cycles 255system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138708 # mshr miss rate for overall accesses 256system.cpu.icache.overall_mshr_miss_rate::total 0.138708 # mshr miss rate for overall accesses 257system.cpu.icache.overall_mshr_misses::cpu.inst 320 # number of overall MSHR misses 258system.cpu.icache.overall_mshr_misses::total 320 # number of overall MSHR misses 259system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 260system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id 261system.cpu.icache.tags.avg_refs 6.209375 # Average number of references to valid blocks. 262system.cpu.icache.tags.data_accesses 4934 # Number of data accesses 263system.cpu.icache.tags.occ_blocks::cpu.inst 161.718196 # Average occupied blocks per requestor 264system.cpu.icache.tags.occ_percent::cpu.inst 0.078964 # Average percentage of cache occupancy 265system.cpu.icache.tags.occ_percent::total 0.078964 # Average percentage of cache occupancy 266system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id 267system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id 268system.cpu.icache.tags.replacements 3 # number of replacements 269system.cpu.icache.tags.sampled_refs 320 # Sample count of references to valid blocks. 270system.cpu.icache.tags.tag_accesses 4934 # Number of tag accesses 271system.cpu.icache.tags.tagsinuse 161.718196 # Cycle average of tags in use 272system.cpu.icache.tags.total_refs 1987 # Total number of references to valid blocks. 273system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 274system.cpu.idleCycles 44980 # Total number of cycles that the CPU has spent unscheduled due to idling 275system.cpu.ipc 0.082323 # IPC: instructions per cycle 276system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 277system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 278system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 279system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 280system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 281system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 282system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 283system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 284system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 285system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 286system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 287system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 288system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 289system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 292system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 293system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 294system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 296system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 297system.cpu.itb.accesses 0 # DTB accesses 298system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 299system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 300system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 301system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 302system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 303system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 304system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 305system.cpu.itb.hits 0 # DTB hits 306system.cpu.itb.inst_accesses 0 # ITB inst accesses 307system.cpu.itb.inst_hits 0 # ITB inst hits 308system.cpu.itb.inst_misses 0 # ITB inst misses 309system.cpu.itb.misses 0 # DTB misses 310system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 311system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 312system.cpu.itb.read_accesses 0 # DTB read accesses 313system.cpu.itb.read_hits 0 # DTB read hits 314system.cpu.itb.read_misses 0 # DTB read misses 315system.cpu.itb.write_accesses 0 # DTB write accesses 316system.cpu.itb.write_hits 0 # DTB write hits 317system.cpu.itb.write_misses 0 # DTB write misses 318system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) 319system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 320system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65831.395349 # average ReadExReq miss latency 321system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65831.395349 # average ReadExReq miss latency 322system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53308.139535 # average ReadExReq mshr miss latency 323system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53308.139535 # average ReadExReq mshr miss latency 324system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2830750 # number of ReadExReq miss cycles 325system.cpu.l2cache.ReadExReq_miss_latency::total 2830750 # number of ReadExReq miss cycles 326system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 327system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 328system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses 329system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 330system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2292250 # number of ReadExReq MSHR miss cycles 331system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2292250 # number of ReadExReq MSHR miss cycles 332system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 333system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses 335system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 336system.cpu.l2cache.ReadReq_accesses::cpu.inst 423 # number of ReadReq accesses(hits+misses) 337system.cpu.l2cache.ReadReq_accesses::total 423 # number of ReadReq accesses(hits+misses) 338system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67507.124352 # average ReadReq miss latency 339system.cpu.l2cache.ReadReq_avg_miss_latency::total 67507.124352 # average ReadReq miss latency 340system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55150.530504 # average ReadReq mshr miss latency 341system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55150.530504 # average ReadReq mshr miss latency 342system.cpu.l2cache.ReadReq_hits::cpu.inst 37 # number of ReadReq hits 343system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits 344system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26057750 # number of ReadReq miss cycles 345system.cpu.l2cache.ReadReq_miss_latency::total 26057750 # number of ReadReq miss cycles 346system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.912530 # miss rate for ReadReq accesses 347system.cpu.l2cache.ReadReq_miss_rate::total 0.912530 # miss rate for ReadReq accesses 348system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses 349system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses 350system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits 351system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 352system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20791750 # number of ReadReq MSHR miss cycles 353system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20791750 # number of ReadReq MSHR miss cycles 354system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891253 # mshr miss rate for ReadReq accesses 355system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.891253 # mshr miss rate for ReadReq accesses 356system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses 357system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses 358system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 359system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 360system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 361system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 362system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu.l2cache.cache_copies 0 # number of cache copies performed 365system.cpu.l2cache.demand_accesses::cpu.inst 466 # number of demand (read+write) accesses 366system.cpu.l2cache.demand_accesses::total 466 # number of demand (read+write) accesses 367system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency 368system.cpu.l2cache.demand_avg_miss_latency::total 67339.160839 # average overall miss latency 369system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency 370system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency 371system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits 372system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits 373system.cpu.l2cache.demand_miss_latency::cpu.inst 28888500 # number of demand (read+write) miss cycles 374system.cpu.l2cache.demand_miss_latency::total 28888500 # number of demand (read+write) miss cycles 375system.cpu.l2cache.demand_miss_rate::cpu.inst 0.920601 # miss rate for demand accesses 376system.cpu.l2cache.demand_miss_rate::total 0.920601 # miss rate for demand accesses 377system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses 378system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses 379system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits 380system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 381system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23084000 # number of demand (read+write) MSHR miss cycles 382system.cpu.l2cache.demand_mshr_miss_latency::total 23084000 # number of demand (read+write) MSHR miss cycles 383system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for demand accesses 384system.cpu.l2cache.demand_mshr_miss_rate::total 0.901288 # mshr miss rate for demand accesses 385system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses 386system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.fast_writes 0 # number of fast writes performed 388system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 389system.cpu.l2cache.overall_accesses::cpu.inst 466 # number of overall (read+write) accesses 390system.cpu.l2cache.overall_accesses::total 466 # number of overall (read+write) accesses 391system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67339.160839 # average overall miss latency 392system.cpu.l2cache.overall_avg_miss_latency::total 67339.160839 # average overall miss latency 393system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54961.904762 # average overall mshr miss latency 394system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54961.904762 # average overall mshr miss latency 395system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits 396system.cpu.l2cache.overall_hits::total 37 # number of overall hits 397system.cpu.l2cache.overall_miss_latency::cpu.inst 28888500 # number of overall miss cycles 398system.cpu.l2cache.overall_miss_latency::total 28888500 # number of overall miss cycles 399system.cpu.l2cache.overall_miss_rate::cpu.inst 0.920601 # miss rate for overall accesses 400system.cpu.l2cache.overall_miss_rate::total 0.920601 # miss rate for overall accesses 401system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses 402system.cpu.l2cache.overall_misses::total 429 # number of overall misses 403system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits 404system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23084000 # number of overall MSHR miss cycles 406system.cpu.l2cache.overall_mshr_miss_latency::total 23084000 # number of overall MSHR miss cycles 407system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.901288 # mshr miss rate for overall accesses 408system.cpu.l2cache.overall_mshr_miss_rate::total 0.901288 # mshr miss rate for overall accesses 409system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses 410system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses 411system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 412system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 413system.cpu.l2cache.tags.avg_refs 0.098143 # Average number of references to valid blocks. 414system.cpu.l2cache.tags.data_accesses 4148 # Number of data accesses 415system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.926239 # Average occupied blocks per requestor 416system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005979 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_percent::total 0.005979 # Average percentage of cache occupancy 418system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id 419system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id 420system.cpu.l2cache.tags.replacements 0 # number of replacements 421system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. 422system.cpu.l2cache.tags.tag_accesses 4148 # Number of tag accesses 423system.cpu.l2cache.tags.tagsinuse 195.926239 # Cycle average of tags in use 424system.cpu.l2cache.tags.total_refs 37 # Total number of references to valid blocks. 425system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 426system.cpu.numCycles 55926 # number of cpu cycles simulated 427system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 428system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 429system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 430system.cpu.tickCycles 10946 # Number of cycles that the CPU actually ticked 431system.cpu.toL2Bus.data_through_bus 29824 # Total data (bytes) 432system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) 433system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 434system.cpu.toL2Bus.pkt_count::total 932 # Packet count per connected master and slave (bytes) 435system.cpu.toL2Bus.reqLayer0.occupancy 233000 # Layer occupancy (ticks) 436system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 437system.cpu.toL2Bus.respLayer0.occupancy 545500 # Layer occupancy (ticks) 438system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 439system.cpu.toL2Bus.respLayer1.occupancy 234491 # Layer occupancy (ticks) 440system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 441system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 442system.cpu.toL2Bus.throughput 1066552230 # Throughput (bytes/s) 443system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20480 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 445system.cpu.toL2Bus.tot_pkt_size::total 29824 # Cumulative packet size per connected master and slave (bytes) 446system.cpu.toL2Bus.trans_dist::ReadReq 423 # Transaction distribution 447system.cpu.toL2Bus.trans_dist::ReadResp 423 # Transaction distribution 448system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 449system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 450system.cpu.workload.num_syscalls 13 # Number of system calls 451system.cpu_clk_domain.clock 500 # Clock period in ticks 452system.membus.data_through_bus 26880 # Total data (bytes) 453system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) 454system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) 455system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) 456system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 457system.membus.respLayer1.occupancy 3923500 # Layer occupancy (ticks) 458system.membus.respLayer1.utilization 14.0 # Layer utilization (%) 459system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 460system.membus.throughput 961270250 # Throughput (bytes/s) 461system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) 462system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) 463system.membus.trans_dist::ReadReq 377 # Transaction distribution 464system.membus.trans_dist::ReadResp 377 # Transaction distribution 465system.membus.trans_dist::ReadExReq 43 # Transaction distribution 466system.membus.trans_dist::ReadExResp 43 # Transaction distribution 467system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 468system.physmem.avgGap 66375.00 # Average gap between requests 469system.physmem.avgMemAccLat 24369.64 # Average memory access latency per DRAM burst 470system.physmem.avgQLat 5619.64 # Average queueing delay per DRAM burst 471system.physmem.avgRdBW 961.27 # Average DRAM read bandwidth in MiByte/s 472system.physmem.avgRdBWSys 961.27 # Average system read bandwidth in MiByte/s 473system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 474system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 475system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 476system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 477system.physmem.busUtil 7.51 # Data bus utilization in percentage 478system.physmem.busUtilRead 7.51 # Data bus utilization in percentage for reads 479system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 480system.physmem.bw_inst_read::cpu.inst 695776562 # Instruction read bandwidth from this memory (bytes/s) 481system.physmem.bw_inst_read::total 695776562 # Instruction read bandwidth from this memory (bytes/s) 482system.physmem.bw_read::cpu.inst 961270250 # Total read bandwidth from this memory (bytes/s) 483system.physmem.bw_read::total 961270250 # Total read bandwidth from this memory (bytes/s) 484system.physmem.bw_total::cpu.inst 961270250 # Total bandwidth to/from this memory (bytes/s) 485system.physmem.bw_total::total 961270250 # Total bandwidth to/from this memory (bytes/s) 486system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation 487system.physmem.bytesPerActivate::mean 389.907692 # Bytes accessed per row activation 488system.physmem.bytesPerActivate::gmean 267.054058 # Bytes accessed per row activation 489system.physmem.bytesPerActivate::stdev 328.238562 # Bytes accessed per row activation 490system.physmem.bytesPerActivate::0-127 11 16.92% 16.92% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::128-255 17 26.15% 43.08% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::256-383 12 18.46% 61.54% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::384-511 7 10.77% 72.31% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::512-639 3 4.62% 76.92% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::640-767 2 3.08% 80.00% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::768-895 3 4.62% 84.62% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::1024-1151 10 15.38% 100.00% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation | 16system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory 17system.physmem.bytes_read::total 26880 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 420 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.readReqs 420 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 499system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM | 32system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM |
| 500system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side | |
| 501system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 502system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 35system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side |
|
| 503system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side | 36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side |
| 504system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory 505system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory 506system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory 507system.physmem.bytes_read::total 26880 # Number of bytes read from this memory 508system.physmem.memoryStateTime::IDLE 12000 # Time in different power states 509system.physmem.memoryStateTime::REF 780000 # Time in different power states 510system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 511system.physmem.memoryStateTime::ACT 22869500 # Time in different power states 512system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue |
| 513system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 514system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 515system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 516system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 517system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory 518system.physmem.num_reads::total 420 # Number of read requests responded to by this memory 519system.physmem.pageHitRate 82.62 # Row buffer hit rate, read and write combined 520system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | |
| 521system.physmem.perBankRdBursts::0 91 # Per bank write bursts 522system.physmem.perBankRdBursts::1 51 # Per bank write bursts 523system.physmem.perBankRdBursts::2 20 # Per bank write bursts 524system.physmem.perBankRdBursts::3 42 # Per bank write bursts | 40system.physmem.perBankRdBursts::0 91 # Per bank write bursts 41system.physmem.perBankRdBursts::1 51 # Per bank write bursts 42system.physmem.perBankRdBursts::2 20 # Per bank write bursts 43system.physmem.perBankRdBursts::3 42 # Per bank write bursts |
| 525system.physmem.perBankRdBursts::4 22 # Per bank write bursts | 44system.physmem.perBankRdBursts::4 23 # Per bank write bursts |
| 526system.physmem.perBankRdBursts::5 41 # Per bank write bursts 527system.physmem.perBankRdBursts::6 36 # Per bank write bursts 528system.physmem.perBankRdBursts::7 12 # Per bank write bursts | 45system.physmem.perBankRdBursts::5 41 # Per bank write bursts 46system.physmem.perBankRdBursts::6 36 # Per bank write bursts 47system.physmem.perBankRdBursts::7 12 # Per bank write bursts |
| 529system.physmem.perBankRdBursts::8 6 # Per bank write bursts | 48system.physmem.perBankRdBursts::8 5 # Per bank write bursts |
| 530system.physmem.perBankRdBursts::9 6 # Per bank write bursts 531system.physmem.perBankRdBursts::10 27 # Per bank write bursts 532system.physmem.perBankRdBursts::11 42 # Per bank write bursts 533system.physmem.perBankRdBursts::12 9 # Per bank write bursts 534system.physmem.perBankRdBursts::13 8 # Per bank write bursts 535system.physmem.perBankRdBursts::14 0 # Per bank write bursts 536system.physmem.perBankRdBursts::15 7 # Per bank write bursts 537system.physmem.perBankWrBursts::0 0 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 545system.physmem.perBankWrBursts::8 0 # Per bank write bursts 546system.physmem.perBankWrBursts::9 0 # Per bank write bursts 547system.physmem.perBankWrBursts::10 0 # Per bank write bursts 548system.physmem.perBankWrBursts::11 0 # Per bank write bursts 549system.physmem.perBankWrBursts::12 0 # Per bank write bursts 550system.physmem.perBankWrBursts::13 0 # Per bank write bursts 551system.physmem.perBankWrBursts::14 0 # Per bank write bursts 552system.physmem.perBankWrBursts::15 0 # Per bank write bursts | 49system.physmem.perBankRdBursts::9 6 # Per bank write bursts 50system.physmem.perBankRdBursts::10 27 # Per bank write bursts 51system.physmem.perBankRdBursts::11 42 # Per bank write bursts 52system.physmem.perBankRdBursts::12 9 # Per bank write bursts 53system.physmem.perBankRdBursts::13 8 # Per bank write bursts 54system.physmem.perBankRdBursts::14 0 # Per bank write bursts 55system.physmem.perBankRdBursts::15 7 # Per bank write bursts 56system.physmem.perBankWrBursts::0 0 # Per bank write bursts --- 7 unchanged lines hidden (view full) --- 64system.physmem.perBankWrBursts::8 0 # Per bank write bursts 65system.physmem.perBankWrBursts::9 0 # Per bank write bursts 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| 553system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see 554system.physmem.rdQLenPdf::1 65 # What read queue length does an incoming req see | 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 74system.physmem.totGap 27825500 # Total gap between requests 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 420 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) 89system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see |
| 555system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 556system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 557system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 558system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 559system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 560system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 561system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 562system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 577system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 578system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 579system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 580system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 581system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 582system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 583system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 584system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 91system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 585system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue 586system.physmem.readPktSize::0 0 # Read request sizes (log2) 587system.physmem.readPktSize::1 0 # Read request sizes (log2) 588system.physmem.readPktSize::2 0 # Read request sizes (log2) 589system.physmem.readPktSize::3 0 # Read request sizes (log2) 590system.physmem.readPktSize::4 0 # Read request sizes (log2) 591system.physmem.readPktSize::5 0 # Read request sizes (log2) 592system.physmem.readPktSize::6 420 # Read request sizes (log2) 593system.physmem.readReqs 420 # Number of read requests accepted 594system.physmem.readRowHitRate 82.62 # Row buffer hit rate for reads 595system.physmem.readRowHits 347 # Number of row buffer hits during reads 596system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 597system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers 598system.physmem.totGap 27877500 # Total gap between requests 599system.physmem.totMemAccLat 10235250 # Total ticks spent from burst creation until serviced by the DRAM 600system.physmem.totQLat 2360250 # Total ticks spent queuing | |
| 601system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 602system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 603system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 604system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 605system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 606system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 607system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 608system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 657system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 658system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 659system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 660system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 661system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 662system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 663system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 664system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 48 unchanged lines hidden (view full) --- 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 665system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 666system.physmem.writePktSize::0 0 # Write request sizes (log2) 667system.physmem.writePktSize::1 0 # Write request sizes (log2) 668system.physmem.writePktSize::2 0 # Write request sizes (log2) 669system.physmem.writePktSize::3 0 # Write request sizes (log2) 670system.physmem.writePktSize::4 0 # Write request sizes (log2) 671system.physmem.writePktSize::5 0 # Write request sizes (log2) 672system.physmem.writePktSize::6 0 # Write request sizes (log2) 673system.physmem.writeReqs 0 # Number of write requests accepted 674system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 185system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation 198system.physmem.totQLat 2525000 # Total ticks spent queuing 199system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM 200system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers 201system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst 202system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 203system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst 204system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s 205system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 206system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s 207system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 208system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 209system.physmem.busUtil 7.52 # Data bus utilization in percentage 210system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads 211system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 212system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing 213system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 214system.physmem.readRowHits 348 # Number of row buffer hits during reads |
| 675system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 215system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 676system.voltage_domain.voltage 1 # Voltage in Volts | 216system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads 217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 218system.physmem.avgGap 66251.19 # Average gap between requests 219system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined 220system.physmem.memoryStateTime::IDLE 12000 # Time in different power states 221system.physmem.memoryStateTime::REF 780000 # Time in different power states 222system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 223system.physmem.memoryStateTime::ACT 22840500 # Time in different power states 224system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 225system.membus.throughput 963061159 # Throughput (bytes/s) 226system.membus.trans_dist::ReadReq 377 # Transaction distribution 227system.membus.trans_dist::ReadResp 377 # Transaction distribution 228system.membus.trans_dist::ReadExReq 43 # Transaction distribution 229system.membus.trans_dist::ReadExResp 43 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) 232system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) 233system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) 234system.membus.data_through_bus 26880 # Total data (bytes) 235system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 236system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) 237system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) 238system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) 239system.membus.respLayer1.utilization 14.1 # Layer utilization (%) 240system.cpu_clk_domain.clock 500 # Clock period in ticks 241system.cpu.branchPred.lookups 1905 # Number of BP lookups 242system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted 243system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect 244system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups 245system.cpu.branchPred.BTBHits 325 # Number of BTB hits 246system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 247system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage 248system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target. 249system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. 250system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 251system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 252system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 253system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 254system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 255system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 256system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 257system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 258system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 259system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 260system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 261system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 262system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 263system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 264system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 265system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 266system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 267system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 268system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 269system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 270system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 271system.cpu.dtb.inst_hits 0 # ITB inst hits 272system.cpu.dtb.inst_misses 0 # ITB inst misses 273system.cpu.dtb.read_hits 0 # DTB read hits 274system.cpu.dtb.read_misses 0 # DTB read misses 275system.cpu.dtb.write_hits 0 # DTB write hits 276system.cpu.dtb.write_misses 0 # DTB write misses 277system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 278system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 279system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 280system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 281system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 282system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 284system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 285system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 286system.cpu.dtb.read_accesses 0 # DTB read accesses 287system.cpu.dtb.write_accesses 0 # DTB write accesses 288system.cpu.dtb.inst_accesses 0 # ITB inst accesses 289system.cpu.dtb.hits 0 # DTB hits 290system.cpu.dtb.misses 0 # DTB misses 291system.cpu.dtb.accesses 0 # DTB accesses 292system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 293system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 294system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 295system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 296system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 297system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 298system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 299system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 300system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 301system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 302system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 303system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 304system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 305system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 306system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 307system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 308system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 309system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 310system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 311system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 312system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 313system.cpu.itb.inst_hits 0 # ITB inst hits 314system.cpu.itb.inst_misses 0 # ITB inst misses 315system.cpu.itb.read_hits 0 # DTB read hits 316system.cpu.itb.read_misses 0 # DTB read misses 317system.cpu.itb.write_hits 0 # DTB write hits 318system.cpu.itb.write_misses 0 # DTB write misses 319system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 320system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 321system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 322system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 323system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 324system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 325system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 326system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 327system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 328system.cpu.itb.read_accesses 0 # DTB read accesses 329system.cpu.itb.write_accesses 0 # DTB write accesses 330system.cpu.itb.inst_accesses 0 # ITB inst accesses 331system.cpu.itb.hits 0 # DTB hits 332system.cpu.itb.misses 0 # DTB misses 333system.cpu.itb.accesses 0 # DTB accesses 334system.cpu.workload.num_syscalls 13 # Number of system calls 335system.cpu.numCycles 55822 # number of cpu cycles simulated 336system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 337system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 338system.cpu.committedInsts 4604 # Number of instructions committed 339system.cpu.committedOps 5390 # Number of ops (including micro ops) committed 340system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit 341system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 342system.cpu.cpi 12.124674 # CPI: cycles per instruction 343system.cpu.ipc 0.082476 # IPC: instructions per cycle 344system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked 345system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped 346system.cpu.icache.tags.replacements 3 # number of replacements 347system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use 348system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks. 349system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. 350system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks. 351system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor 353system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy 354system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy 355system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id 356system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 357system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id 358system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id 359system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses 360system.cpu.icache.tags.data_accesses 4809 # Number of data accesses 361system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits 362system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits 363system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits 364system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits 365system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits 366system.cpu.icache.overall_hits::total 1923 # number of overall hits 367system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses 368system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses 369system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses 370system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses 371system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses 372system.cpu.icache.overall_misses::total 321 # number of overall misses 373system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles 374system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles 375system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles 376system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles 377system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles 378system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles 379system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses) 381system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses 382system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses 383system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses 384system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses 385system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses 386system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses 387system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses 388system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses 389system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses 390system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses 391system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency 392system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency 393system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency 394system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency 395system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency 396system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency 397system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 400system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 401system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 402system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 403system.cpu.icache.fast_writes 0 # number of fast writes performed 404system.cpu.icache.cache_copies 0 # number of cache copies performed 405system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses 406system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses 407system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses 408system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses 409system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses 410system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses 411system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles 412system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles 413system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles 414system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles 415system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles 416system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses 418system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses 419system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses 420system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses 421system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses 422system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses 423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency 424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency 425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency 426system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency 427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency 428system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency 429system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 430system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s) 431system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 433system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 435system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) 437system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) 439system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 440system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes) 442system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 443system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks) 444system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) 445system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks) 446system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 447system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) 448system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 449system.cpu.l2cache.tags.replacements 0 # number of replacements 450system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use 451system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 452system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. 453system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks. 454system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 455system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor 456system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy 457system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy 458system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id 459system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 460system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 461system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id 462system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses 463system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses 464system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits 465system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 466system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits 467system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 468system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits 469system.cpu.l2cache.overall_hits::total 39 # number of overall hits 470system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses 471system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses 472system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses 473system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 474system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses 475system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses 476system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses 477system.cpu.l2cache.overall_misses::total 428 # number of overall misses 478system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles 479system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles 480system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles 481system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles 482system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles 483system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles 484system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles 485system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles 486system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses) 487system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 488system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) 489system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 490system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses 491system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses 492system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses 493system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses 494system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses 495system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses 496system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses 497system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 498system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses 499system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses 500system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses 501system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses 502system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency 503system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency 504system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency 505system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency 506system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency 507system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency 508system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency 509system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency 510system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 511system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 512system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 513system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 514system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 515system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 516system.cpu.l2cache.fast_writes 0 # number of fast writes performed 517system.cpu.l2cache.cache_copies 0 # number of cache copies performed 518system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 519system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits 520system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 521system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 522system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 523system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 524system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses 525system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses 526system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses 527system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 528system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses 529system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses 530system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses 531system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses 532system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles 533system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles 534system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles 535system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles 536system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles 537system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles 538system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles 539system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles 540system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses 541system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses 542system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses 543system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 544system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses 545system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses 546system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses 547system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses 548system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency 549system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency 550system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency 551system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency 552system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency 553system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency 554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency 555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency 556system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 557system.cpu.dcache.tags.replacements 0 # number of replacements 558system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use 559system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks. 560system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 561system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. 562system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 563system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor 564system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy 565system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy 566system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 567system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 568system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id 569system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 570system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses 571system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses 572system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits 573system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits 574system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits 575system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits 576system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits 577system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 578system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits 579system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 580system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits 581system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits 582system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits 583system.cpu.dcache.overall_hits::total 1897 # number of overall hits 584system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses 585system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses 586system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses 587system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses 588system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses 589system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses 590system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses 591system.cpu.dcache.overall_misses::total 182 # number of overall misses 592system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles 593system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles 594system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles 595system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles 596system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles 597system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles 598system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles 599system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles 600system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses) 601system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses) 602system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) 603system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 604system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses) 605system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 606system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses) 607system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 608system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses 609system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses 610system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses 611system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses 612system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses 613system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses 614system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses 615system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses 616system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses 617system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses 618system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses 619system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses 620system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency 621system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency 622system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency 623system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency 624system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency 625system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency 626system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency 627system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency 628system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 629system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 630system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 631system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 632system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 633system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 634system.cpu.dcache.fast_writes 0 # number of fast writes performed 635system.cpu.dcache.cache_copies 0 # number of cache copies performed 636system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 637system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits 638system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 24 # number of WriteReq MSHR hits 639system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits 640system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits 641system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits 642system.cpu.dcache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits 643system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits 644system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses 645system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 646system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses 647system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 648system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses 649system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses 650system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses 651system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses 652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles 653system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles 654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles 655system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles 656system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles 657system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles 658system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles 659system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles 660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses 661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses 662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses 663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 664system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses 665system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses 666system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses 667system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses 668system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency 669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency 670system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency 671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency 672system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency 673system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency 674system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency 675system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency 676system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 677 678---------- End Simulation Statistics ---------- | 677 678---------- End Simulation Statistics ---------- |