4,5c4,5
< sim_ticks 32719500 # Number of ticks simulated
< final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 32617500 # Number of ticks simulated
> final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 128948 # Simulator instruction rate (inst/s)
< host_op_rate 150916 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 915725978 # Simulator tick rate (ticks/s)
< host_mem_usage 269308 # Number of bytes of host memory used
< host_seconds 0.04 # Real time elapsed on the host
---
> host_inst_rate 159604 # Simulator instruction rate (inst/s)
> host_op_rate 186772 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1129633158 # Simulator tick rate (ticks/s)
> host_mem_usage 268376 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 421 # Number of read requests accepted
---
> system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 420 # Number of read requests accepted
35c35
< system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::4 22 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 21 # Per bank write bursts
79c79
< system.physmem.totGap 32621500 # Total gap between requests
---
> system.physmem.totGap 32519500 # Total gap between requests
86c86
< system.physmem.readPktSize::6 421 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 420 # Read request sizes (log2)
94c94
< system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see
191,195c191,195
< system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation
197,200c197,200
< system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation
204,207c204,207
< system.physmem.totQLat 5175000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 5148000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 6.43 # Data bus utilization in percentage
< system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.44 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads
220c220
< system.physmem.readRowHits 347 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 346 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 77485.75 # Average gap between requests
< system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 77427.38 # Average gap between requests
> system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined
228c228
< system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ)
231c231
< system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ)
< system.physmem_0.averagePower 615.992054 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ)
> system.physmem_0.averagePower 616.275926 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank
243,244c243,244
< system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states
250,253c250,253
< system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ)
255,257c255,257
< system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ)
< system.physmem_1.averagePower 556.500000 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ)
> system.physmem_1.averagePower 557.213152 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank
261c261
< system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states
---
> system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states
263,269c263,269
< system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 1968 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 322 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 1965 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 324 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target.
274c274
< system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups.
276,277c276,277
< system.cpu.branchPred.indirectMisses 127 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectMisses 129 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 65439 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 65235 # number of cpu cycles simulated
406c406
< system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit
408,409c408,409
< system.cpu.cpi 14.210423 # CPI: cycles per instruction
< system.cpu.ipc 0.070371 # IPC: instructions per cycle
---
> system.cpu.cpi 14.166124 # CPI: cycles per instruction
> system.cpu.ipc 0.070591 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
453c453
< system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use
458,460c458,460
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy
467c467
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
570c570
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
572,575c572,575
< system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks.
577,580c577,580
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id
582,604c582,604
< system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4896 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits
< system.cpu.icache.overall_hits::total 1965 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
< system.cpu.icache.overall_misses::total 322 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4895 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits
> system.cpu.icache.overall_hits::total 1966 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
> system.cpu.icache.overall_misses::total 321 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles
611,622c611,622
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency
631,655c631,655
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
657c657
< system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use
659,660c659,660
< system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks.
662,667c662,667
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id
669,673c669,673
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
688,689c688,689
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses
692c692
< system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses
694,695c694,695
< system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses
697c697
< system.cpu.l2cache.overall_misses::total 429 # number of overall misses
---
> system.cpu.l2cache.overall_misses::total 428 # number of overall misses
700,701c700,701
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles
704c704
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles
706,707c706,707
< system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles
709c709
< system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles
714,715c714,715
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses)
718c718
< system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses
720,721c720,721
< system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses
723c723
< system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
726,727c726,727
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses
730c730
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses
732,733c732,733
< system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses
735c735
< system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
738,739c738,739
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency
742c742
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency
744,745c744,745
< system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency
747c747
< system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency
762,763c762,763
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses
766c766
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
768,769c768,769
< system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
771c771
< system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
774,775c774,775
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles
778c778
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles
780,781c780,781
< system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles
783c783
< system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles
786,787c786,787
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses
790c790
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses
792,793c792,793
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses
795c795
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
798,799c798,799
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency
802c802
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency
804,805c804,805
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency
807,808c807,808
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter.
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
814,815c814,815
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
819c819
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution
821c821
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes)
823,824c823,824
< system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
826c826
< system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
829,831c829,831
< system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram
833,834c833,834
< system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram
839,840c839,840
< system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks)
842c842
< system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks)
846c846
< system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter.
852,853c852,853
< system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 378 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 377 # Transaction distribution
856,860c856,860
< system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
863c863
< system.membus.snoop_fanout::samples 421 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 420 # Request fanout histogram
867c867
< system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
872,873c872,873
< system.membus.snoop_fanout::total 421 # Request fanout histogram
< system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 420 # Request fanout histogram
> system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
875c875
< system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks)
< sim_ticks 32719500 # Number of ticks simulated
< final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 32617500 # Number of ticks simulated
> final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 128948 # Simulator instruction rate (inst/s)
< host_op_rate 150916 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 915725978 # Simulator tick rate (ticks/s)
< host_mem_usage 269308 # Number of bytes of host memory used
< host_seconds 0.04 # Real time elapsed on the host
---
> host_inst_rate 159604 # Simulator instruction rate (inst/s)
> host_op_rate 186772 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1129633158 # Simulator tick rate (ticks/s)
> host_mem_usage 268376 # Number of bytes of host memory used
> host_seconds 0.03 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 421 # Number of read requests accepted
---
> system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 420 # Number of read requests accepted
35c35
< system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::4 22 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 21 # Per bank write bursts
79c79
< system.physmem.totGap 32621500 # Total gap between requests
---
> system.physmem.totGap 32519500 # Total gap between requests
86c86
< system.physmem.readPktSize::6 421 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 420 # Read request sizes (log2)
94c94
< system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see
191,195c191,195
< system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation
197,200c197,200
< system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation
204,207c204,207
< system.physmem.totQLat 5175000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 5148000 # Total ticks spent queuing
> system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 6.43 # Data bus utilization in percentage
< system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.44 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads
220c220
< system.physmem.readRowHits 347 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 346 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 77485.75 # Average gap between requests
< system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 77427.38 # Average gap between requests
> system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined
228c228
< system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ)
231c231
< system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ)
< system.physmem_0.averagePower 615.992054 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ)
> system.physmem_0.averagePower 616.275926 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank
243,244c243,244
< system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states
250,253c250,253
< system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ)
255,257c255,257
< system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ)
< system.physmem_1.averagePower 556.500000 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ)
> system.physmem_1.averagePower 557.213152 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank
261c261
< system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states
---
> system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states
263,269c263,269
< system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 1968 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 322 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 1965 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 324 # Number of BTB hits
271,272c271,272
< system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target.
274c274
< system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups.
276,277c276,277
< system.cpu.branchPred.indirectMisses 127 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectMisses 129 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches.
279c279
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
309c309
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
339c339
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
369c369
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
400,401c400,401
< system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 65439 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 65235 # number of cpu cycles simulated
406c406
< system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit
408,409c408,409
< system.cpu.cpi 14.210423 # CPI: cycles per instruction
< system.cpu.ipc 0.070371 # IPC: instructions per cycle
---
> system.cpu.cpi 14.166124 # CPI: cycles per instruction
> system.cpu.ipc 0.070591 # IPC: instructions per cycle
449,451c449,451
< system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
453c453
< system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use
458,460c458,460
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy
467c467
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
570c570
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
572,575c572,575
< system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks.
577,580c577,580
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id
582,604c582,604
< system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4896 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits
< system.cpu.icache.overall_hits::total 1965 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
< system.cpu.icache.overall_misses::total 322 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4895 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits
> system.cpu.icache.overall_hits::total 1966 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
> system.cpu.icache.overall_misses::total 321 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles
611,622c611,622
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency
631,655c631,655
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
657c657
< system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use
659,660c659,660
< system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks.
662,667c662,667
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id
669,673c669,673
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
688,689c688,689
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses
692c692
< system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses
694,695c694,695
< system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses
697c697
< system.cpu.l2cache.overall_misses::total 429 # number of overall misses
---
> system.cpu.l2cache.overall_misses::total 428 # number of overall misses
700,701c700,701
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles
704c704
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles
706,707c706,707
< system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles
709c709
< system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles
714,715c714,715
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses)
718c718
< system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses
720,721c720,721
< system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses
723c723
< system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
726,727c726,727
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses
730c730
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses
732,733c732,733
< system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses
735c735
< system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
738,739c738,739
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency
742c742
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency
744,745c744,745
< system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency
747c747
< system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency
762,763c762,763
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses
766c766
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
768,769c768,769
< system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
771c771
< system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
774,775c774,775
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles
778c778
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles
780,781c780,781
< system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles
783c783
< system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles
786,787c786,787
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses
790c790
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses
792,793c792,793
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses
795c795
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
798,799c798,799
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency
802c802
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency
804,805c804,805
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency
807,808c807,808
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter.
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
814,815c814,815
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
819c819
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution
821c821
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 648 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes)
823,824c823,824
< system.cpu.toL2Bus.pkt_count::total 940 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20864 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
826c826
< system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
829,831c829,831
< system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram
833,834c833,834
< system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram
839,840c839,840
< system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks)
842c842
< system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks)
846c846
< system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter.
852,853c852,853
< system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 378 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 377 # Transaction distribution
856,860c856,860
< system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
863c863
< system.membus.snoop_fanout::samples 421 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 420 # Request fanout histogram
867c867
< system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
872,873c872,873
< system.membus.snoop_fanout::total 421 # Request fanout histogram
< system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 420 # Request fanout histogram
> system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
875c875
< system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks)