4,5c4,5
< sim_ticks 30083500 # Number of ticks simulated
< final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30404500 # Number of ticks simulated
> final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 80042 # Simulator instruction rate (inst/s)
< host_op_rate 93682 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 522670316 # Simulator tick rate (ticks/s)
< host_mem_usage 264608 # Number of bytes of host memory used
---
> host_inst_rate 82707 # Simulator instruction rate (inst/s)
> host_op_rate 96800 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 545818868 # Simulator tick rate (ticks/s)
> host_mem_usage 269760 # Number of bytes of host memory used
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 29992500 # Total gap between requests
---
> system.physmem.totGap 30312500 # Total gap between requests
190,205c190,205
< system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
< system.physmem.totQLat 2221000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
> system.physmem.totQLat 2201250 # Total ticks spent queuing
> system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 7.00 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.92 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads
220c220
< system.physmem.readRowHits 350 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 349 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 71241.09 # Average gap between requests
< system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 72001.19 # Average gap between requests
> system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined
228c228
< system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ)
231c231
< system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
233,234c233,234
< system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ)
< system.physmem_0.averagePower 849.295873 # Core power per rank (mW)
---
> system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ)
> system.physmem_0.averagePower 848.348875 # Core power per rank (mW)
238c238
< system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states
245,249c245,249
< system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ)
< system.physmem_1.averagePower 783.273247 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states
---
> system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ)
> system.physmem_1.averagePower 782.690871 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states
254c254
< system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 60167 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 60809 # number of cpu cycles simulated
398,399c398,399
< system.cpu.cpi 13.065581 # CPI: cycles per instruction
< system.cpu.ipc 0.076537 # IPC: instructions per cycle
---
> system.cpu.cpi 13.204995 # CPI: cycles per instruction
> system.cpu.ipc 0.075729 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
439c439
< system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use
444,446c444,446
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy
448,449c448,449
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
453c453
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
474,481c474,481
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles
502,509c502,509
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency
532,539c532,539
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles
548,556c548,556
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
558c558
< system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use
563,565c563,565
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy
567,568c567,568
< system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
572c572
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
585,590c585,590
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles
603,608c603,608
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency
623,628c623,628
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles
635,641c635,641
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
643c643
< system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use
645,646c645,646
< system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks.
648,656c648,656
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
659c659
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
684,695c684,695
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles
722,733c722,733
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency
758,769c758,769
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles
782,793c782,793
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency
800c800
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
832c832,838
< system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
855c861
< system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks)
< sim_ticks 30083500 # Number of ticks simulated
< final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30404500 # Number of ticks simulated
> final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 80042 # Simulator instruction rate (inst/s)
< host_op_rate 93682 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 522670316 # Simulator tick rate (ticks/s)
< host_mem_usage 264608 # Number of bytes of host memory used
---
> host_inst_rate 82707 # Simulator instruction rate (inst/s)
> host_op_rate 96800 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 545818868 # Simulator tick rate (ticks/s)
> host_mem_usage 269760 # Number of bytes of host memory used
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 29992500 # Total gap between requests
---
> system.physmem.totGap 30312500 # Total gap between requests
190,205c190,205
< system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
< system.physmem.totQLat 2221000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
> system.physmem.totQLat 2201250 # Total ticks spent queuing
> system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 7.00 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.92 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads
220c220
< system.physmem.readRowHits 350 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 349 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads
224,225c224,225
< system.physmem.avgGap 71241.09 # Average gap between requests
< system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 72001.19 # Average gap between requests
> system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined
228c228
< system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ)
231c231
< system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
233,234c233,234
< system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ)
< system.physmem_0.averagePower 849.295873 # Core power per rank (mW)
---
> system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ)
> system.physmem_0.averagePower 848.348875 # Core power per rank (mW)
238c238
< system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states
245,249c245,249
< system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ)
< system.physmem_1.averagePower 783.273247 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states
---
> system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ)
> system.physmem_1.averagePower 782.690871 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states
254c254
< system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
269c269
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
299c299
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
329c329
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
359c359
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
390,391c390,391
< system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 60167 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 60809 # number of cpu cycles simulated
398,399c398,399
< system.cpu.cpi 13.065581 # CPI: cycles per instruction
< system.cpu.ipc 0.076537 # IPC: instructions per cycle
---
> system.cpu.cpi 13.204995 # CPI: cycles per instruction
> system.cpu.ipc 0.075729 # IPC: instructions per cycle
435,437c435,437
< system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
439c439
< system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use
444,446c444,446
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy
448,449c448,449
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
453c453
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
474,481c474,481
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles
502,509c502,509
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency
532,539c532,539
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles
548,556c548,556
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
558c558
< system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use
563,565c563,565
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy
567,568c567,568
< system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
572c572
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
585,590c585,590
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles
603,608c603,608
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency
623,628c623,628
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles
635,641c635,641
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
643c643
< system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use
645,646c645,646
< system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks.
648,656c648,656
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
659c659
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
684,695c684,695
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles
722,733c722,733
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency
758,769c758,769
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles
782,793c782,793
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency
800c800
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
832c832,838
< system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
855c861
< system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks)