4,5c4,5
< sim_ticks 29949500 # Number of ticks simulated
< final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29977500 # Number of ticks simulated
> final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
24,31c24,31
< system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 29858000 # Total gap between requests
---
> system.physmem.totGap 29886000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
191,192c191,192
< system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation
194,197c194,197
< system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation
203,204c203,204
< system.physmem.totQLat 2201000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2113500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 7.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 7.02 # Data bus utilization in percentage
> system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
223c223
< system.physmem.avgGap 70921.62 # Average gap between requests
---
> system.physmem.avgGap 70988.12 # Average gap between requests
244,248c244,248
< system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ)
< system.physmem_1.averagePower 784.282403 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states
---
> system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ)
> system.physmem_1.averagePower 784.269066 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 1912 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 347 # Number of BTB hits
---
> system.cpu.branchPred.lookups 1949 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 316 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
261a262,265
> system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
380c384
< system.cpu.numCycles 59899 # number of cpu cycles simulated
---
> system.cpu.numCycles 59955 # number of cpu cycles simulated
385c389
< system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit
387,390c391,429
< system.cpu.cpi 13.007383 # CPI: cycles per instruction
< system.cpu.ipc 0.076879 # IPC: instructions per cycle
< system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 13.019544 # CPI: cycles per instruction
> system.cpu.ipc 0.076808 # IPC: instructions per cycle
> system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
> system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
> system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction
> system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction
> system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction
> system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.op_class_0::total 5391 # Class of committed instruction
> system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
392,393c431,432
< system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
395c434
< system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks.
397,399c436,438
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy
404,407c443,446
< system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
414,417c453,456
< system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits
< system.cpu.dcache.overall_hits::total 1893 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits
> system.cpu.dcache.overall_hits::total 1894 # number of overall hits
426,435c465,474
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
442,447c481,486
< system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses
450,461c489,500
< system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency
486,495c525,534
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses
498,509c537,548
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
511,515c550,554
< system.cpu.icache.tags.replacements 3 # number of replacements
< system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 4 # number of replacements
> system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks.
517,519c556,558
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy
521,522c560,561
< system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
524,561c563,600
< system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
< system.cpu.icache.overall_hits::total 1920 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
< system.cpu.icache.overall_misses::total 322 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4821 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits
> system.cpu.icache.overall_hits::total 1926 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses
> system.cpu.icache.overall_misses::total 323 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency
570,595c609,634
< system.cpu.icache.writebacks::writebacks 3 # number of writebacks
< system.cpu.icache.writebacks::total 3 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
---
> system.cpu.icache.writebacks::writebacks 4 # number of writebacks
> system.cpu.icache.writebacks::total 4 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
598,599c637,638
< system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
601c640
< system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks.
603,607c642,646
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy
609,610c648,649
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
612,617c651,656
< system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
< system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
---
> system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses
> system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits
620c659
< system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
622,623c661,662
< system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
625c664
< system.cpu.l2cache.overall_hits::total 39 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 40 # number of overall hits
638,651c677,690
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
< system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles
> system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
654,655c693,694
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses)
658c697
< system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses
660,661c699,700
< system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses
663c702
< system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses
666,667c705,706
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses
670c709
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses
672,673c711,712
< system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses
675,687c714,726
< system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency
714,725c753,764
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles
728,729c767,768
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses
732c771
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses
734,735c773,774
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses
737,749c776,788
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
751,752c790,791
< system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
757,758c796,797
< system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
761c800
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution
763c802
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes)
765,766c804,805
< system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes)
768c807
< system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes)
770,772c809,811
< system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram
774,775c813,814
< system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram
780,781c819,820
< system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks)
783c822
< system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks)
806c845
< system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
808c847
< system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks)
< sim_ticks 29949500 # Number of ticks simulated
< final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29977500 # Number of ticks simulated
> final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
24,31c24,31
< system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 29858000 # Total gap between requests
---
> system.physmem.totGap 29886000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
191,192c191,192
< system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation
194,197c194,197
< system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation
203,204c203,204
< system.physmem.totQLat 2201000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2113500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 7.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 7.02 # Data bus utilization in percentage
> system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
223c223
< system.physmem.avgGap 70921.62 # Average gap between requests
---
> system.physmem.avgGap 70988.12 # Average gap between requests
244,248c244,248
< system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ)
< system.physmem_1.averagePower 784.282403 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states
---
> system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ)
> system.physmem_1.averagePower 784.269066 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
253,257c253,257
< system.cpu.branchPred.lookups 1912 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 347 # Number of BTB hits
---
> system.cpu.branchPred.lookups 1949 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 316 # Number of BTB hits
259,260c259,260
< system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
261a262,265
> system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
380c384
< system.cpu.numCycles 59899 # number of cpu cycles simulated
---
> system.cpu.numCycles 59955 # number of cpu cycles simulated
385c389
< system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit
387,390c391,429
< system.cpu.cpi 13.007383 # CPI: cycles per instruction
< system.cpu.ipc 0.076879 # IPC: instructions per cycle
< system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 13.019544 # CPI: cycles per instruction
> system.cpu.ipc 0.076808 # IPC: instructions per cycle
> system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
> system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
> system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction
> system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction
> system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction
> system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction
> system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.op_class_0::total 5391 # Class of committed instruction
> system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
392,393c431,432
< system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
395c434
< system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks.
397,399c436,438
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy
404,407c443,446
< system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
414,417c453,456
< system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits
< system.cpu.dcache.overall_hits::total 1893 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits
> system.cpu.dcache.overall_hits::total 1894 # number of overall hits
426,435c465,474
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
442,447c481,486
< system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses
450,461c489,500
< system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency
486,495c525,534
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses
498,509c537,548
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
511,515c550,554
< system.cpu.icache.tags.replacements 3 # number of replacements
< system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 4 # number of replacements
> system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks.
517,519c556,558
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy
521,522c560,561
< system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
524,561c563,600
< system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
< system.cpu.icache.overall_hits::total 1920 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
< system.cpu.icache.overall_misses::total 322 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4821 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits
> system.cpu.icache.overall_hits::total 1926 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses
> system.cpu.icache.overall_misses::total 323 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency
570,595c609,634
< system.cpu.icache.writebacks::writebacks 3 # number of writebacks
< system.cpu.icache.writebacks::total 3 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
---
> system.cpu.icache.writebacks::writebacks 4 # number of writebacks
> system.cpu.icache.writebacks::total 4 # number of writebacks
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
598,599c637,638
< system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
601c640
< system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks.
603,607c642,646
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy
609,610c648,649
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
612,617c651,656
< system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
< system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
---
> system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses
> system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits
620c659
< system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
622,623c661,662
< system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
625c664
< system.cpu.l2cache.overall_hits::total 39 # number of overall hits
---
> system.cpu.l2cache.overall_hits::total 40 # number of overall hits
638,651c677,690
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
< system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles
> system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
654,655c693,694
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses)
658c697
< system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses
660,661c699,700
< system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses
663c702
< system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses
666,667c705,706
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses
670c709
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses
672,673c711,712
< system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses
675,687c714,726
< system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency
714,725c753,764
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles
728,729c767,768
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses
732c771
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses
734,735c773,774
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses
737,749c776,788
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
751,752c790,791
< system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
757,758c796,797
< system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
761c800
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution
763c802
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes)
765,766c804,805
< system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes)
768c807
< system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes)
770,772c809,811
< system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram
774,775c813,814
< system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram
780,781c819,820
< system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks)
783c822
< system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks)
806c845
< system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
808c847
< system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks)