4,5c4,5
< sim_ticks 29941500 # Number of ticks simulated
< final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29949500 # Number of ticks simulated
> final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 58660 # Simulator instruction rate (inst/s)
< host_op_rate 68656 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 381226078 # Simulator tick rate (ticks/s)
< host_mem_usage 304332 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 110305 # Simulator instruction rate (inst/s)
> host_op_rate 129095 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 716958322 # Simulator tick rate (ticks/s)
> host_mem_usage 313816 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 29851000 # Total gap between requests
---
> system.physmem.totGap 29858000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
203,204c203,204
< system.physmem.totQLat 2218000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2201000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 70904.99 # Average gap between requests
---
> system.physmem.avgGap 70921.62 # Average gap between requests
380c380
< system.cpu.numCycles 59883 # number of cpu cycles simulated
---
> system.cpu.numCycles 59899 # number of cpu cycles simulated
387,388c387,388
< system.cpu.cpi 13.003909 # CPI: cycles per instruction
< system.cpu.ipc 0.076900 # IPC: instructions per cycle
---
> system.cpu.cpi 13.007383 # CPI: cycles per instruction
> system.cpu.ipc 0.076879 # IPC: instructions per cycle
390c390
< system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped
---
> system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
392c392
< system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
397c397
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
426,427c426,427
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
430,433c430,433
< system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
454,455c454,455
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
458,461c458,461
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
486,487c486,487
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
490,493c490,493
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
502,503c502,503
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
506,509c506,509
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
512c512
< system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
517,519c517,519
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
538,543c538,543
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
556,561c556,561
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
576,581c576,581
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
588,593c588,593
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
596c596
< system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
601,603c601,603
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
636,637c636,637
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
640c640
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
642,643c642,643
< system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
645c645
< system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
672,673c672,673
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
676c676
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
678,679c678,679
< system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
681c681
< system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
710,711c710,711
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
714c714
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
716,717c716,717
< system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
719c719
< system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
734,735c734,735
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
738c738
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
740,741c740,741
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
743c743
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
744a745,750
> system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
759,760c765,766
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram
762,763c768,769
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram
766c772
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
794c800
< system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
< sim_ticks 29941500 # Number of ticks simulated
< final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29949500 # Number of ticks simulated
> final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 58660 # Simulator instruction rate (inst/s)
< host_op_rate 68656 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 381226078 # Simulator tick rate (ticks/s)
< host_mem_usage 304332 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 110305 # Simulator instruction rate (inst/s)
> host_op_rate 129095 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 716958322 # Simulator tick rate (ticks/s)
> host_mem_usage 313816 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 29851000 # Total gap between requests
---
> system.physmem.totGap 29858000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
203,204c203,204
< system.physmem.totQLat 2218000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2201000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 70904.99 # Average gap between requests
---
> system.physmem.avgGap 70921.62 # Average gap between requests
380c380
< system.cpu.numCycles 59883 # number of cpu cycles simulated
---
> system.cpu.numCycles 59899 # number of cpu cycles simulated
387,388c387,388
< system.cpu.cpi 13.003909 # CPI: cycles per instruction
< system.cpu.ipc 0.076900 # IPC: instructions per cycle
---
> system.cpu.cpi 13.007383 # CPI: cycles per instruction
> system.cpu.ipc 0.076879 # IPC: instructions per cycle
390c390
< system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped
---
> system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
392c392
< system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
397c397
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
426,427c426,427
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
430,433c430,433
< system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
454,455c454,455
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
458,461c458,461
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
486,487c486,487
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
490,493c490,493
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
502,503c502,503
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
506,509c506,509
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
512c512
< system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
517,519c517,519
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
538,543c538,543
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
556,561c556,561
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
576,581c576,581
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
588,593c588,593
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
596c596
< system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
601,603c601,603
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
636,637c636,637
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
640c640
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
642,643c642,643
< system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
645c645
< system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
672,673c672,673
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
676c676
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
678,679c678,679
< system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
681c681
< system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
710,711c710,711
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
714c714
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
716,717c716,717
< system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
719c719
< system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
734,735c734,735
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
738c738
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
740,741c740,741
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
743c743
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
744a745,750
> system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
759,760c765,766
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram
762,763c768,769
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram
766c772
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
794c800
< system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)