4,5c4,5
< sim_ticks 30321500 # Number of ticks simulated
< final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30323500 # Number of ticks simulated
> final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 50258 # Simulator instruction rate (inst/s)
< host_op_rate 58824 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 330783185 # Simulator tick rate (ticks/s)
< host_mem_usage 302404 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 117134 # Simulator instruction rate (inst/s)
> host_op_rate 137081 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 770805796 # Simulator tick rate (ticks/s)
> host_mem_usage 310084 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 30230000 # Total gap between requests
---
> system.physmem.totGap 30232000 # Total gap between requests
203,204c203,204
< system.physmem.totQLat 2532750 # Total ticks spent queuing
< system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2542750 # Total ticks spent queuing
> system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 71805.23 # Average gap between requests
---
> system.physmem.avgGap 71809.98 # Average gap between requests
380c380
< system.cpu.numCycles 60643 # number of cpu cycles simulated
---
> system.cpu.numCycles 60647 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 13.168947 # CPI: cycles per instruction
< system.cpu.ipc 0.075936 # IPC: instructions per cycle
< system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 13.169815 # CPI: cycles per instruction
> system.cpu.ipc 0.075931 # IPC: instructions per cycle
> system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy
404,407c404,407
< system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits
414,417c414,417
< system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits
< system.cpu.dcache.overall_hits::total 1895 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
> system.cpu.dcache.overall_hits::total 1896 # number of overall hits
426,427c426,427
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles
430,435c430,435
< system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses)
442,447c442,447
< system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses
450,455c450,455
< system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency
458,461c458,461
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency
486,487c486,487
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles
490,495c490,495
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9741508 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9741508 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses
498,503c498,503
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070294 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070294 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63723.378641 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63723.378641 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718 # average ReadReq mshr miss latency
506,509c506,509
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency
512c512
< system.cpu.icache.tags.tagsinuse 161.427928 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.448164 # Cycle average of tags in use
517,519c517,519
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.427928 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.078822 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.078822 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.448164 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078832 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078832 # Average percentage of cache occupancy
521,522c521,522
< system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
538,543c538,543
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23868000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23868000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23868000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23868000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23868000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23868000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23879500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23879500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23879500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23879500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23879500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23879500 # number of overall miss cycles
556,561c556,561
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74124.223602 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74124.223602 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74124.223602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74124.223602 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74159.937888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74159.937888 # average overall miss latency
576,581c576,581
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23250000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23250000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23250000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23250000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23250000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23250000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23261500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23261500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23261500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23261500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23261500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23261500 # number of overall MSHR miss cycles
588,593c588,593
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72204.968944 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72204.968944 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency
596c596
< system.cpu.l2cache.tags.tagsinuse 195.047415 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.068888 # Cycle average of tags in use
601,602c601,602
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.972747 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.074668 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.992766 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.076122 # Average occupied blocks per requestor
604,605c604,605
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001253 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005952 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001254 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005953 # Average percentage of cache occupancy
632,634c632,634
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22749500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6226500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28976000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22761000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6225250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 28986250 # number of ReadReq miss cycles
637,642c637,642
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22749500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9362750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 32112250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22749500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9362750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 32112250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22761000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9361500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32122500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22761000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9361500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32122500 # number of overall miss cycles
665,667c665,667
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74588.524590 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76870.370370 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75067.357513 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917 # average ReadReq miss latency
670,675c670,675
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74853.729604 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74853.729604 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378 # average overall miss latency
701,703c701,703
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18927000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4781000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23708000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18938500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4780750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23719250 # number of ReadReq MSHR miss cycles
706,711c706,711
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18927000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26306750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18927000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26306750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18938500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26318000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18938500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26318000 # number of overall MSHR miss cycles
723,725c723,725
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62055.737705 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65493.150685 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62719.576720 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624 # average ReadReq mshr miss latency
728,733c728,733
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency
761c761
< system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks)
782c782
< system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
784c784
< system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks)
< sim_ticks 30321500 # Number of ticks simulated
< final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30323500 # Number of ticks simulated
> final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 50258 # Simulator instruction rate (inst/s)
< host_op_rate 58824 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 330783185 # Simulator tick rate (ticks/s)
< host_mem_usage 302404 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 117134 # Simulator instruction rate (inst/s)
> host_op_rate 137081 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 770805796 # Simulator tick rate (ticks/s)
> host_mem_usage 310084 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 30230000 # Total gap between requests
---
> system.physmem.totGap 30232000 # Total gap between requests
203,204c203,204
< system.physmem.totQLat 2532750 # Total ticks spent queuing
< system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2542750 # Total ticks spent queuing
> system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s
223c223
< system.physmem.avgGap 71805.23 # Average gap between requests
---
> system.physmem.avgGap 71809.98 # Average gap between requests
380c380
< system.cpu.numCycles 60643 # number of cpu cycles simulated
---
> system.cpu.numCycles 60647 # number of cpu cycles simulated
385c385
< system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit
387,390c387,390
< system.cpu.cpi 13.168947 # CPI: cycles per instruction
< system.cpu.ipc 0.075936 # IPC: instructions per cycle
< system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 13.169815 # CPI: cycles per instruction
> system.cpu.ipc 0.075931 # IPC: instructions per cycle
> system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped
392,393c392,393
< system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks.
395c395
< system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks.
397,399c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy
404,407c404,407
< system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits
414,417c414,417
< system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits
< system.cpu.dcache.overall_hits::total 1895 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
> system.cpu.dcache.overall_hits::total 1896 # number of overall hits
426,427c426,427
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles
430,435c430,435
< system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses)
442,447c442,447
< system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses
450,455c450,455
< system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency
458,461c458,461
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency
486,487c486,487
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles
490,495c490,495
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9741508 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9741508 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses
498,503c498,503
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070294 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070294 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63723.378641 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63723.378641 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718 # average ReadReq mshr miss latency
506,509c506,509
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency
512c512
< system.cpu.icache.tags.tagsinuse 161.427928 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.448164 # Cycle average of tags in use
517,519c517,519
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.427928 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.078822 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.078822 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.448164 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078832 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078832 # Average percentage of cache occupancy
521,522c521,522
< system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
538,543c538,543
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 23868000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 23868000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 23868000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 23868000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 23868000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 23868000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23879500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23879500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23879500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23879500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23879500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23879500 # number of overall miss cycles
556,561c556,561
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74124.223602 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74124.223602 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74124.223602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74124.223602 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74159.937888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74159.937888 # average overall miss latency
576,581c576,581
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23250000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23250000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23250000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23250000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23250000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23250000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23261500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23261500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23261500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23261500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23261500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23261500 # number of overall MSHR miss cycles
588,593c588,593
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72204.968944 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72204.968944 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency
596c596
< system.cpu.l2cache.tags.tagsinuse 195.047415 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.068888 # Cycle average of tags in use
601,602c601,602
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.972747 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.074668 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.992766 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.076122 # Average occupied blocks per requestor
604,605c604,605
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001253 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005952 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001254 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005953 # Average percentage of cache occupancy
632,634c632,634
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22749500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6226500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 28976000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22761000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6225250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 28986250 # number of ReadReq miss cycles
637,642c637,642
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22749500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9362750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 32112250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22749500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9362750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 32112250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22761000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9361500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32122500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22761000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9361500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32122500 # number of overall miss cycles
665,667c665,667
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74588.524590 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76870.370370 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 75067.357513 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917 # average ReadReq miss latency
670,675c670,675
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74853.729604 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74853.729604 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378 # average overall miss latency
701,703c701,703
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18927000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4781000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23708000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18938500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4780750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23719250 # number of ReadReq MSHR miss cycles
706,711c706,711
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18927000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26306750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18927000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26306750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18938500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26318000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18938500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26318000 # number of overall MSHR miss cycles
723,725c723,725
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62055.737705 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65493.150685 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62719.576720 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624 # average ReadReq mshr miss latency
728,733c728,733
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency
761c761
< system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks)
782c782
< system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
784c784
< system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks)