3,5c3,5
< sim_seconds 0.000028 # Number of seconds simulated
< sim_ticks 27981000 # Number of ticks simulated
< final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000030 # Number of seconds simulated
> sim_ticks 30427500 # Number of ticks simulated
> final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 40383 # Simulator instruction rate (inst/s)
< host_op_rate 47269 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 245344554 # Simulator tick rate (ticks/s)
< host_mem_usage 297404 # Number of bytes of host memory used
< host_seconds 0.11 # Real time elapsed on the host
---
> host_inst_rate 90683 # Simulator instruction rate (inst/s)
> host_op_rate 106136 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 599001910 # Simulator tick rate (ticks/s)
> host_mem_usage 308040 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 27895500 # Total gap between requests
---
> system.physmem.totGap 30336000 # Total gap between requests
190,200c190,201
< system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
202,203c203,204
< system.physmem.totQLat 2478000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2605000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM
205c206
< system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst
207,208c208,209
< system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s
210c211
< system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s
213,214c214,215
< system.physmem.busUtil 7.52 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.92 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads
218c219
< system.physmem.readRowHits 350 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 348 # Number of row buffer hits during reads
220c221
< system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads
222,226c223,227
< system.physmem.avgGap 66260.10 # Average gap between requests
< system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 72057.01 # Average gap between requests
> system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ)
231,233c232,234
< system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ)
< system.physmem_0.averagePower 856.107753 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states
---
> system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ)
> system.physmem_0.averagePower 848.018629 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states
236c237
< system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
238,240c239,241
< system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
243,247c244,248
< system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ)
< system.physmem_1.averagePower 786.272135 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states
---
> system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ)
> system.physmem_1.averagePower 782.664197 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states
250c251
< system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states
252c253
< system.cpu.branchPred.lookups 1926 # Number of BP lookups
---
> system.cpu.branchPred.lookups 1927 # Number of BP lookups
255c256
< system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups
258c259
< system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage
379c380
< system.cpu.numCycles 55962 # number of cpu cycles simulated
---
> system.cpu.numCycles 60855 # number of cpu cycles simulated
386,389c387,390
< system.cpu.cpi 12.155083 # CPI: cycles per instruction
< system.cpu.ipc 0.082270 # IPC: instructions per cycle
< system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 13.217854 # CPI: cycles per instruction
> system.cpu.ipc 0.075655 # IPC: instructions per cycle
> system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped
391,392c392,393
< system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks.
394c395
< system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks.
396,398c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy
400,401c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
403,406c404,407
< system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits
413,416c414,417
< system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits
< system.cpu.dcache.overall_hits::total 1900 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
> system.cpu.dcache.overall_hits::total 1899 # number of overall hits
425,434c426,435
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses)
441,446c442,447
< system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses
449,460c450,461
< system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency
485,494c486,495
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses
497,508c498,509
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency
511,512c512,513
< system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
514c515
< system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
516,518c517,519
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy
520,521c521,522
< system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
523,530c524,531
< system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
< system.cpu.icache.overall_hits::total 1919 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
> system.cpu.icache.overall_hits::total 1920 # number of overall hits
537,560c538,561
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency
575,592c576,593
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency
595c596
< system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use
600,604c601,605
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy
606,607c607,608
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
631,641c632,642
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles
664,674c665,675
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency
700,710c701,711
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles
722,732c723,733
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency
746c747
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
752,755c753,754
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
757,758c756,757
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
762,764c761,763
< system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
785,788c784,787
< system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
< sim_seconds 0.000028 # Number of seconds simulated
< sim_ticks 27981000 # Number of ticks simulated
< final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000030 # Number of seconds simulated
> sim_ticks 30427500 # Number of ticks simulated
> final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 40383 # Simulator instruction rate (inst/s)
< host_op_rate 47269 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 245344554 # Simulator tick rate (ticks/s)
< host_mem_usage 297404 # Number of bytes of host memory used
< host_seconds 0.11 # Real time elapsed on the host
---
> host_inst_rate 90683 # Simulator instruction rate (inst/s)
> host_op_rate 106136 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 599001910 # Simulator tick rate (ticks/s)
> host_mem_usage 308040 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 27895500 # Total gap between requests
---
> system.physmem.totGap 30336000 # Total gap between requests
190,200c190,201
< system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
202,203c203,204
< system.physmem.totQLat 2478000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2605000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM
205c206
< system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst
207,208c208,209
< system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s
210c211
< system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s
213,214c214,215
< system.physmem.busUtil 7.52 # Data bus utilization in percentage
< system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 6.92 # Data bus utilization in percentage
> system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads
218c219
< system.physmem.readRowHits 350 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 348 # Number of row buffer hits during reads
220c221
< system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads
222,226c223,227
< system.physmem.avgGap 66260.10 # Average gap between requests
< system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 72057.01 # Average gap between requests
> system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ)
231,233c232,234
< system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ)
< system.physmem_0.averagePower 856.107753 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states
---
> system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ)
> system.physmem_0.averagePower 848.018629 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states
236c237
< system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
238,240c239,241
< system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
243,247c244,248
< system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ)
< system.physmem_1.averagePower 786.272135 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states
---
> system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ)
> system.physmem_1.averagePower 782.664197 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states
250c251
< system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states
252c253
< system.cpu.branchPred.lookups 1926 # Number of BP lookups
---
> system.cpu.branchPred.lookups 1927 # Number of BP lookups
255c256
< system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups
258c259
< system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage
379c380
< system.cpu.numCycles 55962 # number of cpu cycles simulated
---
> system.cpu.numCycles 60855 # number of cpu cycles simulated
386,389c387,390
< system.cpu.cpi 12.155083 # CPI: cycles per instruction
< system.cpu.ipc 0.082270 # IPC: instructions per cycle
< system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 13.217854 # CPI: cycles per instruction
> system.cpu.ipc 0.075655 # IPC: instructions per cycle
> system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped
391,392c392,393
< system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks.
394c395
< system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks.
396,398c397,399
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy
400,401c401,402
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
403,406c404,407
< system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits
413,416c414,417
< system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits
< system.cpu.dcache.overall_hits::total 1900 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
> system.cpu.dcache.overall_hits::total 1899 # number of overall hits
425,434c426,435
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses)
441,446c442,447
< system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses
449,460c450,461
< system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency
485,494c486,495
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses
497,508c498,509
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency
511,512c512,513
< system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
514c515
< system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
516,518c517,519
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy
520,521c521,522
< system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
523,530c524,531
< system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
< system.cpu.icache.overall_hits::total 1919 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
> system.cpu.icache.overall_hits::total 1920 # number of overall hits
537,560c538,561
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency
575,592c576,593
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency
595c596
< system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use
600,604c601,605
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy
606,607c607,608
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
631,641c632,642
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles
664,674c665,675
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency
700,710c701,711
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles
722,732c723,733
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency
746c747
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
752,755c753,754
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
757,758c756,757
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
762,764c761,763
< system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks)
785,788c784,787
< system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 7.4 # Layer utilization (%)