4,5c4,5
< sim_ticks 27911000 # Number of ticks simulated
< final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 27981000 # Number of ticks simulated
> final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 3437 # Simulator instruction rate (inst/s)
< host_op_rate 4023 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 20833659 # Simulator tick rate (ticks/s)
< host_mem_usage 251612 # Number of bytes of host memory used
< host_seconds 1.34 # Real time elapsed on the host
---
> host_inst_rate 65720 # Simulator instruction rate (inst/s)
> host_op_rate 76928 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 399296424 # Simulator tick rate (ticks/s)
> host_mem_usage 250660 # Number of bytes of host memory used
> host_seconds 0.07 # Real time elapsed on the host
16,28c16,28
< system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
< system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 420 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 421 # Number of read requests accepted
30c30
< system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
32c32
< system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
35c35
< system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
41c41
< system.physmem.perBankRdBursts::1 51 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 52 # Per bank write bursts
43,44c43,44
< system.physmem.perBankRdBursts::3 42 # Per bank write bursts
< system.physmem.perBankRdBursts::4 23 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 43 # Per bank write bursts
> system.physmem.perBankRdBursts::4 22 # Per bank write bursts
74c74
< system.physmem.totGap 27825500 # Total gap between requests
---
> system.physmem.totGap 27895500 # Total gap between requests
81c81
< system.physmem.readPktSize::6 420 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 421 # Read request sizes (log2)
90c90
< system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
185,201c185,201
< system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
< system.physmem.totQLat 2575500 # Total ticks spent queuing
< system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
> system.physmem.totQLat 2478000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
203,204c203,204
< system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
206c206
< system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
214c214
< system.physmem.readRowHits 348 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 350 # Number of row buffer hits during reads
216c216
< system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
218,219c218,219
< system.physmem.avgGap 66251.19 # Average gap between requests
< system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 66260.10 # Average gap between requests
> system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
225c225
< system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ)
---
> system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ)
227c227
< system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ)
---
> system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ)
235,268c235,244
< system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ)
< system.physmem.averagePower::0 856.166817 # Core power per rank (mW)
< system.physmem.averagePower::1 786.636676 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 377 # Transaction distribution
< system.membus.trans_dist::ReadResp 377 # Transaction distribution
< system.membus.trans_dist::ReadExReq 43 # Transaction distribution
< system.membus.trans_dist::ReadExResp 43 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 420 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 420 # Request fanout histogram
< system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 1903 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
---
> system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ)
> system.physmem.averagePower::0 856.107753 # Core power per rank (mW)
> system.physmem.averagePower::1 786.272135 # Core power per rank (mW)
> system.cpu.branchPred.lookups 1926 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted
270,271c246,247
< system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 325 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 326 # Number of BTB hits
273c249
< system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
275a252
> system.cpu_clk_domain.clock 500 # Clock period in ticks
361c338
< system.cpu.numCycles 55822 # number of cpu cycles simulated
---
> system.cpu.numCycles 55962 # number of cpu cycles simulated
366c343
< system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
368,595c345,348
< system.cpu.cpi 12.124674 # CPI: cycles per instruction
< system.cpu.ipc 0.082476 # IPC: instructions per cycle
< system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 3 # number of replacements
< system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4799 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits
< system.cpu.icache.overall_hits::total 1918 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
< system.cpu.icache.overall_misses::total 321 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
< system.cpu.l2cache.tags.replacements 0 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
< system.cpu.l2cache.overall_hits::total 39 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
< system.cpu.l2cache.overall_misses::total 428 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.cpi 12.155083 # CPI: cycles per instruction
> system.cpu.ipc 0.082270 # IPC: instructions per cycle
> system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
597,598c350,351
< system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
600c353
< system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
602c355
< system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor
606,607c359,360
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
609,612c362,365
< system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
619,622c372,375
< system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits
< system.cpu.dcache.overall_hits::total 1897 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits
> system.cpu.dcache.overall_hits::total 1900 # number of overall hits
631,640c384,393
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4576500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 11285241 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 11285241 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 1169 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
647,652c400,405
< system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
655,666c408,419
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.087416 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.087416 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
691,700c444,453
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6015258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2857500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 8872758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 8872758 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
703,714c456,467
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
715a469,715
> system.cpu.icache.tags.replacements 3 # number of replacements
> system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
> system.cpu.icache.overall_hits::total 1919 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
> system.cpu.icache.overall_misses::total 322 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.icache.fast_writes 0 # number of fast writes performed
> system.cpu.icache.cache_copies 0 # number of cache copies performed
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
> system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.l2cache.tags.replacements 0 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.981905 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005981 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
> system.cpu.l2cache.overall_hits::total 39 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses
> system.cpu.l2cache.overall_misses::total 429 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26149000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2814500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 28963500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 28963500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 425 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 468 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 468 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908235 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916667 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916667 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 378 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 421 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 421 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20940500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2273500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889412 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 378 # Transaction distribution
> system.membus.trans_dist::ReadResp 378 # Transaction distribution
> system.membus.trans_dist::ReadExReq 43 # Transaction distribution
> system.membus.trans_dist::ReadExResp 43 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 421 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 421 # Request fanout histogram
> system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
> system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
< sim_ticks 27911000 # Number of ticks simulated
< final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 27981000 # Number of ticks simulated
> final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 3437 # Simulator instruction rate (inst/s)
< host_op_rate 4023 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 20833659 # Simulator tick rate (ticks/s)
< host_mem_usage 251612 # Number of bytes of host memory used
< host_seconds 1.34 # Real time elapsed on the host
---
> host_inst_rate 65720 # Simulator instruction rate (inst/s)
> host_op_rate 76928 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 399296424 # Simulator tick rate (ticks/s)
> host_mem_usage 250660 # Number of bytes of host memory used
> host_seconds 0.07 # Real time elapsed on the host
16,28c16,28
< system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
< system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 420 # Number of read requests accepted
---
> system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 421 # Number of read requests accepted
30c30
< system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
32c32
< system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
35c35
< system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
41c41
< system.physmem.perBankRdBursts::1 51 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 52 # Per bank write bursts
43,44c43,44
< system.physmem.perBankRdBursts::3 42 # Per bank write bursts
< system.physmem.perBankRdBursts::4 23 # Per bank write bursts
---
> system.physmem.perBankRdBursts::3 43 # Per bank write bursts
> system.physmem.perBankRdBursts::4 22 # Per bank write bursts
74c74
< system.physmem.totGap 27825500 # Total gap between requests
---
> system.physmem.totGap 27895500 # Total gap between requests
81c81
< system.physmem.readPktSize::6 420 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 421 # Read request sizes (log2)
90c90
< system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
185,201c185,201
< system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
< system.physmem.totQLat 2575500 # Total ticks spent queuing
< system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
> system.physmem.totQLat 2478000 # Total ticks spent queuing
> system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst
203,204c203,204
< system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s
206c206
< system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s
214c214
< system.physmem.readRowHits 348 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 350 # Number of row buffer hits during reads
216c216
< system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
218,219c218,219
< system.physmem.avgGap 66251.19 # Average gap between requests
< system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 66260.10 # Average gap between requests
> system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
225c225
< system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ)
---
> system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ)
227c227
< system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ)
---
> system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ)
235,268c235,244
< system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ)
< system.physmem.averagePower::0 856.166817 # Core power per rank (mW)
< system.physmem.averagePower::1 786.636676 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 377 # Transaction distribution
< system.membus.trans_dist::ReadResp 377 # Transaction distribution
< system.membus.trans_dist::ReadExReq 43 # Transaction distribution
< system.membus.trans_dist::ReadExResp 43 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 420 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 420 # Request fanout histogram
< system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 1903 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
---
> system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ)
> system.physmem.averagePower::0 856.107753 # Core power per rank (mW)
> system.physmem.averagePower::1 786.272135 # Core power per rank (mW)
> system.cpu.branchPred.lookups 1926 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted
270,271c246,247
< system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 325 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 326 # Number of BTB hits
273c249
< system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage
275a252
> system.cpu_clk_domain.clock 500 # Clock period in ticks
361c338
< system.cpu.numCycles 55822 # number of cpu cycles simulated
---
> system.cpu.numCycles 55962 # number of cpu cycles simulated
366c343
< system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
368,595c345,348
< system.cpu.cpi 12.124674 # CPI: cycles per instruction
< system.cpu.ipc 0.082476 # IPC: instructions per cycle
< system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
< system.cpu.icache.tags.replacements 3 # number of replacements
< system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4799 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits
< system.cpu.icache.overall_hits::total 1918 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
< system.cpu.icache.overall_misses::total 321 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
< system.cpu.l2cache.tags.replacements 0 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
< system.cpu.l2cache.overall_hits::total 39 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
< system.cpu.l2cache.overall_misses::total 428 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.cpi 12.155083 # CPI: cycles per instruction
> system.cpu.ipc 0.082270 # IPC: instructions per cycle
> system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped
597,598c350,351
< system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks.
600c353
< system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
602c355
< system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor
606,607c359,360
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
609,612c362,365
< system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
619,622c372,375
< system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits
< system.cpu.dcache.overall_hits::total 1897 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits
> system.cpu.dcache.overall_hits::total 1900 # number of overall hits
631,640c384,393
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4576500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 11285241 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 11285241 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 1169 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
647,652c400,405
< system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses
655,666c408,419
< system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.inst 0.087416 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.inst 0.087416 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
691,700c444,453
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6015258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2857500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 8872758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 8872758 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
703,714c456,467
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070125 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency
715a469,715
> system.cpu.icache.tags.replacements 3 # number of replacements
> system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4804 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
> system.cpu.icache.overall_hits::total 1919 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
> system.cpu.icache.overall_misses::total 322 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.icache.fast_writes 0 # number of fast writes performed
> system.cpu.icache.cache_copies 0 # number of cache copies performed
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency
> system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.l2cache.tags.replacements 0 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.981905 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005981 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
> system.cpu.l2cache.overall_hits::total 39 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 429 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 429 # number of overall misses
> system.cpu.l2cache.overall_misses::total 429 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26149000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2814500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 28963500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 28963500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 425 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 468 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 468 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908235 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916667 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916667 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 378 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 421 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 421 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20940500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2273500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889412 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899573 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
> system.membus.trans_dist::ReadReq 378 # Transaction distribution
> system.membus.trans_dist::ReadResp 378 # Transaction distribution
> system.membus.trans_dist::ReadExReq 43 # Transaction distribution
> system.membus.trans_dist::ReadExResp 43 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 421 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 421 # Request fanout histogram
> system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
> system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 14.1 # Layer utilization (%)