7,11c7,11
< host_inst_rate 66829 # Simulator instruction rate (inst/s)
< host_op_rate 78212 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 404876453 # Simulator tick rate (ticks/s)
< host_mem_usage 278412 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 116522 # Simulator instruction rate (inst/s)
> host_op_rate 136369 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 705946329 # Simulator tick rate (ticks/s)
> host_mem_usage 304192 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
198,199c198,199
< system.physmem.totQLat 2525000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2575500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
201c201
< system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
203c203
< system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
225d224
< system.membus.throughput 963061159 # Throughput (bytes/s)
232,235c231,243
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 26880 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 420 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 420 # Request fanout histogram
241,242c249,250
< system.cpu.branchPred.lookups 1905 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 1903 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
244c252
< system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
247,248c255,256
< system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
344,345c352,353
< system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
347,348c355,356
< system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
350c358
< system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks.
352,354c360,362
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
359,366c367,374
< system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4809 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits
< system.cpu.icache.overall_hits::total 1923 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4801 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
> system.cpu.icache.overall_hits::total 1919 # number of overall hits
373,396c381,404
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
411,428c419,436
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
430d437
< system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s)
438,442c445,463
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
450c471
< system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
455c476
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
478,479c499,500
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
482,485c503,506
< system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
502,503c523,524
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
506,509c527,530
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
532,533c553,554
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
536,539c557,560
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
548,549c569,570
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
552,555c573,576
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
558c579
< system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
563,565c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
592,593c613,614
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
596,599c617,620
< system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
620,621c641,642
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
624,627c645,648
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
652,653c673,674
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
656,659c677,680
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
668,669c689,690
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
672,675c693,696
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
< host_inst_rate 66829 # Simulator instruction rate (inst/s)
< host_op_rate 78212 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 404876453 # Simulator tick rate (ticks/s)
< host_mem_usage 278412 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 116522 # Simulator instruction rate (inst/s)
> host_op_rate 136369 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 705946329 # Simulator tick rate (ticks/s)
> host_mem_usage 304192 # Number of bytes of host memory used
> host_seconds 0.04 # Real time elapsed on the host
198,199c198,199
< system.physmem.totQLat 2525000 # Total ticks spent queuing
< system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2575500 # Total ticks spent queuing
> system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
201c201
< system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
203c203
< system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
225d224
< system.membus.throughput 963061159 # Throughput (bytes/s)
232,235c231,243
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 26880 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 420 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 420 # Request fanout histogram
241,242c249,250
< system.cpu.branchPred.lookups 1905 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 1903 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
244c252
< system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
247,248c255,256
< system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
344,345c352,353
< system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
347,348c355,356
< system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks.
350c358
< system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks.
352,354c360,362
< system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
359,366c367,374
< system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4809 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits
< system.cpu.icache.overall_hits::total 1923 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4801 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits
> system.cpu.icache.overall_hits::total 1919 # number of overall hits
373,396c381,404
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
411,428c419,436
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
430d437
< system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s)
438,442c445,463
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
450c471
< system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
455c476
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
478,479c499,500
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
482,485c503,506
< system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
502,503c523,524
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
506,509c527,530
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
532,533c553,554
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
536,539c557,560
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
548,549c569,570
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
552,555c573,576
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
558c579
< system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
563,565c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
592,593c613,614
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
596,599c617,620
< system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
620,621c641,642
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
624,627c645,648
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
652,653c673,674
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
656,659c677,680
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
668,669c689,690
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
672,675c693,696
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency