1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000030 # Number of seconds simulated
4sim_ticks 29977500 # Number of ticks simulated
5final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000030 # Number of seconds simulated
4sim_ticks 29977500 # Number of ticks simulated
5final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 146522 # Simulator instruction rate (inst/s)
8host_op_rate 171470 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 953185288 # Simulator tick rate (ticks/s)
10host_mem_usage 264656 # Number of bytes of host memory used
| 7host_inst_rate 147440 # Simulator instruction rate (inst/s)
8host_op_rate 172555 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 959274014 # Simulator tick rate (ticks/s)
10host_mem_usage 309288 # Number of bytes of host memory used
|
11host_seconds 0.03 # Real time elapsed on the host
12sim_insts 4605 # Number of instructions simulated
13sim_ops 5391 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
| 11host_seconds 0.03 # Real time elapsed on the host
12sim_insts 4605 # Number of instructions simulated
13sim_ops 5391 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
|
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 421 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 91 # Per bank write bursts
45system.physmem.perBankRdBursts::1 52 # Per bank write bursts
46system.physmem.perBankRdBursts::2 20 # Per bank write bursts
47system.physmem.perBankRdBursts::3 43 # Per bank write bursts
48system.physmem.perBankRdBursts::4 22 # Per bank write bursts
49system.physmem.perBankRdBursts::5 41 # Per bank write bursts
50system.physmem.perBankRdBursts::6 36 # Per bank write bursts
51system.physmem.perBankRdBursts::7 12 # Per bank write bursts
52system.physmem.perBankRdBursts::8 5 # Per bank write bursts
53system.physmem.perBankRdBursts::9 6 # Per bank write bursts
54system.physmem.perBankRdBursts::10 27 # Per bank write bursts
55system.physmem.perBankRdBursts::11 42 # Per bank write bursts
56system.physmem.perBankRdBursts::12 9 # Per bank write bursts
57system.physmem.perBankRdBursts::13 8 # Per bank write bursts
58system.physmem.perBankRdBursts::14 0 # Per bank write bursts
59system.physmem.perBankRdBursts::15 7 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 29886000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 421 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
203system.physmem.totQLat 2113500 # Total ticks spent queuing
204system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 7.02 # Data bus utilization in percentage
215system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 350 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 70988.12 # Average gap between requests
224system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 20068140 # Total energy per rank (pJ)
233system.physmem_0.averagePower 849.669860 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states
235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ)
247system.physmem_1.averagePower 784.269066 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states
249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
| 17system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
19system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 421 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 91 # Per bank write bursts
46system.physmem.perBankRdBursts::1 52 # Per bank write bursts
47system.physmem.perBankRdBursts::2 20 # Per bank write bursts
48system.physmem.perBankRdBursts::3 43 # Per bank write bursts
49system.physmem.perBankRdBursts::4 22 # Per bank write bursts
50system.physmem.perBankRdBursts::5 41 # Per bank write bursts
51system.physmem.perBankRdBursts::6 36 # Per bank write bursts
52system.physmem.perBankRdBursts::7 12 # Per bank write bursts
53system.physmem.perBankRdBursts::8 5 # Per bank write bursts
54system.physmem.perBankRdBursts::9 6 # Per bank write bursts
55system.physmem.perBankRdBursts::10 27 # Per bank write bursts
56system.physmem.perBankRdBursts::11 42 # Per bank write bursts
57system.physmem.perBankRdBursts::12 9 # Per bank write bursts
58system.physmem.perBankRdBursts::13 8 # Per bank write bursts
59system.physmem.perBankRdBursts::14 0 # Per bank write bursts
60system.physmem.perBankRdBursts::15 7 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 29886000 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 421 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
204system.physmem.totQLat 2113500 # Total ticks spent queuing
205system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM
206system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
207system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst
210system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 7.02 # Data bus utilization in percentage
216system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220system.physmem.readRowHits 350 # Number of row buffer hits during reads
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224system.physmem.avgGap 70988.12 # Average gap between requests
225system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
233system.physmem_0.totalEnergy 20068140 # Total energy per rank (pJ)
234system.physmem_0.averagePower 849.669860 # Core power per rank (mW)
235system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states
236system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
238system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
240system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
241system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
242system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
244system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
245system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ)
246system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ)
247system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ)
248system.physmem_1.averagePower 784.269066 # Core power per rank (mW)
249system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states
250system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
252system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
| 254system.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
253system.cpu.branchPred.lookups 1949 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 316 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
262system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups.
263system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
264system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
265system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
266system.cpu_clk_domain.clock 500 # Clock period in ticks
| 255system.cpu.branchPred.lookups 1949 # Number of BP lookups
256system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
257system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
258system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
259system.cpu.branchPred.BTBHits 316 # Number of BTB hits
260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
261system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage
262system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
263system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
264system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups.
265system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
266system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
267system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
268system.cpu_clk_domain.clock 500 # Clock period in ticks
|
| 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
285system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
286system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
287system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
278system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
279system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
280system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
281system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
282system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
283system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
288system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
289system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
290system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
| 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
296system.cpu.dtb.walker.walks 0 # Table walker walks requested
297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.inst_hits 0 # ITB inst hits
305system.cpu.dtb.inst_misses 0 # ITB inst misses
306system.cpu.dtb.read_hits 0 # DTB read hits
307system.cpu.dtb.read_misses 0 # DTB read misses
308system.cpu.dtb.write_hits 0 # DTB write hits
309system.cpu.dtb.write_misses 0 # DTB write misses
310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
312system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
313system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
314system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
315system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
316system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dtb.read_accesses 0 # DTB read accesses
320system.cpu.dtb.write_accesses 0 # DTB write accesses
321system.cpu.dtb.inst_accesses 0 # ITB inst accesses
322system.cpu.dtb.hits 0 # DTB hits
323system.cpu.dtb.misses 0 # DTB misses
324system.cpu.dtb.accesses 0 # DTB accesses
| 300system.cpu.dtb.walker.walks 0 # Table walker walks requested
301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
308system.cpu.dtb.inst_hits 0 # ITB inst hits
309system.cpu.dtb.inst_misses 0 # ITB inst misses
310system.cpu.dtb.read_hits 0 # DTB read hits
311system.cpu.dtb.read_misses 0 # DTB read misses
312system.cpu.dtb.write_hits 0 # DTB write hits
313system.cpu.dtb.write_misses 0 # DTB write misses
314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
316system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
317system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
318system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
320system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
323system.cpu.dtb.read_accesses 0 # DTB read accesses
324system.cpu.dtb.write_accesses 0 # DTB write accesses
325system.cpu.dtb.inst_accesses 0 # ITB inst accesses
326system.cpu.dtb.hits 0 # DTB hits
327system.cpu.dtb.misses 0 # DTB misses
328system.cpu.dtb.accesses 0 # DTB accesses
|
| 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
341system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
342system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
343system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
344system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
345system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
| 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
338system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
339system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
340system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
341system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
342system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
343system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
344system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
346system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
347system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
348system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
349system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
350system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
| 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
354system.cpu.itb.walker.walks 0 # Table walker walks requested
355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.inst_hits 0 # ITB inst hits
363system.cpu.itb.inst_misses 0 # ITB inst misses
364system.cpu.itb.read_hits 0 # DTB read hits
365system.cpu.itb.read_misses 0 # DTB read misses
366system.cpu.itb.write_hits 0 # DTB write hits
367system.cpu.itb.write_misses 0 # DTB write misses
368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
370system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
371system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
372system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
373system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
374system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
375system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.itb.read_accesses 0 # DTB read accesses
378system.cpu.itb.write_accesses 0 # DTB write accesses
379system.cpu.itb.inst_accesses 0 # ITB inst accesses
380system.cpu.itb.hits 0 # DTB hits
381system.cpu.itb.misses 0 # DTB misses
382system.cpu.itb.accesses 0 # DTB accesses
383system.cpu.workload.num_syscalls 13 # Number of system calls
| 360system.cpu.itb.walker.walks 0 # Table walker walks requested
361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
368system.cpu.itb.inst_hits 0 # ITB inst hits
369system.cpu.itb.inst_misses 0 # ITB inst misses
370system.cpu.itb.read_hits 0 # DTB read hits
371system.cpu.itb.read_misses 0 # DTB read misses
372system.cpu.itb.write_hits 0 # DTB write hits
373system.cpu.itb.write_misses 0 # DTB write misses
374system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
375system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
376system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
377system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
378system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
379system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
380system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
381system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
383system.cpu.itb.read_accesses 0 # DTB read accesses
384system.cpu.itb.write_accesses 0 # DTB write accesses
385system.cpu.itb.inst_accesses 0 # ITB inst accesses
386system.cpu.itb.hits 0 # DTB hits
387system.cpu.itb.misses 0 # DTB misses
388system.cpu.itb.accesses 0 # DTB accesses
389system.cpu.workload.num_syscalls 13 # Number of system calls
|
| 390system.cpu.pwrStateResidencyTicks::ON 29977500 # Cumulative time (in ticks) in various power states
|
384system.cpu.numCycles 59955 # number of cpu cycles simulated
385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
387system.cpu.committedInsts 4605 # Number of instructions committed
388system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
389system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit
390system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
391system.cpu.cpi 13.019544 # CPI: cycles per instruction
392system.cpu.ipc 0.076808 # IPC: instructions per cycle
393system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
394system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
395system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
396system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction
397system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction
398system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction
399system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction
400system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction
401system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction
402system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction
403system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction
404system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction
405system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction
406system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction
407system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction
408system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction
409system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction
410system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction
411system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction
412system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction
413system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction
414system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction
415system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction
416system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction
417system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction
418system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction
419system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction
420system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction
421system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction
422system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction
423system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction
424system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction
425system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
426system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
427system.cpu.op_class_0::total 5391 # Class of committed instruction
428system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
429system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
| 391system.cpu.numCycles 59955 # number of cpu cycles simulated
392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
394system.cpu.committedInsts 4605 # Number of instructions committed
395system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
396system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit
397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
398system.cpu.cpi 13.019544 # CPI: cycles per instruction
399system.cpu.ipc 0.076808 # IPC: instructions per cycle
400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
401system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
402system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
403system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction
404system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction
405system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction
406system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction
407system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction
408system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction
409system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction
410system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction
411system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction
412system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction
413system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction
414system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction
415system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction
416system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction
417system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction
418system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction
419system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction
420system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction
421system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction
422system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction
423system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction
424system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction
425system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction
426system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction
427system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction
428system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction
429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction
430system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction
431system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction
432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
434system.cpu.op_class_0::total 5391 # Class of committed instruction
435system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
436system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
|
| 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
430system.cpu.dcache.tags.replacements 0 # number of replacements
431system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
432system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
433system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
434system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks.
435system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
436system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor
437system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy
438system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy
439system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
440system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
441system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
442system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
443system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
444system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
| 438system.cpu.dcache.tags.replacements 0 # number of replacements
439system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
440system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
441system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
442system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks.
443system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
444system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor
445system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy
446system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy
447system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
448system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
449system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
450system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
451system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
452system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
|
| 453system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
445system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
446system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
447system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
448system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
449system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
450system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
451system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
452system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
453system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits
454system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits
455system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits
456system.cpu.dcache.overall_hits::total 1894 # number of overall hits
457system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
458system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
459system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
460system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
461system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses
462system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
463system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
464system.cpu.dcache.overall_misses::total 182 # number of overall misses
465system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles
466system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles
467system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles
468system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles
469system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles
470system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles
471system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles
472system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles
473system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
474system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
475system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
476system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
477system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
478system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
479system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
480system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
481system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses
482system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses
483system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses
484system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses
485system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses
486system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses
487system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
488system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
489system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses
490system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses
491system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses
492system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses
493system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency
494system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency
495system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency
496system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency
497system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
498system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency
499system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
500system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency
501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
502system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
504system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
506system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
507system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits
508system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
509system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits
510system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits
511system.cpu.dcache.demand_mshr_hits::cpu.data 36 # number of demand (read+write) MSHR hits
512system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits
513system.cpu.dcache.overall_mshr_hits::cpu.data 36 # number of overall MSHR hits
514system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits
515system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
516system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
517system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
518system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
519system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
520system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
521system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
522system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
523system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles
524system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles
525system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles
526system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles
527system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles
528system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles
529system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles
530system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles
531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses
532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses
533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
535system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses
536system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses
537system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses
538system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses
539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency
540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency
541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency
542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency
543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
544system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
546system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
| 454system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
455system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
456system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
457system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
458system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
459system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
460system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
461system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
462system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits
463system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits
464system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits
465system.cpu.dcache.overall_hits::total 1894 # number of overall hits
466system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
467system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
468system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
469system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
470system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses
471system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
472system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
473system.cpu.dcache.overall_misses::total 182 # number of overall misses
474system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles
475system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles
476system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles
477system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles
478system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles
479system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles
480system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles
481system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles
482system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
483system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
484system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
485system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
486system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
487system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
488system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
489system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
490system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses
491system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses
492system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses
493system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses
494system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses
495system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses
496system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
497system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
498system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses
499system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses
500system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses
501system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses
502system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency
503system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency
504system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency
505system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency
506system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
507system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency
508system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
509system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency
510system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
511system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
512system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
513system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
514system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
515system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
516system.cpu.dcache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits
517system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
518system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits
519system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits
520system.cpu.dcache.demand_mshr_hits::cpu.data 36 # number of demand (read+write) MSHR hits
521system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits
522system.cpu.dcache.overall_mshr_hits::cpu.data 36 # number of overall MSHR hits
523system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits
524system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
525system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
526system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
527system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
528system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
529system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
530system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
531system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
532system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles
533system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles
534system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles
535system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles
536system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles
537system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles
538system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles
539system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles
540system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses
541system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses
542system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
543system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
544system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses
545system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses
546system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses
547system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses
548system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency
549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency
550system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency
551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency
552system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
553system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
554system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
555system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
|
| 556system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
547system.cpu.icache.tags.replacements 4 # number of replacements
548system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
549system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
550system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks.
551system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks.
552system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
553system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor
554system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy
555system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy
556system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
557system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
558system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
559system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
560system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses
561system.cpu.icache.tags.data_accesses 4821 # Number of data accesses
| 557system.cpu.icache.tags.replacements 4 # number of replacements
558system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
559system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
560system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks.
561system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks.
562system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
563system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor
564system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy
565system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy
566system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
567system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
568system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
569system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
570system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses
571system.cpu.icache.tags.data_accesses 4821 # Number of data accesses
|
| 572system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
562system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits
563system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits
564system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits
565system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits
566system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits
567system.cpu.icache.overall_hits::total 1926 # number of overall hits
568system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses
569system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses
570system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses
571system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses
572system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses
573system.cpu.icache.overall_misses::total 323 # number of overall misses
574system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles
575system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles
576system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles
577system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles
578system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles
579system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles
580system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses)
581system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses)
582system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses
583system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses
584system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses
585system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses
586system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses
587system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses
588system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses
589system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses
590system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses
591system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses
592system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency
593system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency
594system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
595system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency
596system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
597system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency
598system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
599system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
600system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
601system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
602system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
603system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
604system.cpu.icache.writebacks::writebacks 4 # number of writebacks
605system.cpu.icache.writebacks::total 4 # number of writebacks
606system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses
607system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses
608system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses
609system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses
610system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses
611system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses
612system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles
613system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles
614system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles
615system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles
616system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles
617system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles
618system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses
619system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses
620system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses
621system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses
622system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses
623system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses
624system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency
625system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency
626system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
627system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
628system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
629system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
| 573system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits
574system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits
575system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits
576system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits
577system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits
578system.cpu.icache.overall_hits::total 1926 # number of overall hits
579system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses
580system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses
581system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses
582system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses
583system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses
584system.cpu.icache.overall_misses::total 323 # number of overall misses
585system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles
586system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles
587system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles
588system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles
589system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles
590system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles
591system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses)
592system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses)
593system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses
594system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses
595system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses
596system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses
597system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses
598system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses
599system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses
600system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses
601system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses
602system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses
603system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency
604system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency
605system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
606system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency
607system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
608system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency
609system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
610system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
611system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
612system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
613system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
614system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
615system.cpu.icache.writebacks::writebacks 4 # number of writebacks
616system.cpu.icache.writebacks::total 4 # number of writebacks
617system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses
618system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses
619system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses
620system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses
621system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses
622system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses
623system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles
624system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles
625system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles
626system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles
627system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles
628system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles
629system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses
630system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses
631system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses
632system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses
633system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses
634system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses
635system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency
636system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency
637system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
638system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
639system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
640system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
|
| 641system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
630system.cpu.l2cache.tags.replacements 0 # number of replacements
631system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
632system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
633system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
634system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks.
635system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
636system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor
637system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor
638system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy
639system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy
640system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy
641system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
642system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
643system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
644system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
645system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses
646system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses
| 642system.cpu.l2cache.tags.replacements 0 # number of replacements
643system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
644system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
645system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
646system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks.
647system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
648system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor
649system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor
650system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy
651system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy
652system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy
653system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
654system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
655system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
656system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
657system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses
658system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses
|
| 659system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
647system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
648system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
649system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
650system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits
651system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
652system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits
653system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
654system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
655system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
656system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
657system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
658system.cpu.l2cache.overall_hits::total 40 # number of overall hits
659system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
660system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
661system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
662system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
663system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses
664system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses
665system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
666system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses
667system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
668system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
669system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
670system.cpu.l2cache.overall_misses::total 429 # number of overall misses
671system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles
672system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles
673system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles
674system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles
675system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles
676system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles
677system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles
678system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles
679system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles
680system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles
681system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles
682system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles
683system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
684system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
685system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
686system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
687system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses)
688system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses)
689system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
690system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
691system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses
692system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
693system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses
694system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses
695system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
696system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses
697system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
698system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
699system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses
700system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses
701system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses
702system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses
703system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses
704system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses
705system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses
706system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses
707system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
708system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses
709system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency
710system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency
711system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency
712system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency
713system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency
714system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency
715system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
716system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
717system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency
718system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
719system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
720system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency
721system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
722system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
723system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
724system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
725system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
726system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
727system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
728system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
729system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
730system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
731system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
732system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
733system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
734system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
735system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses
736system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses
737system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses
738system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses
739system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
740system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses
741system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
742system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
743system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
744system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
745system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles
746system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles
747system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles
748system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles
749system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles
750system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles
751system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles
752system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles
753system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles
754system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles
755system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles
756system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles
757system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
758system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
759system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses
760system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses
761system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
762system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
763system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses
764system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
765system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses
766system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses
767system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
768system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses
769system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency
770system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency
771system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency
772system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency
773system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency
774system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency
775system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
776system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
777system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
778system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
780system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
781system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
782system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
783system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
784system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
785system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
786system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
| 660system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
661system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
662system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
663system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits
664system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
665system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits
666system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
667system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
668system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
669system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
670system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
671system.cpu.l2cache.overall_hits::total 40 # number of overall hits
672system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
673system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
674system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
675system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
676system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses
677system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses
678system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
679system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses
680system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
681system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
682system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
683system.cpu.l2cache.overall_misses::total 429 # number of overall misses
684system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles
685system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles
686system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles
687system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles
688system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles
689system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles
690system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles
691system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles
692system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles
693system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles
694system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles
695system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles
696system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
697system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
698system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
699system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
700system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses)
701system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses)
702system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
703system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
704system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses
705system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
706system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses
707system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses
708system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
709system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses
710system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
711system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
712system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses
713system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses
714system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses
715system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses
716system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses
717system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses
718system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses
719system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses
720system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
721system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses
722system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency
723system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency
724system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency
725system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency
726system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency
727system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency
728system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
729system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
730system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency
731system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
732system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
733system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency
734system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
735system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
736system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
737system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
738system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
739system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
740system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
741system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
742system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
743system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
744system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
745system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
746system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
747system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
748system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses
749system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses
750system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses
751system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses
752system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
753system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses
754system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
755system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
756system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
757system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
758system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles
759system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles
760system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles
761system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles
762system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles
763system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles
764system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles
765system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles
766system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles
767system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles
768system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles
769system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles
770system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
771system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
772system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses
773system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses
774system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
775system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
776system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses
777system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
778system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses
779system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses
780system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
781system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses
782system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency
783system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency
784system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency
785system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency
786system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency
787system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency
788system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
789system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
790system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
791system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
792system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
793system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
794system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
795system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
796system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
797system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
798system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
799system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
| 800system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
787system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
788system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
789system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
790system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
791system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution
792system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
793system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes)
794system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
795system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
796system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes)
797system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
798system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes)
799system.cpu.toL2Bus.snoops 0 # Total snoops (count)
800system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram
801system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram
802system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram
803system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
804system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram
805system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram
806system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
807system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
808system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
809system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
810system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram
811system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks)
812system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
813system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks)
814system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
815system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
816system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
| 801system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
802system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
803system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
804system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
805system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution
806system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
807system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes)
808system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
809system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
810system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes)
811system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
812system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes)
813system.cpu.toL2Bus.snoops 0 # Total snoops (count)
814system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram
815system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram
816system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram
817system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
818system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram
819system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram
820system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
821system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
822system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
823system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
824system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram
825system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks)
826system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
827system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks)
828system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
829system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
830system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
| 831system.membus.pwrStateResidencyTicks::UNDEFINED 29977500 # Cumulative time (in ticks) in various power states
|
817system.membus.trans_dist::ReadResp 378 # Transaction distribution
818system.membus.trans_dist::ReadExReq 43 # Transaction distribution
819system.membus.trans_dist::ReadExResp 43 # Transaction distribution
820system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
821system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
822system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
823system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
824system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
825system.membus.snoops 0 # Total snoops (count)
826system.membus.snoop_fanout::samples 421 # Request fanout histogram
827system.membus.snoop_fanout::mean 0 # Request fanout histogram
828system.membus.snoop_fanout::stdev 0 # Request fanout histogram
829system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
830system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
831system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
832system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
833system.membus.snoop_fanout::min_value 0 # Request fanout histogram
834system.membus.snoop_fanout::max_value 0 # Request fanout histogram
835system.membus.snoop_fanout::total 421 # Request fanout histogram
836system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
837system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
838system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks)
839system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
840
841---------- End Simulation Statistics ----------
| 832system.membus.trans_dist::ReadResp 378 # Transaction distribution
833system.membus.trans_dist::ReadExReq 43 # Transaction distribution
834system.membus.trans_dist::ReadExResp 43 # Transaction distribution
835system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
836system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
837system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
838system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes)
839system.membus.pkt_size::total 26944 # Cumulative packet size per connected master and slave (bytes)
840system.membus.snoops 0 # Total snoops (count)
841system.membus.snoop_fanout::samples 421 # Request fanout histogram
842system.membus.snoop_fanout::mean 0 # Request fanout histogram
843system.membus.snoop_fanout::stdev 0 # Request fanout histogram
844system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
845system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
846system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
847system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
848system.membus.snoop_fanout::min_value 0 # Request fanout histogram
849system.membus.snoop_fanout::max_value 0 # Request fanout histogram
850system.membus.snoop_fanout::total 421 # Request fanout histogram
851system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
852system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
853system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks)
854system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
855
856---------- End Simulation Statistics ----------
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