1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000030 # Number of seconds simulated
4sim_ticks 29949500 # Number of ticks simulated
5final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 167534 # Simulator instruction rate (inst/s)
8host_op_rate 196036 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1088591965 # Simulator tick rate (ticks/s)
10host_mem_usage 269228 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
12sim_insts 4605 # Number of instructions simulated
13sim_ops 5391 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 421 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
--- 30 unchanged lines hidden (view full) ---
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 29858000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 421 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 80 unchanged lines hidden (view full) ---
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
203system.physmem.totQLat 2201000 # Total ticks spent queuing
204system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 7.03 # Data bus utilization in percentage
215system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 350 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 70921.62 # Average gap between requests
224system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
--- 4 unchanged lines hidden (view full) ---
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ)
247system.physmem_1.averagePower 784.282403 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states
249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 1912 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 347 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
--- 102 unchanged lines hidden (view full) ---
372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
373system.cpu.itb.read_accesses 0 # DTB read accesses
374system.cpu.itb.write_accesses 0 # DTB write accesses
375system.cpu.itb.inst_accesses 0 # ITB inst accesses
376system.cpu.itb.hits 0 # DTB hits
377system.cpu.itb.misses 0 # DTB misses
378system.cpu.itb.accesses 0 # DTB accesses
379system.cpu.workload.num_syscalls 13 # Number of system calls
380system.cpu.numCycles 59899 # number of cpu cycles simulated
381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
383system.cpu.committedInsts 4605 # Number of instructions committed
384system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
385system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
387system.cpu.cpi 13.007383 # CPI: cycles per instruction
388system.cpu.ipc 0.076879 # IPC: instructions per cycle
389system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
390system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
391system.cpu.dcache.tags.replacements 0 # number of replacements
392system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
393system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
395system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
397system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
398system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
399system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
401system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
402system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
404system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses
405system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses
406system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits
407system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits
408system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
409system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
410system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
411system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
412system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
413system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
414system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits
415system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits
416system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits
417system.cpu.dcache.overall_hits::total 1893 # number of overall hits
418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses
423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
425system.cpu.dcache.overall_misses::total 182 # number of overall misses
426system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
427system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
429system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
430system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
431system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
432system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
433system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
434system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
435system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
442system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses
443system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses
444system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses
445system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses
446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses
447system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
450system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses
451system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
452system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
453system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
455system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
457system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
458system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
459system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
460system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
461system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
468system.cpu.dcache.fast_writes 0 # number of fast writes performed
469system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 8 unchanged lines hidden (view full) ---
478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
491system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
493system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses
499system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
501system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
507system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
509system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
511system.cpu.icache.tags.replacements 3 # number of replacements
512system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
513system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
515system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
517system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
518system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
519system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
521system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
522system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
524system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
525system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
526system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
527system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
528system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
529system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
530system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
531system.cpu.icache.overall_hits::total 1920 # number of overall hits
532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
537system.cpu.icache.overall_misses::total 322 # number of overall misses
538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
539system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
540system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
541system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
542system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
543system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
544system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
545system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
546system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
547system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
548system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
549system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
551system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
552system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
553system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
554system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
555system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
557system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
558system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
559system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
560system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
561system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
568system.cpu.icache.fast_writes 0 # number of fast writes performed
569system.cpu.icache.cache_copies 0 # number of cache copies performed
570system.cpu.icache.writebacks::writebacks 3 # number of writebacks
571system.cpu.icache.writebacks::total 3 # number of writebacks
572system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
573system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
574system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
575system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
576system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
577system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
578system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
579system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
580system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
581system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
582system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
583system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
584system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
585system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
586system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
587system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
588system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
589system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
590system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
591system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
592system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
593system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
594system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
595system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
596system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
597system.cpu.l2cache.tags.replacements 0 # number of replacements
598system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
599system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
600system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
601system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
602system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
603system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
604system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
605system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
606system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
607system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
608system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
609system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
610system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
611system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
612system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
613system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
614system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
615system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
616system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
617system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
618system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
619system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits
620system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
621system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
622system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
623system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
624system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
625system.cpu.l2cache.overall_hits::total 39 # number of overall hits
626system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
627system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
628system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
629system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
630system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses
631system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses
632system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
633system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses
634system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
635system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
636system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
637system.cpu.l2cache.overall_misses::total 429 # number of overall misses
638system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
639system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
640system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
641system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
642system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
643system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
644system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
645system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
646system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
647system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
648system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
649system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
650system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
651system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
652system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
653system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
654system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
655system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
656system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
657system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
658system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
659system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
660system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
661system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
662system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
663system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
664system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
665system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
666system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
667system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
668system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses
669system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses
670system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
671system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses
672system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
673system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
674system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
675system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
676system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
677system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
678system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
679system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
680system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
681system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
682system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
683system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
684system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
685system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
686system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
687system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
688system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
689system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
690system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
691system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
692system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
693system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
694system.cpu.l2cache.fast_writes 0 # number of fast writes performed
695system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 10 unchanged lines hidden (view full) ---
706system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses
707system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses
708system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
709system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses
710system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
711system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
712system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
713system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
714system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
715system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
716system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
717system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
718system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
719system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
720system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
721system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
722system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
723system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
724system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
725system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
726system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
727system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
728system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
729system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
730system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
731system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
732system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
733system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
734system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
735system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
736system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
737system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
739system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
740system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
741system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
742system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
743system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
744system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
745system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
746system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
747system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
748system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
749system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
750system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
751system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
752system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
753system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
754system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
755system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
756system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
757system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
758system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
759system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
760system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
761system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
762system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
763system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
764system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
765system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
766system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
767system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
768system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
769system.cpu.toL2Bus.snoops 0 # Total snoops (count)
770system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
771system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
772system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
773system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
774system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
775system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
776system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
777system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
778system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
779system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
780system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
781system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
782system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
783system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
784system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
785system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
786system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
787system.membus.trans_dist::ReadResp 378 # Transaction distribution
788system.membus.trans_dist::ReadExReq 43 # Transaction distribution
789system.membus.trans_dist::ReadExResp 43 # Transaction distribution
790system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
791system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
--- 6 unchanged lines hidden (view full) ---
798system.membus.snoop_fanout::stdev 0 # Request fanout histogram
799system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
800system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
801system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
802system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
803system.membus.snoop_fanout::min_value 0 # Request fanout histogram
804system.membus.snoop_fanout::max_value 0 # Request fanout histogram
805system.membus.snoop_fanout::total 421 # Request fanout histogram
806system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
807system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
808system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
809system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
810
811---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000030 # Number of seconds simulated
4sim_ticks 29949500 # Number of ticks simulated
5final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 167534 # Simulator instruction rate (inst/s)
8host_op_rate 196036 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1088591965 # Simulator tick rate (ticks/s)
10host_mem_usage 269228 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
12sim_insts 4605 # Number of instructions simulated
13sim_ops 5391 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
18system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 421 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 26944 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 26944 # Total read bytes from the system interface side
--- 30 unchanged lines hidden (view full) ---
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 29858000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 421 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 80 unchanged lines hidden (view full) ---
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
203system.physmem.totQLat 2201000 # Total ticks spent queuing
204system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 7.03 # Data bus utilization in percentage
215system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 350 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 70921.62 # Average gap between requests
224system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
--- 4 unchanged lines hidden (view full) ---
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ)
247system.physmem_1.averagePower 784.282403 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states
249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 1912 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 347 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
264system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
265system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
266system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
267system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
--- 102 unchanged lines hidden (view full) ---
372system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
373system.cpu.itb.read_accesses 0 # DTB read accesses
374system.cpu.itb.write_accesses 0 # DTB write accesses
375system.cpu.itb.inst_accesses 0 # ITB inst accesses
376system.cpu.itb.hits 0 # DTB hits
377system.cpu.itb.misses 0 # DTB misses
378system.cpu.itb.accesses 0 # DTB accesses
379system.cpu.workload.num_syscalls 13 # Number of system calls
380system.cpu.numCycles 59899 # number of cpu cycles simulated
381system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
382system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
383system.cpu.committedInsts 4605 # Number of instructions committed
384system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
385system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
386system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
387system.cpu.cpi 13.007383 # CPI: cycles per instruction
388system.cpu.ipc 0.076879 # IPC: instructions per cycle
389system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
390system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
391system.cpu.dcache.tags.replacements 0 # number of replacements
392system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
393system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
394system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
395system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
396system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
397system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
398system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
399system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
400system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
401system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
402system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
403system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
404system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses
405system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses
406system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits
407system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits
408system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
409system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
410system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
411system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
412system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
413system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
414system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits
415system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits
416system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits
417system.cpu.dcache.overall_hits::total 1893 # number of overall hits
418system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
419system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
420system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
421system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
422system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses
423system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
424system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
425system.cpu.dcache.overall_misses::total 182 # number of overall misses
426system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
427system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
428system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
429system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
430system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
431system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
432system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
433system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
434system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
435system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
436system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
437system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
438system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
439system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
440system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
441system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
442system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses
443system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses
444system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses
445system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses
446system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses
447system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses
448system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
449system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
450system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses
451system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
452system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
453system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
454system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
455system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
456system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
457system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
458system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
459system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
460system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
461system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
468system.cpu.dcache.fast_writes 0 # number of fast writes performed
469system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 8 unchanged lines hidden (view full) ---
478system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses
479system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
480system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
481system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
482system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
483system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
484system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
485system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
486system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
487system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
488system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
489system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
490system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
491system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
492system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
493system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
494system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
495system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
496system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
497system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses
499system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
501system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
506system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
507system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
508system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
509system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
511system.cpu.icache.tags.replacements 3 # number of replacements
512system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
513system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
514system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
515system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
516system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
517system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
518system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
519system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
520system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
521system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
522system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
523system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
524system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
525system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
526system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
527system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
528system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
529system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
530system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
531system.cpu.icache.overall_hits::total 1920 # number of overall hits
532system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
533system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
534system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
535system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
536system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
537system.cpu.icache.overall_misses::total 322 # number of overall misses
538system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
539system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
540system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
541system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
542system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
543system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
544system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
545system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
546system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
547system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
548system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
549system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
551system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
552system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
553system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
554system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
555system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
557system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
558system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
559system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
560system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
561system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
568system.cpu.icache.fast_writes 0 # number of fast writes performed
569system.cpu.icache.cache_copies 0 # number of cache copies performed
570system.cpu.icache.writebacks::writebacks 3 # number of writebacks
571system.cpu.icache.writebacks::total 3 # number of writebacks
572system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
573system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
574system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
575system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
576system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
577system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
578system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
579system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
580system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
581system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
582system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
583system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
584system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
585system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
586system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
587system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
588system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
589system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
590system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
591system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
592system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
593system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
594system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
595system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
596system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
597system.cpu.l2cache.tags.replacements 0 # number of replacements
598system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
599system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
600system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
601system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
602system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
603system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
604system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
605system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
606system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
607system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
608system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
609system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
610system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
611system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
612system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
613system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
614system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
615system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
616system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
617system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
618system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
619system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits
620system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
621system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
622system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
623system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
624system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
625system.cpu.l2cache.overall_hits::total 39 # number of overall hits
626system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
627system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
628system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
629system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses
630system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses
631system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses
632system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses
633system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses
634system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses
635system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
636system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
637system.cpu.l2cache.overall_misses::total 429 # number of overall misses
638system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
639system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
640system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
641system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
642system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
643system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
644system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
645system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
646system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
647system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
648system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
649system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
650system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
651system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
652system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
653system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
654system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
655system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
656system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
657system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
658system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
659system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
660system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
661system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
662system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
663system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
664system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
665system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
666system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
667system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
668system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses
669system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses
670system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
671system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses
672system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
673system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
674system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
675system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
676system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
677system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
678system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
679system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
680system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
681system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
682system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
683system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
684system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
685system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
686system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
687system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
688system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
689system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
690system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
691system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
692system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
693system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
694system.cpu.l2cache.fast_writes 0 # number of fast writes performed
695system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 10 unchanged lines hidden (view full) ---
706system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses
707system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses
708system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses
709system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses
710system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses
711system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
712system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
713system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
714system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
715system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
716system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
717system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
718system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
719system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
720system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
721system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
722system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
723system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
724system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
725system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
726system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
727system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
728system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
729system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
730system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
731system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
732system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
733system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
734system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
735system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
736system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
737system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
739system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
740system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
741system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
742system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
743system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
744system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
745system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
746system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
747system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
748system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
749system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
750system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
751system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
752system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
753system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
754system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
755system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
756system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
757system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
758system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
759system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
760system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
761system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
762system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
763system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
764system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
765system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
766system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
767system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
768system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
769system.cpu.toL2Bus.snoops 0 # Total snoops (count)
770system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
771system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
772system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
773system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
774system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
775system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
776system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
777system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
778system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
779system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
780system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
781system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
782system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
783system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
784system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
785system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
786system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
787system.membus.trans_dist::ReadResp 378 # Transaction distribution
788system.membus.trans_dist::ReadExReq 43 # Transaction distribution
789system.membus.trans_dist::ReadExResp 43 # Transaction distribution
790system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution
791system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes)
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798system.membus.snoop_fanout::stdev 0 # Request fanout histogram
799system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
800system.membus.snoop_fanout::0 421 100.00% 100.00% # Request fanout histogram
801system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
802system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
803system.membus.snoop_fanout::min_value 0 # Request fanout histogram
804system.membus.snoop_fanout::max_value 0 # Request fanout histogram
805system.membus.snoop_fanout::total 421 # Request fanout histogram
806system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
807system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
808system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
809system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
810
811---------- End Simulation Statistics ----------