1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 27911000 # Number of ticks simulated
5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 3437 # Simulator instruction rate (inst/s)
8host_op_rate 4023 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20833659 # Simulator tick rate (ticks/s)
10host_mem_usage 251612 # Number of bytes of host memory used
11host_seconds 1.34 # Real time elapsed on the host
12sim_insts 4604 # Number of instructions simulated
13sim_ops 5390 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
17system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 420 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 91 # Per bank write bursts
41system.physmem.perBankRdBursts::1 51 # Per bank write bursts
42system.physmem.perBankRdBursts::2 20 # Per bank write bursts
43system.physmem.perBankRdBursts::3 42 # Per bank write bursts
44system.physmem.perBankRdBursts::4 23 # Per bank write bursts
45system.physmem.perBankRdBursts::5 41 # Per bank write bursts
46system.physmem.perBankRdBursts::6 36 # Per bank write bursts
47system.physmem.perBankRdBursts::7 12 # Per bank write bursts
48system.physmem.perBankRdBursts::8 5 # Per bank write bursts
49system.physmem.perBankRdBursts::9 6 # Per bank write bursts
50system.physmem.perBankRdBursts::10 27 # Per bank write bursts
51system.physmem.perBankRdBursts::11 42 # Per bank write bursts
52system.physmem.perBankRdBursts::12 9 # Per bank write bursts
--- 13 unchanged lines hidden (view full) ---
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 27825500 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 420 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 78 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
198system.physmem.totQLat 2575500 # Total ticks spent queuing
199system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
200system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
201system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
202system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
203system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
204system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
205system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
206system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
207system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
208system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
209system.physmem.busUtil 7.52 # Data bus utilization in percentage
210system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
211system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
212system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
213system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
214system.physmem.readRowHits 348 # Number of row buffer hits during reads
215system.physmem.writeRowHits 0 # Number of row buffer hits during writes
216system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
218system.physmem.avgGap 66251.19 # Average gap between requests
219system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined
220system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
221system.physmem.memoryStateTime::REF 780000 # Time in different power states
222system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
223system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
224system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
225system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ)
226system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ)
227system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ)
228system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ)
229system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ)
230system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ)
231system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
232system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
233system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ)
234system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ)
235system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ)
236system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ)
237system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ)
238system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ)
239system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ)
240system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ)
241system.physmem.averagePower::0 856.166817 # Core power per rank (mW)
242system.physmem.averagePower::1 786.636676 # Core power per rank (mW)
243system.membus.trans_dist::ReadReq 377 # Transaction distribution
244system.membus.trans_dist::ReadResp 377 # Transaction distribution
245system.membus.trans_dist::ReadExReq 43 # Transaction distribution
246system.membus.trans_dist::ReadExResp 43 # Transaction distribution
247system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
248system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
249system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
250system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
251system.membus.snoops 0 # Total snoops (count)
252system.membus.snoop_fanout::samples 420 # Request fanout histogram
253system.membus.snoop_fanout::mean 0 # Request fanout histogram
254system.membus.snoop_fanout::stdev 0 # Request fanout histogram
255system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
256system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
257system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
258system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
259system.membus.snoop_fanout::min_value 0 # Request fanout histogram
260system.membus.snoop_fanout::max_value 0 # Request fanout histogram
261system.membus.snoop_fanout::total 420 # Request fanout histogram
262system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
263system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
264system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
265system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
266system.cpu_clk_domain.clock 500 # Clock period in ticks
267system.cpu.branchPred.lookups 1903 # Number of BP lookups
268system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
269system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
270system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
271system.cpu.branchPred.BTBHits 325 # Number of BTB hits
272system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
273system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
274system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
275system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
276system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
277system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
278system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
279system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
280system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
281system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
353system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
354system.cpu.itb.read_accesses 0 # DTB read accesses
355system.cpu.itb.write_accesses 0 # DTB write accesses
356system.cpu.itb.inst_accesses 0 # ITB inst accesses
357system.cpu.itb.hits 0 # DTB hits
358system.cpu.itb.misses 0 # DTB misses
359system.cpu.itb.accesses 0 # DTB accesses
360system.cpu.workload.num_syscalls 13 # Number of system calls
361system.cpu.numCycles 55822 # number of cpu cycles simulated
362system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
363system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
364system.cpu.committedInsts 4604 # Number of instructions committed
365system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
366system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit
367system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
368system.cpu.cpi 12.124674 # CPI: cycles per instruction
369system.cpu.ipc 0.082476 # IPC: instructions per cycle
370system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
371system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
372system.cpu.icache.tags.replacements 3 # number of replacements
373system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
374system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks.
375system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
376system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks.
377system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
378system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
379system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
380system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
382system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
384system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
385system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses
386system.cpu.icache.tags.data_accesses 4799 # Number of data accesses
387system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits
388system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits
389system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits
390system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits
391system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits
392system.cpu.icache.overall_hits::total 1918 # number of overall hits
393system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
394system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
395system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
396system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
397system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
398system.cpu.icache.overall_misses::total 321 # number of overall misses
399system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
400system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
401system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
402system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
403system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
404system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
405system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses)
406system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses)
407system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses
408system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses
409system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses
410system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses
411system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses
412system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses
413system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses
414system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses
415system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses
416system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses
417system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
418system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
419system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
420system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
421system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
422system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
423system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
424system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
425system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
426system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
427system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
428system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
429system.cpu.icache.fast_writes 0 # number of fast writes performed
430system.cpu.icache.cache_copies 0 # number of cache copies performed
431system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
432system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
433system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
434system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
435system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
436system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
437system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
438system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
439system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
440system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
441system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
442system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
443system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses
444system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses
445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses
446system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses
447system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses
448system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses
449system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
450system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
451system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
452system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
453system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
454system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
455system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
456system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
457system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
458system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
460system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
461system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
462system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
463system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
466system.cpu.toL2Bus.snoops 0 # Total snoops (count)
467system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
468system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
469system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
470system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
482system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
483system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
484system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
485system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
486system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
487system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
488system.cpu.l2cache.tags.replacements 0 # number of replacements
489system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
490system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
491system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
492system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
493system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
494system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
495system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
496system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
497system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
498system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
499system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
500system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
501system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses
502system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses
503system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
504system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
505system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
506system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
507system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
508system.cpu.l2cache.overall_hits::total 39 # number of overall hits
509system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
510system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses
511system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
512system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
513system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses
514system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
515system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
516system.cpu.l2cache.overall_misses::total 428 # number of overall misses
517system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
518system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
519system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
520system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
521system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
522system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
523system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
524system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
525system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
526system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
527system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
528system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
529system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses
530system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
531system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses
532system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
533system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses
534system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses
535system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
536system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
537system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses
538system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
539system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
540system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
541system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
542system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
543system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
544system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
545system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
546system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
547system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
548system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
549system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
552system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
553system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555system.cpu.l2cache.fast_writes 0 # number of fast writes performed
556system.cpu.l2cache.cache_copies 0 # number of cache copies performed
557system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
558system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
559system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
560system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
561system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
562system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
563system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
564system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
565system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
566system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
567system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
568system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
569system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
570system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
571system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
572system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
573system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
574system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
575system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
581system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
582system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596system.cpu.dcache.tags.replacements 0 # number of replacements
597system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
598system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
599system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
600system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
601system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
602system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
603system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
604system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
605system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
606system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
607system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
608system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
609system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses
610system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses
611system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits
612system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits
613system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
614system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
615system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
616system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
617system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
618system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
619system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits
620system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits
621system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits
622system.cpu.dcache.overall_hits::total 1897 # number of overall hits
623system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
624system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
625system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
626system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
627system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses
628system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
629system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
630system.cpu.dcache.overall_misses::total 182 # number of overall misses
631system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
632system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
633system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
634system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
635system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
636system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
637system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
638system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
639system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
640system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
641system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
642system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
643system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
644system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
645system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
646system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
647system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses
648system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses
649system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses
650system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses
651system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses
652system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses
653system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
654system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
655system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses
656system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
657system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
658system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
659system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
660system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
661system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
662system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
663system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
664system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
665system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
666system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
667system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
668system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
669system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
670system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
671system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
672system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
673system.cpu.dcache.fast_writes 0 # number of fast writes performed
674system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 8 unchanged lines hidden (view full) ---
683system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses
684system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
685system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses
686system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
687system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses
688system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
689system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
690system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
692system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
694system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
695system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
696system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
697system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
698system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
699system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
700system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
701system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
702system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
703system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses
704system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
705system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
706system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
711system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
712system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
713system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
714system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
715system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
716
717---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 27911000 # Number of ticks simulated
5final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 3437 # Simulator instruction rate (inst/s)
8host_op_rate 4023 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20833659 # Simulator tick rate (ticks/s)
10host_mem_usage 251612 # Number of bytes of host memory used
11host_seconds 1.34 # Real time elapsed on the host
12sim_insts 4604 # Number of instructions simulated
13sim_ops 5390 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 26880 # Number of bytes read from this memory
17system.physmem.bytes_read::total 26880 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
20system.physmem.num_reads::cpu.inst 420 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 420 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 963061159 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::total 963061159 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_inst_read::cpu.inst 697072839 # Instruction read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::total 697072839 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_total::cpu.inst 963061159 # Total bandwidth to/from this memory (bytes/s)
27system.physmem.bw_total::total 963061159 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.readReqs 420 # Number of read requests accepted
29system.physmem.writeReqs 0 # Number of write requests accepted
30system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue
31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
32system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM
33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
35system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side
36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
40system.physmem.perBankRdBursts::0 91 # Per bank write bursts
41system.physmem.perBankRdBursts::1 51 # Per bank write bursts
42system.physmem.perBankRdBursts::2 20 # Per bank write bursts
43system.physmem.perBankRdBursts::3 42 # Per bank write bursts
44system.physmem.perBankRdBursts::4 23 # Per bank write bursts
45system.physmem.perBankRdBursts::5 41 # Per bank write bursts
46system.physmem.perBankRdBursts::6 36 # Per bank write bursts
47system.physmem.perBankRdBursts::7 12 # Per bank write bursts
48system.physmem.perBankRdBursts::8 5 # Per bank write bursts
49system.physmem.perBankRdBursts::9 6 # Per bank write bursts
50system.physmem.perBankRdBursts::10 27 # Per bank write bursts
51system.physmem.perBankRdBursts::11 42 # Per bank write bursts
52system.physmem.perBankRdBursts::12 9 # Per bank write bursts
--- 13 unchanged lines hidden (view full) ---
66system.physmem.perBankWrBursts::10 0 # Per bank write bursts
67system.physmem.perBankWrBursts::11 0 # Per bank write bursts
68system.physmem.perBankWrBursts::12 0 # Per bank write bursts
69system.physmem.perBankWrBursts::13 0 # Per bank write bursts
70system.physmem.perBankWrBursts::14 0 # Per bank write bursts
71system.physmem.perBankWrBursts::15 0 # Per bank write bursts
72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
74system.physmem.totGap 27825500 # Total gap between requests
75system.physmem.readPktSize::0 0 # Read request sizes (log2)
76system.physmem.readPktSize::1 0 # Read request sizes (log2)
77system.physmem.readPktSize::2 0 # Read request sizes (log2)
78system.physmem.readPktSize::3 0 # Read request sizes (log2)
79system.physmem.readPktSize::4 0 # Read request sizes (log2)
80system.physmem.readPktSize::5 0 # Read request sizes (log2)
81system.physmem.readPktSize::6 420 # Read request sizes (log2)
82system.physmem.writePktSize::0 0 # Write request sizes (log2)
83system.physmem.writePktSize::1 0 # Write request sizes (log2)
84system.physmem.writePktSize::2 0 # Write request sizes (log2)
85system.physmem.writePktSize::3 0 # Write request sizes (log2)
86system.physmem.writePktSize::4 0 # Write request sizes (log2)
87system.physmem.writePktSize::5 0 # Write request sizes (log2)
88system.physmem.writePktSize::6 0 # Write request sizes (log2)
89system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
90system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
91system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
--- 78 unchanged lines hidden (view full) ---
177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
185system.physmem.bytesPerActivate::samples 64 # Bytes accessed per row activation
186system.physmem.bytesPerActivate::mean 396 # Bytes accessed per row activation
187system.physmem.bytesPerActivate::gmean 274.035894 # Bytes accessed per row activation
188system.physmem.bytesPerActivate::stdev 327.902425 # Bytes accessed per row activation
189system.physmem.bytesPerActivate::0-127 10 15.62% 15.62% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::128-255 17 26.56% 42.19% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::256-383 12 18.75% 60.94% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::384-511 7 10.94% 71.88% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::512-639 3 4.69% 76.56% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation
198system.physmem.totQLat 2575500 # Total ticks spent queuing
199system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM
200system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers
201system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst
202system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
203system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst
204system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s
205system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
206system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s
207system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
208system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
209system.physmem.busUtil 7.52 # Data bus utilization in percentage
210system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
211system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
212system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
213system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
214system.physmem.readRowHits 348 # Number of row buffer hits during reads
215system.physmem.writeRowHits 0 # Number of row buffer hits during writes
216system.physmem.readRowHitRate 82.86 # Row buffer hit rate for reads
217system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
218system.physmem.avgGap 66251.19 # Average gap between requests
219system.physmem.pageHitRate 82.86 # Row buffer hit rate, read and write combined
220system.physmem.memoryStateTime::IDLE 12000 # Time in different power states
221system.physmem.memoryStateTime::REF 780000 # Time in different power states
222system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
223system.physmem.memoryStateTime::ACT 22840500 # Time in different power states
224system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
225system.physmem.actEnergy::0 302400 # Energy for activate commands per rank (pJ)
226system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ)
227system.physmem.preEnergy::0 165000 # Energy for precharge commands per rank (pJ)
228system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ)
229system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ)
230system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ)
231system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
232system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
233system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ)
234system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ)
235system.physmem.actBackEnergy::0 16015860 # Energy for active background per rank (pJ)
236system.physmem.actBackEnergy::1 16042365 # Energy for active background per rank (pJ)
237system.physmem.preBackEnergy::0 122250 # Energy for precharge background per rank (pJ)
238system.physmem.preBackEnergy::1 99000 # Energy for precharge background per rank (pJ)
239system.physmem.totalEnergy::0 20221590 # Total energy per rank (pJ)
240system.physmem.totalEnergy::1 18579375 # Total energy per rank (pJ)
241system.physmem.averagePower::0 856.166817 # Core power per rank (mW)
242system.physmem.averagePower::1 786.636676 # Core power per rank (mW)
243system.membus.trans_dist::ReadReq 377 # Transaction distribution
244system.membus.trans_dist::ReadResp 377 # Transaction distribution
245system.membus.trans_dist::ReadExReq 43 # Transaction distribution
246system.membus.trans_dist::ReadExResp 43 # Transaction distribution
247system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes)
248system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes)
249system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes)
250system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes)
251system.membus.snoops 0 # Total snoops (count)
252system.membus.snoop_fanout::samples 420 # Request fanout histogram
253system.membus.snoop_fanout::mean 0 # Request fanout histogram
254system.membus.snoop_fanout::stdev 0 # Request fanout histogram
255system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
256system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram
257system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
258system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
259system.membus.snoop_fanout::min_value 0 # Request fanout histogram
260system.membus.snoop_fanout::max_value 0 # Request fanout histogram
261system.membus.snoop_fanout::total 420 # Request fanout histogram
262system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks)
263system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
264system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks)
265system.membus.respLayer1.utilization 14.1 # Layer utilization (%)
266system.cpu_clk_domain.clock 500 # Clock period in ticks
267system.cpu.branchPred.lookups 1903 # Number of BP lookups
268system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted
269system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect
270system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups
271system.cpu.branchPred.BTBHits 325 # Number of BTB hits
272system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
273system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage
274system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
275system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
276system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
277system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
278system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
279system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
280system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
281system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 69 unchanged lines hidden (view full) ---
353system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
354system.cpu.itb.read_accesses 0 # DTB read accesses
355system.cpu.itb.write_accesses 0 # DTB write accesses
356system.cpu.itb.inst_accesses 0 # ITB inst accesses
357system.cpu.itb.hits 0 # DTB hits
358system.cpu.itb.misses 0 # DTB misses
359system.cpu.itb.accesses 0 # DTB accesses
360system.cpu.workload.num_syscalls 13 # Number of system calls
361system.cpu.numCycles 55822 # number of cpu cycles simulated
362system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
363system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
364system.cpu.committedInsts 4604 # Number of instructions committed
365system.cpu.committedOps 5390 # Number of ops (including micro ops) committed
366system.cpu.discardedOps 1208 # Number of ops (including micro ops) which were discarded before commit
367system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
368system.cpu.cpi 12.124674 # CPI: cycles per instruction
369system.cpu.ipc 0.082476 # IPC: instructions per cycle
370system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked
371system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped
372system.cpu.icache.tags.replacements 3 # number of replacements
373system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use
374system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks.
375system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks.
376system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks.
377system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
378system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor
379system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy
380system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy
381system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
382system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
383system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
384system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
385system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses
386system.cpu.icache.tags.data_accesses 4799 # Number of data accesses
387system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits
388system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits
389system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits
390system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits
391system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits
392system.cpu.icache.overall_hits::total 1918 # number of overall hits
393system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses
394system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses
395system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses
396system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses
397system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses
398system.cpu.icache.overall_misses::total 321 # number of overall misses
399system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles
400system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles
401system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles
402system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles
403system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles
404system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles
405system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses)
406system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses)
407system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses
408system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses
409system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses
410system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses
411system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses
412system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses
413system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses
414system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses
415system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses
416system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses
417system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency
418system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency
419system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
420system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency
421system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency
422system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency
423system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
424system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
425system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
426system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
427system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
428system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
429system.cpu.icache.fast_writes 0 # number of fast writes performed
430system.cpu.icache.cache_copies 0 # number of cache copies performed
431system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses
432system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses
433system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses
434system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses
435system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses
436system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses
437system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles
438system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles
439system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles
440system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles
441system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles
442system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles
443system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses
444system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses
445system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses
446system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses
447system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses
448system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses
449system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency
450system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency
451system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
452system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
453system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency
454system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency
455system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
456system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
457system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
458system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
460system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes)
461system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
462system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes)
463system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes)
466system.cpu.toL2Bus.snoops 0 # Total snoops (count)
467system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram
468system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
469system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
470system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram
482system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks)
483system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
484system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks)
485system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
486system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks)
487system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
488system.cpu.l2cache.tags.replacements 0 # number of replacements
489system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use
490system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
491system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks.
492system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks.
493system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
494system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor
495system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy
496system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy
497system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id
498system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
499system.cpu.l2cache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
500system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011505 # Percentage of cache occupancy per task id
501system.cpu.l2cache.tags.tag_accesses 4156 # Number of tag accesses
502system.cpu.l2cache.tags.data_accesses 4156 # Number of data accesses
503system.cpu.l2cache.ReadReq_hits::cpu.inst 39 # number of ReadReq hits
504system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits
505system.cpu.l2cache.demand_hits::cpu.inst 39 # number of demand (read+write) hits
506system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
507system.cpu.l2cache.overall_hits::cpu.inst 39 # number of overall hits
508system.cpu.l2cache.overall_hits::total 39 # number of overall hits
509system.cpu.l2cache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses
510system.cpu.l2cache.ReadReq_misses::total 385 # number of ReadReq misses
511system.cpu.l2cache.ReadExReq_misses::cpu.inst 43 # number of ReadExReq misses
512system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
513system.cpu.l2cache.demand_misses::cpu.inst 428 # number of demand (read+write) misses
514system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses
515system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses
516system.cpu.l2cache.overall_misses::total 428 # number of overall misses
517system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles
518system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles
519system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles
520system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles
521system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles
522system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles
523system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles
524system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles
525system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses)
526system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
527system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses)
528system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
529system.cpu.l2cache.demand_accesses::cpu.inst 467 # number of demand (read+write) accesses
530system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses
531system.cpu.l2cache.overall_accesses::cpu.inst 467 # number of overall (read+write) accesses
532system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses
533system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.908019 # miss rate for ReadReq accesses
534system.cpu.l2cache.ReadReq_miss_rate::total 0.908019 # miss rate for ReadReq accesses
535system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 1 # miss rate for ReadExReq accesses
536system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
537system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 # miss rate for demand accesses
538system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses
539system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses
540system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses
541system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency
542system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency
543system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency
544system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency
545system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
546system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency
547system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency
548system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency
549system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
552system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
553system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555system.cpu.l2cache.fast_writes 0 # number of fast writes performed
556system.cpu.l2cache.cache_copies 0 # number of cache copies performed
557system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
558system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
559system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
560system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
561system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
562system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
563system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 377 # number of ReadReq MSHR misses
564system.cpu.l2cache.ReadReq_mshr_misses::total 377 # number of ReadReq MSHR misses
565system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 43 # number of ReadExReq MSHR misses
566system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
567system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 # number of demand (read+write) MSHR misses
568system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses
569system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses
570system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses
571system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles
572system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles
573system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles
574system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles
575system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles
576system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles
577system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles
578system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles
579system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses
580system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses
581system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
582system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
583system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for demand accesses
584system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses
585system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses
586system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses
587system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency
588system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency
589system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency
590system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency
595system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
596system.cpu.dcache.tags.replacements 0 # number of replacements
597system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use
598system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks.
599system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
600system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks.
601system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
602system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor
603system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
604system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
605system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
606system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
607system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
608system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
609system.cpu.dcache.tags.tag_accesses 4348 # Number of tag accesses
610system.cpu.dcache.tags.data_accesses 4348 # Number of data accesses
611system.cpu.dcache.ReadReq_hits::cpu.inst 1051 # number of ReadReq hits
612system.cpu.dcache.ReadReq_hits::total 1051 # number of ReadReq hits
613system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
614system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
615system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
616system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
617system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
618system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
619system.cpu.dcache.demand_hits::cpu.inst 1897 # number of demand (read+write) hits
620system.cpu.dcache.demand_hits::total 1897 # number of demand (read+write) hits
621system.cpu.dcache.overall_hits::cpu.inst 1897 # number of overall hits
622system.cpu.dcache.overall_hits::total 1897 # number of overall hits
623system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
624system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
625system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
626system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
627system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses
628system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
629system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
630system.cpu.dcache.overall_misses::total 182 # number of overall misses
631system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles
632system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles
633system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles
634system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles
635system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles
636system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles
637system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles
638system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles
639system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses)
640system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses)
641system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses)
642system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
643system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
644system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
645system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
646system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
647system.cpu.dcache.demand_accesses::cpu.inst 2079 # number of demand (read+write) accesses
648system.cpu.dcache.demand_accesses::total 2079 # number of demand (read+write) accesses
649system.cpu.dcache.overall_accesses::cpu.inst 2079 # number of overall (read+write) accesses
650system.cpu.dcache.overall_accesses::total 2079 # number of overall (read+write) accesses
651system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098628 # miss rate for ReadReq accesses
652system.cpu.dcache.ReadReq_miss_rate::total 0.098628 # miss rate for ReadReq accesses
653system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.073384 # miss rate for WriteReq accesses
654system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
655system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 # miss rate for demand accesses
656system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses
657system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses
658system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses
659system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency
660system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency
661system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency
662system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency
663system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
664system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency
665system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency
666system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency
667system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
668system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
669system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
670system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
671system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
672system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
673system.cpu.dcache.fast_writes 0 # number of fast writes performed
674system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 8 unchanged lines hidden (view full) ---
683system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 103 # number of ReadReq MSHR misses
684system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
685system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 43 # number of WriteReq MSHR misses
686system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
687system.cpu.dcache.demand_mshr_misses::cpu.inst 146 # number of demand (read+write) MSHR misses
688system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
689system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses
690system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles
692system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles
693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles
694system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles
695system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles
696system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles
697system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles
698system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles
699system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses
700system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses
701system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses
702system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
703system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for demand accesses
704system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses
705system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses
706system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses
707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency
708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency
709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency
710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency
711system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
712system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
713system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency
714system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency
715system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
716
717---------- End Simulation Statistics ----------