| stats.txt (9055:38f1926fb599) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33007000 # Number of ticks simulated 5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000034 # Number of seconds simulated 4sim_ticks 34425000 # Number of ticks simulated 5final_tick 34425000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 524144 # Simulator instruction rate (inst/s) 8host_op_rate 523337 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2693393609 # Simulator tick rate (ticks/s) 10host_mem_usage 214140 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host | 7host_inst_rate 6722 # Simulator instruction rate (inst/s) 8host_op_rate 6722 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36133024 # Simulator tick rate (ticks/s) 10host_mem_usage 217168 # Number of bytes of host memory used 11host_seconds 0.95 # Real time elapsed on the host |
| 12sim_insts 6404 # Number of instructions simulated 13sim_ops 6404 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory | 12sim_insts 6404 # Number of instructions simulated 13sim_ops 6404 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 516833696 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 312331155 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 829164851 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 516833696 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 516833696 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 516833696 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 312331155 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 829164851 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.fetch_hits 0 # ITB hits 31system.cpu.dtb.fetch_misses 0 # ITB misses 32system.cpu.dtb.fetch_acv 0 # ITB acv 33system.cpu.dtb.fetch_accesses 0 # ITB accesses 34system.cpu.dtb.read_hits 1185 # DTB read hits 35system.cpu.dtb.read_misses 7 # DTB read misses 36system.cpu.dtb.read_acv 0 # DTB read access violations 37system.cpu.dtb.read_accesses 1192 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 55system.cpu.itb.write_misses 0 # DTB write misses 56system.cpu.itb.write_acv 0 # DTB write access violations 57system.cpu.itb.write_accesses 0 # DTB write accesses 58system.cpu.itb.data_hits 0 # DTB hits 59system.cpu.itb.data_misses 0 # DTB misses 60system.cpu.itb.data_acv 0 # DTB access violations 61system.cpu.itb.data_accesses 0 # DTB accesses 62system.cpu.workload.num_syscalls 17 # Number of system calls | 30system.cpu.dtb.fetch_hits 0 # ITB hits 31system.cpu.dtb.fetch_misses 0 # ITB misses 32system.cpu.dtb.fetch_acv 0 # ITB acv 33system.cpu.dtb.fetch_accesses 0 # ITB accesses 34system.cpu.dtb.read_hits 1185 # DTB read hits 35system.cpu.dtb.read_misses 7 # DTB read misses 36system.cpu.dtb.read_acv 0 # DTB read access violations 37system.cpu.dtb.read_accesses 1192 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 55system.cpu.itb.write_misses 0 # DTB write misses 56system.cpu.itb.write_acv 0 # DTB write access violations 57system.cpu.itb.write_accesses 0 # DTB write accesses 58system.cpu.itb.data_hits 0 # DTB hits 59system.cpu.itb.data_misses 0 # DTB misses 60system.cpu.itb.data_acv 0 # DTB access violations 61system.cpu.itb.data_accesses 0 # DTB accesses 62system.cpu.workload.num_syscalls 17 # Number of system calls |
| 63system.cpu.numCycles 66014 # number of cpu cycles simulated | 63system.cpu.numCycles 68850 # number of cpu cycles simulated |
| 64system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 65system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 66system.cpu.committedInsts 6404 # Number of instructions committed 67system.cpu.committedOps 6404 # Number of ops (including micro ops) committed 68system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses 69system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 70system.cpu.num_func_calls 251 # number of times a function call or return occured 71system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls 72system.cpu.num_int_insts 6331 # number of integer instructions 73system.cpu.num_fp_insts 10 # number of float instructions 74system.cpu.num_int_register_reads 8304 # number of times the integer registers were read 75system.cpu.num_int_register_writes 4581 # number of times the integer registers were written 76system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 77system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 78system.cpu.num_mem_refs 2060 # number of memory refs 79system.cpu.num_load_insts 1192 # Number of load instructions 80system.cpu.num_store_insts 868 # Number of store instructions 81system.cpu.num_idle_cycles 0 # Number of idle cycles | 64system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 65system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 66system.cpu.committedInsts 6404 # Number of instructions committed 67system.cpu.committedOps 6404 # Number of ops (including micro ops) committed 68system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses 69system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 70system.cpu.num_func_calls 251 # number of times a function call or return occured 71system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls 72system.cpu.num_int_insts 6331 # number of integer instructions 73system.cpu.num_fp_insts 10 # number of float instructions 74system.cpu.num_int_register_reads 8304 # number of times the integer registers were read 75system.cpu.num_int_register_writes 4581 # number of times the integer registers were written 76system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 77system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 78system.cpu.num_mem_refs 2060 # number of memory refs 79system.cpu.num_load_insts 1192 # Number of load instructions 80system.cpu.num_store_insts 868 # Number of store instructions 81system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 82system.cpu.num_busy_cycles 66014 # Number of busy cycles | 82system.cpu.num_busy_cycles 68850 # Number of busy cycles |
| 83system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 84system.cpu.idle_fraction 0 # Percentage of idle cycles 85system.cpu.icache.replacements 0 # number of replacements | 83system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 84system.cpu.idle_fraction 0 # Percentage of idle cycles 85system.cpu.icache.replacements 0 # number of replacements |
| 86system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use | 86system.cpu.icache.tagsinuse 128.155444 # Cycle average of tags in use |
| 87system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. 88system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 89system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. 90system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 87system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. 88system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. 89system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. 90system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 91system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor 92system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy 93system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy | 91system.cpu.icache.occ_blocks::cpu.inst 128.155444 # Average occupied blocks per requestor 92system.cpu.icache.occ_percent::cpu.inst 0.062576 # Average percentage of cache occupancy 93system.cpu.icache.occ_percent::total 0.062576 # Average percentage of cache occupancy |
| 94system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits 95system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits 96system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits 97system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits 98system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits 99system.cpu.icache.overall_hits::total 6136 # number of overall hits 100system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 101system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 156system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 157system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 158system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 159system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 160system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 161system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 162system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 163system.cpu.dcache.replacements 0 # number of replacements | 94system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits 95system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits 96system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits 97system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits 98system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits 99system.cpu.icache.overall_hits::total 6136 # number of overall hits 100system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 101system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 156system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency 157system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency 158system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 159system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 160system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency 161system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency 162system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 163system.cpu.dcache.replacements 0 # number of replacements |
| 164system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use | 164system.cpu.dcache.tagsinuse 103.856385 # Cycle average of tags in use |
| 165system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. 166system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 167system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. 168system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 165system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. 166system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 167system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. 168system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 169system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor 170system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy 171system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy | 169system.cpu.dcache.occ_blocks::cpu.data 103.856385 # Average occupied blocks per requestor 170system.cpu.dcache.occ_percent::cpu.data 0.025356 # Average percentage of cache occupancy 171system.cpu.dcache.occ_percent::total 0.025356 # Average percentage of cache occupancy |
| 172system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 173system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 174system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 175system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 176system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 177system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 178system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 179system.cpu.dcache.overall_hits::total 1882 # number of overall hits --- 74 unchanged lines hidden (view full) --- 254system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 255system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 256system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 257system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 258system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 259system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 260system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 261system.cpu.l2cache.replacements 0 # number of replacements | 172system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 173system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 174system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 175system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 176system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 177system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 178system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 179system.cpu.dcache.overall_hits::total 1882 # number of overall hits --- 74 unchanged lines hidden (view full) --- 254system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 255system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 256system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 257system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 258system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 259system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 260system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 261system.cpu.l2cache.replacements 0 # number of replacements |
| 262system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use | 262system.cpu.l2cache.tagsinuse 184.699061 # Cycle average of tags in use |
| 263system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 264system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 265system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 266system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 263system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 264system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 265system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 266system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 267system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor 268system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor 269system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy 270system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy 271system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy | 267system.cpu.l2cache.occ_blocks::cpu.inst 128.168283 # Average occupied blocks per requestor 268system.cpu.l2cache.occ_blocks::cpu.data 56.530778 # Average occupied blocks per requestor 269system.cpu.l2cache.occ_percent::cpu.inst 0.003911 # Average percentage of cache occupancy 270system.cpu.l2cache.occ_percent::cpu.data 0.001725 # Average percentage of cache occupancy 271system.cpu.l2cache.occ_percent::total 0.005637 # Average percentage of cache occupancy |
| 272system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 273system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 274system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 275system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 276system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 277system.cpu.l2cache.overall_hits::total 1 # number of overall hits 278system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 279system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses --- 108 unchanged lines hidden --- | 272system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 273system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 274system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 275system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 276system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 277system.cpu.l2cache.overall_hits::total 1 # number of overall hits 278system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses 279system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses --- 108 unchanged lines hidden --- |