| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33007000 # Number of ticks simulated 5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33007000 # Number of ticks simulated 5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 37663 # Simulator instruction rate (inst/s) 8host_op_rate 37658 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 194071847 # Simulator tick rate (ticks/s) 10host_mem_usage 209060 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host | 7host_inst_rate 236370 # Simulator instruction rate (inst/s) 8host_op_rate 236114 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1215776788 # Simulator tick rate (ticks/s) 10host_mem_usage 213800 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 6404 # Number of instructions simulated 13sim_ops 6404 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28544 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 446 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 93 unchanged lines hidden (view full) --- 113system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses 114system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency 115system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency 116system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency 117system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 120system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 6404 # Number of instructions simulated 13sim_ops 6404 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28544 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 446 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 93 unchanged lines hidden (view full) --- 113system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses 114system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency 115system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency 116system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency 117system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 120system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 121system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 122system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 121system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 122system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 123system.cpu.icache.fast_writes 0 # number of fast writes performed 124system.cpu.icache.cache_copies 0 # number of cache copies performed 125system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 126system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 127system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 128system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 129system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 130system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses --- 58 unchanged lines hidden (view full) --- 189system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 190system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 191system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 192system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 193system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 194system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 195system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 196system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 123system.cpu.icache.fast_writes 0 # number of fast writes performed 124system.cpu.icache.cache_copies 0 # number of cache copies performed 125system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 126system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 127system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 128system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 129system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 130system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses --- 58 unchanged lines hidden (view full) --- 189system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 190system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 191system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 192system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 193system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 194system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 195system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 196system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 197system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 198system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 197system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 198system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 199system.cpu.dcache.fast_writes 0 # number of fast writes performed 200system.cpu.dcache.cache_copies 0 # number of cache copies performed 201system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 202system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 203system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 204system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 205system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 206system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses --- 79 unchanged lines hidden (view full) --- 286system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 287system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 288system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 289system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 290system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 291system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 292system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 293system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 199system.cpu.dcache.fast_writes 0 # number of fast writes performed 200system.cpu.dcache.cache_copies 0 # number of cache copies performed 201system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 202system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 203system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 204system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 205system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 206system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses --- 79 unchanged lines hidden (view full) --- 286system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 287system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 288system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 289system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 290system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 291system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 292system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 293system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 294system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 295system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 294system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 295system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 296system.cpu.l2cache.fast_writes 0 # number of fast writes performed 297system.cpu.l2cache.cache_copies 0 # number of cache copies performed 298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 300system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 302system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 303system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 296system.cpu.l2cache.fast_writes 0 # number of fast writes performed 297system.cpu.l2cache.cache_copies 0 # number of cache copies performed 298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses 299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 300system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses 301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 302system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 303system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |