| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000036 # Number of seconds simulated 4sim_ticks 35682500 # Number of ticks simulated 5final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000036 # Number of seconds simulated 4sim_ticks 35682500 # Number of ticks simulated 5final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 581025 # Simulator instruction rate (inst/s) 8host_op_rate 580437 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3231677275 # Simulator tick rate (ticks/s) 10host_mem_usage 247496 # Number of bytes of host memory used | 7host_inst_rate 516760 # Simulator instruction rate (inst/s) 8host_op_rate 516348 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2875227341 # Simulator tick rate (ticks/s) 10host_mem_usage 291440 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6403 # Number of instructions simulated 13sim_ops 6403 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6403 # Number of instructions simulated 13sim_ops 6403 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dtb.fetch_hits 0 # ITB hits 34system.cpu.dtb.fetch_misses 0 # ITB misses 35system.cpu.dtb.fetch_acv 0 # ITB acv 36system.cpu.dtb.fetch_accesses 0 # ITB accesses 37system.cpu.dtb.read_hits 1185 # DTB read hits 38system.cpu.dtb.read_misses 7 # DTB read misses 39system.cpu.dtb.read_acv 0 # DTB read access violations --- 18 unchanged lines hidden (view full) --- 58system.cpu.itb.write_misses 0 # DTB write misses 59system.cpu.itb.write_acv 0 # DTB write access violations 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.data_hits 0 # DTB hits 62system.cpu.itb.data_misses 0 # DTB misses 63system.cpu.itb.data_acv 0 # DTB access violations 64system.cpu.itb.data_accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 17 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.fetch_hits 0 # ITB hits 36system.cpu.dtb.fetch_misses 0 # ITB misses 37system.cpu.dtb.fetch_acv 0 # ITB acv 38system.cpu.dtb.fetch_accesses 0 # ITB accesses 39system.cpu.dtb.read_hits 1185 # DTB read hits 40system.cpu.dtb.read_misses 7 # DTB read misses 41system.cpu.dtb.read_acv 0 # DTB read access violations --- 18 unchanged lines hidden (view full) --- 60system.cpu.itb.write_misses 0 # DTB write misses 61system.cpu.itb.write_acv 0 # DTB write access violations 62system.cpu.itb.write_accesses 0 # DTB write accesses 63system.cpu.itb.data_hits 0 # DTB hits 64system.cpu.itb.data_misses 0 # DTB misses 65system.cpu.itb.data_acv 0 # DTB access violations 66system.cpu.itb.data_accesses 0 # DTB accesses 67system.cpu.workload.num_syscalls 17 # Number of system calls |
| 68system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states |
|
| 66system.cpu.numCycles 71365 # number of cpu cycles simulated 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.committedInsts 6403 # Number of instructions committed 70system.cpu.committedOps 6403 # Number of ops (including micro ops) committed 71system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses 72system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 73system.cpu.num_func_calls 251 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 116system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction 117system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction 118system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction 119system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction 120system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction 121system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 122system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 123system.cpu.op_class::total 6413 # Class of executed instruction | 69system.cpu.numCycles 71365 # number of cpu cycles simulated 70system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 71system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 72system.cpu.committedInsts 6403 # Number of instructions committed 73system.cpu.committedOps 6403 # Number of ops (including micro ops) committed 74system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses 75system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 76system.cpu.num_func_calls 251 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 119system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction 120system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction 121system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction 122system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction 123system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction 124system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 125system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 126system.cpu.op_class::total 6413 # Class of executed instruction |
| 127system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 124system.cpu.dcache.tags.replacements 0 # number of replacements 125system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use 126system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. 127system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 128system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. 129system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 130system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor 131system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 132system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy 133system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id 136system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 137system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses 138system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses | 128system.cpu.dcache.tags.replacements 0 # number of replacements 129system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use 130system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. 131system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 132system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. 133system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 134system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor 135system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy 136system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy 137system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 138system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id 139system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id 140system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 141system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses 142system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses |
| 143system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 139system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 140system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 141system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 142system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 143system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 144system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 145system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 146system.cpu.dcache.overall_hits::total 1882 # number of overall hits --- 70 unchanged lines hidden (view full) --- 217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 144system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits 145system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits 146system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 147system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 148system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 149system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 150system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 151system.cpu.dcache.overall_hits::total 1882 # number of overall hits --- 70 unchanged lines hidden (view full) --- 222system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 223system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 224system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 225system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 226system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 227system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 228system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 229system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 230system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 225system.cpu.icache.tags.replacements 0 # number of replacements 226system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use 227system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. 228system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 229system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. 230system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 231system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor 232system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy 233system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy 234system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 235system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 236system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 237system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 238system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses 239system.cpu.icache.tags.data_accesses 13107 # Number of data accesses | 231system.cpu.icache.tags.replacements 0 # number of replacements 232system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use 233system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. 234system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 235system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. 236system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 237system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor 238system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy 239system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy 240system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 241system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 242system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 243system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 244system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses 245system.cpu.icache.tags.data_accesses 13107 # Number of data accesses |
| 246system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 240system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits 241system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits 242system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits 243system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits 244system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits 245system.cpu.icache.overall_hits::total 6135 # number of overall hits 246system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 247system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 298system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses 299system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency 301system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 303system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 305system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency | 247system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits 248system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits 249system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits 250system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits 251system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits 252system.cpu.icache.overall_hits::total 6135 # number of overall hits 253system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 254system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses --- 50 unchanged lines hidden (view full) --- 305system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses 306system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses 307system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency 308system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency 309system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 310system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 311system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 312system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency |
| 313system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 306system.cpu.l2cache.tags.replacements 0 # number of replacements 307system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use 308system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 312system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor 314system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy 315system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy 316system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy 317system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 318system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 319system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 320system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 321system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 322system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses | 314system.cpu.l2cache.tags.replacements 0 # number of replacements 315system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use 316system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 317system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 318system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 319system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 320system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor 321system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy 323system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy 324system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 326system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 327system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 328system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 329system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 330system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses |
| 331system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
|
| 323system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 324system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 325system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 326system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 327system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 328system.cpu.l2cache.overall_hits::total 1 # number of overall hits 329system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 330system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 443system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 444system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 445system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 446system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 447system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 448system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 332system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 333system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 334system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 335system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 336system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 337system.cpu.l2cache.overall_hits::total 1 # number of overall hits 338system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 339system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 450system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 451system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 452system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 458system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
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| 449system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 451system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution 454system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 455system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 456system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 470system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 472system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 473system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 474system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 475system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 476system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 477system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 459system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution 464system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 465system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 480system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 482system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 483system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 484system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 485system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) 486system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 487system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 488system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states |
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| 478system.membus.trans_dist::ReadResp 373 # Transaction distribution 479system.membus.trans_dist::ReadExReq 73 # Transaction distribution 480system.membus.trans_dist::ReadExResp 73 # Transaction distribution 481system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 482system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 483system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 484system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 485system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 489system.membus.trans_dist::ReadResp 373 # Transaction distribution 490system.membus.trans_dist::ReadExReq 73 # Transaction distribution 491system.membus.trans_dist::ReadExResp 73 # Transaction distribution 492system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 493system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 494system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 495system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 496system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |