| stats.txt (11390:f40859930028) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000036 # Number of seconds simulated 4sim_ticks 35682500 # Number of ticks simulated 5final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000036 # Number of seconds simulated 4sim_ticks 35682500 # Number of ticks simulated 5final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 44587 # Simulator instruction rate (inst/s) 8host_op_rate 44581 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 248411942 # Simulator tick rate (ticks/s) 10host_mem_usage 226904 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host | 7host_inst_rate 421865 # Simulator instruction rate (inst/s) 8host_op_rate 421312 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2345119890 # Simulator tick rate (ticks/s) 10host_mem_usage 251096 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 6403 # Number of instructions simulated 13sim_ops 6403 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 165 unchanged lines hidden (view full) --- 185system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 186system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 187system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 188system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 189system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 190system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 191system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 192system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 6403 # Number of instructions simulated 13sim_ops 6403 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 165 unchanged lines hidden (view full) --- 185system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 186system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency 187system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 188system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 189system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 190system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 191system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 192system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 193system.cpu.dcache.fast_writes 0 # number of fast writes performed 194system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 195system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 196system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 197system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 198system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 199system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 200system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 201system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 202system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 219system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 220system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 221system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 225system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 193system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 194system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 195system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 196system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 197system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 198system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 199system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 200system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 222system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 224system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 227system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 228system.cpu.icache.tags.replacements 0 # number of replacements 229system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use 230system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. 231system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 232system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. 233system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 234system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor 235system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 277system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency 279system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 225system.cpu.icache.tags.replacements 0 # number of replacements 226system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use 227system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. 228system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 229system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. 230system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 231system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor 232system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 274system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency 275system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency 276system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 277system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 280system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 281system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 285system.cpu.icache.fast_writes 0 # number of fast writes performed 286system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 287system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 288system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 289system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 290system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 291system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 292system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 293system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles 294system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses 304system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses 305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency 306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency 307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 308system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency | 282system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 283system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 284system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 285system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 286system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 287system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 288system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles 289system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 298system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses 299system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses 300system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency 301system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency 302system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 303system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency 304system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency 305system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency |
| 311system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 312system.cpu.l2cache.tags.replacements 0 # number of replacements 313system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use 314system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 315system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 316system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 318system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 393system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 394system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency 395system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 306system.cpu.l2cache.tags.replacements 0 # number of replacements 307system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use 308system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 309system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 310system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 311system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 312system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor 313system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 387system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency 389system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 401system.cpu.l2cache.fast_writes 0 # number of fast writes performed 402system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 403system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 404system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 405system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 406system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 407system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 408system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses 409system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 410system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 443system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency | 395system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 396system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 397system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses 398system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses 399system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 400system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses 401system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 435system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 436system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 437system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency 440system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency |
| 451system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 452system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution --- 52 unchanged lines hidden --- | 443system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 444system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 445system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 446system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 447system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 448system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 449system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 450system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution --- 52 unchanged lines hidden --- |