| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated |
| 4sim_ticks 32544500 # Number of ticks simulated 5final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 32545500 # Number of ticks simulated 5final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 619666 # Simulator instruction rate (inst/s) 8host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3148046044 # Simulator tick rate (ticks/s) 10host_mem_usage 291528 # Number of bytes of host memory used | 7host_inst_rate 507828 # Simulator instruction rate (inst/s) 8host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2581337246 # Simulator tick rate (ticks/s) 10host_mem_usage 294696 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 446 # Number of read requests responded to by this memory | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 446 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) |
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dtb.fetch_hits 0 # ITB hits 34system.cpu.dtb.fetch_misses 0 # ITB misses 35system.cpu.dtb.fetch_acv 0 # ITB acv 36system.cpu.dtb.fetch_accesses 0 # ITB accesses 37system.cpu.dtb.read_hits 1183 # DTB read hits 38system.cpu.dtb.read_misses 7 # DTB read misses 39system.cpu.dtb.read_acv 0 # DTB read access violations --- 18 unchanged lines hidden (view full) --- 58system.cpu.itb.write_misses 0 # DTB write misses 59system.cpu.itb.write_acv 0 # DTB write access violations 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.data_hits 0 # DTB hits 62system.cpu.itb.data_misses 0 # DTB misses 63system.cpu.itb.data_acv 0 # DTB access violations 64system.cpu.itb.data_accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 17 # Number of system calls | 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dtb.fetch_hits 0 # ITB hits 34system.cpu.dtb.fetch_misses 0 # ITB misses 35system.cpu.dtb.fetch_acv 0 # ITB acv 36system.cpu.dtb.fetch_accesses 0 # ITB accesses 37system.cpu.dtb.read_hits 1183 # DTB read hits 38system.cpu.dtb.read_misses 7 # DTB read misses 39system.cpu.dtb.read_acv 0 # DTB read access violations --- 18 unchanged lines hidden (view full) --- 58system.cpu.itb.write_misses 0 # DTB write misses 59system.cpu.itb.write_acv 0 # DTB write access violations 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.data_hits 0 # DTB hits 62system.cpu.itb.data_misses 0 # DTB misses 63system.cpu.itb.data_acv 0 # DTB access violations 64system.cpu.itb.data_accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 17 # Number of system calls |
| 66system.cpu.numCycles 65089 # number of cpu cycles simulated | 66system.cpu.numCycles 65091 # number of cpu cycles simulated |
| 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.committedInsts 6390 # Number of instructions committed 70system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 71system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 72system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 73system.cpu.num_func_calls 251 # number of times a function call or return occured 74system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 75system.cpu.num_int_insts 6317 # number of integer instructions 76system.cpu.num_fp_insts 10 # number of float instructions 77system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 78system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 79system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 80system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 81system.cpu.num_mem_refs 2058 # number of memory refs 82system.cpu.num_load_insts 1190 # Number of load instructions 83system.cpu.num_store_insts 868 # Number of store instructions 84system.cpu.num_idle_cycles 0 # Number of idle cycles | 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.committedInsts 6390 # Number of instructions committed 70system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 71system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 72system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 73system.cpu.num_func_calls 251 # number of times a function call or return occured 74system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 75system.cpu.num_int_insts 6317 # number of integer instructions 76system.cpu.num_fp_insts 10 # number of float instructions 77system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 78system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 79system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 80system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 81system.cpu.num_mem_refs 2058 # number of memory refs 82system.cpu.num_load_insts 1190 # Number of load instructions 83system.cpu.num_store_insts 868 # Number of store instructions 84system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 85system.cpu.num_busy_cycles 65089 # Number of busy cycles | 85system.cpu.num_busy_cycles 65091 # Number of busy cycles |
| 86system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 87system.cpu.idle_fraction 0 # Percentage of idle cycles 88system.cpu.Branches 1050 # Number of branches fetched 89system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 90system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 91system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 92system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 93system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 117system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 118system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 119system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 120system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 121system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 122system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 123system.cpu.op_class::total 6400 # Class of executed instruction 124system.cpu.dcache.tags.replacements 0 # number of replacements | 86system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 87system.cpu.idle_fraction 0 # Percentage of idle cycles 88system.cpu.Branches 1050 # Number of branches fetched 89system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 90system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 91system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 92system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 93system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 117system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 118system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 119system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 120system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 121system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 122system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 123system.cpu.op_class::total 6400 # Class of executed instruction 124system.cpu.dcache.tags.replacements 0 # number of replacements |
| 125system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use | 125system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use |
| 126system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. 127system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 128system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. 129system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 126system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. 127system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 128system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. 129system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 130system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor | 130system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor |
| 131system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy 132system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy 133system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 136system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 137system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses 138system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses --- 82 unchanged lines hidden (view full) --- 221system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 225system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 227system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 228system.cpu.icache.tags.replacements 0 # number of replacements | 131system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy 132system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy 133system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 136system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id 137system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses 138system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses --- 82 unchanged lines hidden (view full) --- 221system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency 223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 224system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 225system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency 226system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency 227system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 228system.cpu.icache.tags.replacements 0 # number of replacements |
| 229system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use | 229system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use |
| 230system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. 231system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 232system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. 233system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 230system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. 231system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. 232system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. 233system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 234system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor 235system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy 236system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy | 234system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor 235system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy 236system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy |
| 237system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 240system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 241system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses 242system.cpu.icache.tags.data_accesses 13081 # Number of data accesses 243system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 244system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 245system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 246system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 247system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 248system.cpu.icache.overall_hits::total 6122 # number of overall hits 249system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 250system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 251system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 252system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 253system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 254system.cpu.icache.overall_misses::total 279 # number of overall misses | 237system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id 238system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 239system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 240system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id 241system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses 242system.cpu.icache.tags.data_accesses 13081 # Number of data accesses 243system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits 244system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits 245system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits 246system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits 247system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits 248system.cpu.icache.overall_hits::total 6122 # number of overall hits 249system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 250system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses 251system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 252system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses 253system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses 254system.cpu.icache.overall_misses::total 279 # number of overall misses |
| 255system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles 256system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles 257system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles 258system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles 259system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles 260system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles | 255system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles 256system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles 257system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles 258system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles 259system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles 260system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles |
| 261system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 262system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 264system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 265system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 266system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 267system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 269system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 270system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 271system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 272system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses | 261system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) 262system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses 264system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses 265system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses 266system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses 267system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses 268system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses 269system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses 270system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses 271system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses 272system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses |
| 273system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency 274system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency 275system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency 276system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency 277system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency | 273system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency 274system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency 275system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency 276system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency 277system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency 278system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency |
| 279system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.icache.fast_writes 0 # number of fast writes performed 286system.cpu.icache.cache_copies 0 # number of cache copies performed 287system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 288system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 289system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 290system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 291system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 292system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses | 279system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.icache.fast_writes 0 # number of fast writes performed 286system.cpu.icache.cache_copies 0 # number of cache copies performed 287system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 288system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses 289system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 290system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses 291system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 292system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses |
| 293system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles 294system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles 295system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles 298system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles | 293system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles 294system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles 295system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles 296system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles 297system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles 298system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles |
| 299system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 301system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 302system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 304system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses | 299system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses 301system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses 302system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses 303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses 304system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses |
| 305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency 306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency 307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency 308system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency | 305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency 306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency 307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency 308system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency 309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency 310system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency |
| 311system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 312system.cpu.l2cache.tags.replacements 0 # number of replacements | 311system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 312system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 313system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use | 313system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use |
| 314system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 315system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 316system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 314system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 315system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 316system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. 317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 318system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor | 318system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor 319system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor |
| 320system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy | 320system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy 321system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy |
| 322system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy | 322system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy |
| 323system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 326system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 327system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 328system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses 329system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 330system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits --- 113 unchanged lines hidden (view full) --- 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency 451system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 323system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 326system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id 327system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses 328system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses 329system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 330system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits --- 113 unchanged lines hidden (view full) --- 444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency 448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency 449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency 451system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 452system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. 453system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 454system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 455system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 452system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution 457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 459system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 460system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 461system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 462system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.snoops 0 # Total snoops (count) 464system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram | 458system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution 463system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 464system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 465system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.snoops 0 # Total snoops (count) 470system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram |
| 465system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 471system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram 472system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram |
| 467system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 473system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 468system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 469system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram | 474system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram |
| 470system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 476system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 472system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 478system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 473system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 475system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 476system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 477system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 478system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- | 479system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram 481system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 482system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 483system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 484system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 485system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 486system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- |