| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33007000 # Number of ticks simulated 5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 524144 # Simulator instruction rate (inst/s) 8host_op_rate 523337 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2693393609 # Simulator tick rate (ticks/s) 10host_mem_usage 214140 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 6404 # Number of instructions simulated 13sim_ops 6404 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28544 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 446 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.fetch_hits 0 # ITB hits 31system.cpu.dtb.fetch_misses 0 # ITB misses 32system.cpu.dtb.fetch_acv 0 # ITB acv 33system.cpu.dtb.fetch_accesses 0 # ITB accesses 34system.cpu.dtb.read_hits 1185 # DTB read hits 35system.cpu.dtb.read_misses 7 # DTB read misses 36system.cpu.dtb.read_acv 0 # DTB read access violations 37system.cpu.dtb.read_accesses 1192 # DTB read accesses --- 73 unchanged lines hidden (view full) --- 111system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles 112system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses) 113system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses) 114system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses 115system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses 116system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses 117system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses 118system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses |
| 119system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses |
| 120system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses |
| 121system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses |
| 122system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses |
| 123system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses |
| 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency |
| 125system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency |
| 126system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency |
| 127system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency |
| 128system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency |
| 129system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency |
| 130system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 131system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 132system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 133system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 134system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 135system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 136system.cpu.icache.fast_writes 0 # number of fast writes performed 137system.cpu.icache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 143system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses 144system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles 145system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles 146system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles 147system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles 148system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles 149system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles 150system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses |
| 151system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses |
| 152system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses |
| 153system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses |
| 154system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses |
| 155system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses |
| 156system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency |
| 157system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency |
| 158system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency |
| 159system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency |
| 160system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency |
| 161system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency |
| 162system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 163system.cpu.dcache.replacements 0 # number of replacements 164system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use 165system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. 166system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. 167system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. 168system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 169system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 197system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) 198system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 199system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 200system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses 201system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses 202system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses 203system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses 204system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses |
| 205system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses |
| 206system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses |
| 207system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses |
| 208system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses |
| 209system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses |
| 210system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses |
| 211system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses |
| 212system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency |
| 213system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency |
| 214system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency |
| 215system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency |
| 216system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency |
| 217system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency |
| 218system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency |
| 219system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency |
| 220system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 221system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 222system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 223system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 224system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 225system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 226system.cpu.dcache.fast_writes 0 # number of fast writes performed 227system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 9 unchanged lines hidden (view full) --- 237system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles 238system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles 239system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles 240system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles 241system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles 242system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles 243system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles 244system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses |
| 245system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses |
| 246system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses |
| 247system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses |
| 248system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses |
| 249system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses |
| 250system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses |
| 251system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses |
| 252system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency |
| 253system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency |
| 254system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency |
| 255system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency |
| 256system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency |
| 257system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency |
| 258system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency |
| 259system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency |
| 260system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 261system.cpu.l2cache.replacements 0 # number of replacements 262system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use 263system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 264system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. 265system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. 266system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 267system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 305system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses 306system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 307system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses 308system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses 309system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 310system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses 311system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses 312system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 313system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses |
| 314system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 315system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 316system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses 317system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 318system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses |
| 319system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses 320system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 321system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses |
| 322system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 323system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency |
| 324system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency |
| 325system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency |
| 326system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency |
| 327system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 328system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency |
| 329system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency |
| 330system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 331system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency |
| 332system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency |
| 333system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 334system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 335system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 336system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 337system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 338system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 339system.cpu.l2cache.fast_writes 0 # number of fast writes performed 340system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 357system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles 358system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles 359system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles 360system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles 361system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles 362system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles 363system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses 364system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 365system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses |
| 366system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 367system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 368system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses 369system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 370system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses |
| 371system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses 372system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 373system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses |
| 374system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 375system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency |
| 376system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |
| 377system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency |
| 378system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency |
| 379system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 380system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 381system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
| 382system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 383system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency |
| 384system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency |
| 385system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 386 387---------- End Simulation Statistics ---------- |