1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 32544000 # Number of ticks simulated 5final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 485157 # Simulator instruction rate (inst/s) 8host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2465828156 # Simulator tick rate (ticks/s) 10host_mem_usage 286540 # Number of bytes of host memory used |
11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory --- 5 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) |
32system.membus.trans_dist::ReadReq 373 # Transaction distribution 33system.membus.trans_dist::ReadResp 373 # Transaction distribution 34system.membus.trans_dist::ReadExReq 73 # Transaction distribution 35system.membus.trans_dist::ReadExResp 73 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) |
38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 446 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 446 # Request fanout histogram |
51system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 53system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 12.3 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dtb.fetch_hits 0 # ITB hits 57system.cpu.dtb.fetch_misses 0 # ITB misses 58system.cpu.dtb.fetch_acv 0 # ITB acv --- 399 unchanged lines hidden (view full) --- 458system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 459system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 460system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 461system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 462system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 463system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 464system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 465system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
466system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 470system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) |
473system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 475system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.snoops 0 # Total snoops (count) 477system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram |
488system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) 489system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 490system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) 491system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 492system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) 493system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 494 495---------- End Simulation Statistics ---------- |