7,11c7,11
< host_inst_rate 236370 # Simulator instruction rate (inst/s)
< host_op_rate 236114 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1215776788 # Simulator tick rate (ticks/s)
< host_mem_usage 213800 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 524144 # Simulator instruction rate (inst/s)
> host_op_rate 523337 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2693393609 # Simulator tick rate (ticks/s)
> host_mem_usage 214140 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 28544 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 446 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s)
111a119
> system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses
112a121
> system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses
113a123
> system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses
114a125
> system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency
115a127
> system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency
116a129
> system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency
137a151
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses
138a153
> system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses
139a155
> system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses
140a157
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
141a159
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
142a161
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
185a205
> system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
186a207
> system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
187a209
> system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
188a211
> system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
189a213
> system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
190a215
> system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
191a217
> system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
192a219
> system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
217a245
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
218a247
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
219a249
> system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
220a251
> system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
221a253
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
222a255
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
223a257
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
224a259
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
277a313
> system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
278a315
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
280a318
> system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
282a321
> system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
284a324
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
285a326
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
287a329
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
289a332
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
321a365
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
322a367
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
324a370
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
326a373
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
328a376
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
329a378
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
331a381
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
333a384
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< host_inst_rate 236370 # Simulator instruction rate (inst/s)
< host_op_rate 236114 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1215776788 # Simulator tick rate (ticks/s)
< host_mem_usage 213800 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 524144 # Simulator instruction rate (inst/s)
> host_op_rate 523337 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2693393609 # Simulator tick rate (ticks/s)
> host_mem_usage 214140 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 28544 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 446 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s)
111a119
> system.cpu.icache.ReadReq_miss_rate::total 0.043492 # miss rate for ReadReq accesses
112a121
> system.cpu.icache.demand_miss_rate::total 0.043492 # miss rate for demand accesses
113a123
> system.cpu.icache.overall_miss_rate::total 0.043492 # miss rate for overall accesses
114a125
> system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366 # average ReadReq miss latency
115a127
> system.cpu.icache.demand_avg_miss_latency::total 55849.462366 # average overall miss latency
116a129
> system.cpu.icache.overall_avg_miss_latency::total 55849.462366 # average overall miss latency
137a151
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043492 # mshr miss rate for ReadReq accesses
138a153
> system.cpu.icache.demand_mshr_miss_rate::total 0.043492 # mshr miss rate for demand accesses
139a155
> system.cpu.icache.overall_mshr_miss_rate::total 0.043492 # mshr miss rate for overall accesses
140a157
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
141a159
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
142a161
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
185a205
> system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
186a207
> system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
187a209
> system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
188a211
> system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
189a213
> system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
190a215
> system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
191a217
> system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
192a219
> system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
217a245
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
218a247
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
219a249
> system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
220a251
> system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
221a253
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
222a255
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
223a257
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
224a259
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
277a313
> system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses
278a315
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
280a318
> system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses
282a321
> system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
284a324
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
285a326
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
287a329
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
289a332
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
321a365
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses
322a367
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
324a370
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses
326a373
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
328a376
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
329a378
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
331a381
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
333a384
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency