4,5c4,5
< sim_ticks 32544000 # Number of ticks simulated
< final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 32544500 # Number of ticks simulated
> final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 485157 # Simulator instruction rate (inst/s)
< host_op_rate 484642 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2465828156 # Simulator tick rate (ticks/s)
< host_mem_usage 286540 # Number of bytes of host memory used
---
> host_inst_rate 643051 # Simulator instruction rate (inst/s)
> host_op_rate 642147 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3266208350 # Simulator tick rate (ticks/s)
> host_mem_usage 291356 # Number of bytes of host memory used
24,54c24,31
< system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 373 # Transaction distribution
< system.membus.trans_dist::ReadResp 373 # Transaction distribution
< system.membus.trans_dist::ReadExReq 73 # Transaction distribution
< system.membus.trans_dist::ReadExResp 73 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 446 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 446 # Request fanout histogram
< system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s)
89c66
< system.cpu.numCycles 65088 # number of cpu cycles simulated
---
> system.cpu.numCycles 65089 # number of cpu cycles simulated
108c85
< system.cpu.num_busy_cycles 65088 # Number of busy cycles
---
> system.cpu.num_busy_cycles 65089 # Number of busy cycles
146a124,227
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
> system.cpu.dcache.overall_hits::total 1880 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
> system.cpu.dcache.overall_misses::total 168 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
148c229
< system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use
153,155c234,236
< system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
174,179c255,260
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles
192,197c273,278
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency
212,217c293,298
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles
224,229c305,310
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
232c313
< system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use
237,238c318,319
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor
265,275c346,356
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles
298,308c379,389
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency
328,338c409,419
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles
350,360c431,441
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
362,465d442
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
< system.cpu.dcache.overall_hits::total 1880 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
< system.cpu.dcache.overall_misses::total 168 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
493a471,493
> system.membus.trans_dist::ReadReq 373 # Transaction distribution
> system.membus.trans_dist::ReadResp 373 # Transaction distribution
> system.membus.trans_dist::ReadExReq 73 # Transaction distribution
> system.membus.trans_dist::ReadExResp 73 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 446 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 446 # Request fanout histogram
> system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
< sim_ticks 32544000 # Number of ticks simulated
< final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 32544500 # Number of ticks simulated
> final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 485157 # Simulator instruction rate (inst/s)
< host_op_rate 484642 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2465828156 # Simulator tick rate (ticks/s)
< host_mem_usage 286540 # Number of bytes of host memory used
---
> host_inst_rate 643051 # Simulator instruction rate (inst/s)
> host_op_rate 642147 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3266208350 # Simulator tick rate (ticks/s)
> host_mem_usage 291356 # Number of bytes of host memory used
24,54c24,31
< system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 373 # Transaction distribution
< system.membus.trans_dist::ReadResp 373 # Transaction distribution
< system.membus.trans_dist::ReadExReq 73 # Transaction distribution
< system.membus.trans_dist::ReadExResp 73 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 446 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 446 # Request fanout histogram
< system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s)
89c66
< system.cpu.numCycles 65088 # number of cpu cycles simulated
---
> system.cpu.numCycles 65089 # number of cpu cycles simulated
108c85
< system.cpu.num_busy_cycles 65088 # Number of busy cycles
---
> system.cpu.num_busy_cycles 65089 # Number of busy cycles
146a124,227
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
> system.cpu.dcache.overall_hits::total 1880 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
> system.cpu.dcache.overall_misses::total 168 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
148c229
< system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use
153,155c234,236
< system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
174,179c255,260
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles
192,197c273,278
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency
212,217c293,298
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles
224,229c305,310
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency
232c313
< system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use
237,238c318,319
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor
265,275c346,356
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles
298,308c379,389
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency
328,338c409,419
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles
350,360c431,441
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
362,465d442
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
< system.cpu.dcache.overall_hits::total 1880 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
< system.cpu.dcache.overall_misses::total 168 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
493a471,493
> system.membus.trans_dist::ReadReq 373 # Transaction distribution
> system.membus.trans_dist::ReadResp 373 # Transaction distribution
> system.membus.trans_dist::ReadExReq 73 # Transaction distribution
> system.membus.trans_dist::ReadExResp 73 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 446 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 446 # Request fanout histogram
> system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 6.9 # Layer utilization (%)