1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000033 # Number of seconds simulated
4sim_ticks 33007000 # Number of ticks simulated
5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000033 # Number of seconds simulated
4sim_ticks 33007000 # Number of ticks simulated
5final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 37663 # Simulator instruction rate (inst/s)
8host_op_rate 37658 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 194071847 # Simulator tick rate (ticks/s)
10host_mem_usage 209060 # Number of bytes of host memory used
11host_seconds 0.17 # Real time elapsed on the host
| 7host_inst_rate 236370 # Simulator instruction rate (inst/s)
8host_op_rate 236114 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1215776788 # Simulator tick rate (ticks/s)
10host_mem_usage 213800 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host
|
12sim_insts 6404 # Number of instructions simulated
13sim_ops 6404 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 28544 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 446 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.fetch_hits 0 # ITB hits
24system.cpu.dtb.fetch_misses 0 # ITB misses
25system.cpu.dtb.fetch_acv 0 # ITB acv
26system.cpu.dtb.fetch_accesses 0 # ITB accesses
27system.cpu.dtb.read_hits 1185 # DTB read hits
28system.cpu.dtb.read_misses 7 # DTB read misses
29system.cpu.dtb.read_acv 0 # DTB read access violations
30system.cpu.dtb.read_accesses 1192 # DTB read accesses
31system.cpu.dtb.write_hits 865 # DTB write hits
32system.cpu.dtb.write_misses 3 # DTB write misses
33system.cpu.dtb.write_acv 0 # DTB write access violations
34system.cpu.dtb.write_accesses 868 # DTB write accesses
35system.cpu.dtb.data_hits 2050 # DTB hits
36system.cpu.dtb.data_misses 10 # DTB misses
37system.cpu.dtb.data_acv 0 # DTB access violations
38system.cpu.dtb.data_accesses 2060 # DTB accesses
39system.cpu.itb.fetch_hits 6415 # ITB hits
40system.cpu.itb.fetch_misses 17 # ITB misses
41system.cpu.itb.fetch_acv 0 # ITB acv
42system.cpu.itb.fetch_accesses 6432 # ITB accesses
43system.cpu.itb.read_hits 0 # DTB read hits
44system.cpu.itb.read_misses 0 # DTB read misses
45system.cpu.itb.read_acv 0 # DTB read access violations
46system.cpu.itb.read_accesses 0 # DTB read accesses
47system.cpu.itb.write_hits 0 # DTB write hits
48system.cpu.itb.write_misses 0 # DTB write misses
49system.cpu.itb.write_acv 0 # DTB write access violations
50system.cpu.itb.write_accesses 0 # DTB write accesses
51system.cpu.itb.data_hits 0 # DTB hits
52system.cpu.itb.data_misses 0 # DTB misses
53system.cpu.itb.data_acv 0 # DTB access violations
54system.cpu.itb.data_accesses 0 # DTB accesses
55system.cpu.workload.num_syscalls 17 # Number of system calls
56system.cpu.numCycles 66014 # number of cpu cycles simulated
57system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
58system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
59system.cpu.committedInsts 6404 # Number of instructions committed
60system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
61system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
62system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
63system.cpu.num_func_calls 251 # number of times a function call or return occured
64system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
65system.cpu.num_int_insts 6331 # number of integer instructions
66system.cpu.num_fp_insts 10 # number of float instructions
67system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
68system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
69system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
70system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
71system.cpu.num_mem_refs 2060 # number of memory refs
72system.cpu.num_load_insts 1192 # Number of load instructions
73system.cpu.num_store_insts 868 # Number of store instructions
74system.cpu.num_idle_cycles 0 # Number of idle cycles
75system.cpu.num_busy_cycles 66014 # Number of busy cycles
76system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
77system.cpu.idle_fraction 0 # Percentage of idle cycles
78system.cpu.icache.replacements 0 # number of replacements
79system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
80system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
81system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
82system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
83system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
84system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor
85system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy
86system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy
87system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits
88system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits
89system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits
90system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits
91system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits
92system.cpu.icache.overall_hits::total 6136 # number of overall hits
93system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
94system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
95system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
96system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
97system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
98system.cpu.icache.overall_misses::total 279 # number of overall misses
99system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles
100system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles
101system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles
102system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles
103system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles
104system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles
105system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses)
106system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses)
107system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses
108system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses
109system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses
110system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses
111system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses
112system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses
113system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses
114system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency
115system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
116system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
117system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
118system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
119system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
120system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
| 12sim_insts 6404 # Number of instructions simulated
13sim_ops 6404 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 28544 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 446 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 864786257 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 539037174 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 864786257 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.fetch_hits 0 # ITB hits
24system.cpu.dtb.fetch_misses 0 # ITB misses
25system.cpu.dtb.fetch_acv 0 # ITB acv
26system.cpu.dtb.fetch_accesses 0 # ITB accesses
27system.cpu.dtb.read_hits 1185 # DTB read hits
28system.cpu.dtb.read_misses 7 # DTB read misses
29system.cpu.dtb.read_acv 0 # DTB read access violations
30system.cpu.dtb.read_accesses 1192 # DTB read accesses
31system.cpu.dtb.write_hits 865 # DTB write hits
32system.cpu.dtb.write_misses 3 # DTB write misses
33system.cpu.dtb.write_acv 0 # DTB write access violations
34system.cpu.dtb.write_accesses 868 # DTB write accesses
35system.cpu.dtb.data_hits 2050 # DTB hits
36system.cpu.dtb.data_misses 10 # DTB misses
37system.cpu.dtb.data_acv 0 # DTB access violations
38system.cpu.dtb.data_accesses 2060 # DTB accesses
39system.cpu.itb.fetch_hits 6415 # ITB hits
40system.cpu.itb.fetch_misses 17 # ITB misses
41system.cpu.itb.fetch_acv 0 # ITB acv
42system.cpu.itb.fetch_accesses 6432 # ITB accesses
43system.cpu.itb.read_hits 0 # DTB read hits
44system.cpu.itb.read_misses 0 # DTB read misses
45system.cpu.itb.read_acv 0 # DTB read access violations
46system.cpu.itb.read_accesses 0 # DTB read accesses
47system.cpu.itb.write_hits 0 # DTB write hits
48system.cpu.itb.write_misses 0 # DTB write misses
49system.cpu.itb.write_acv 0 # DTB write access violations
50system.cpu.itb.write_accesses 0 # DTB write accesses
51system.cpu.itb.data_hits 0 # DTB hits
52system.cpu.itb.data_misses 0 # DTB misses
53system.cpu.itb.data_acv 0 # DTB access violations
54system.cpu.itb.data_accesses 0 # DTB accesses
55system.cpu.workload.num_syscalls 17 # Number of system calls
56system.cpu.numCycles 66014 # number of cpu cycles simulated
57system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
58system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
59system.cpu.committedInsts 6404 # Number of instructions committed
60system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
61system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
62system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
63system.cpu.num_func_calls 251 # number of times a function call or return occured
64system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls
65system.cpu.num_int_insts 6331 # number of integer instructions
66system.cpu.num_fp_insts 10 # number of float instructions
67system.cpu.num_int_register_reads 8304 # number of times the integer registers were read
68system.cpu.num_int_register_writes 4581 # number of times the integer registers were written
69system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
70system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
71system.cpu.num_mem_refs 2060 # number of memory refs
72system.cpu.num_load_insts 1192 # Number of load instructions
73system.cpu.num_store_insts 868 # Number of store instructions
74system.cpu.num_idle_cycles 0 # Number of idle cycles
75system.cpu.num_busy_cycles 66014 # Number of busy cycles
76system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
77system.cpu.idle_fraction 0 # Percentage of idle cycles
78system.cpu.icache.replacements 0 # number of replacements
79system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
80system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
81system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
82system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
83system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
84system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor
85system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy
86system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy
87system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits
88system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits
89system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits
90system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits
91system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits
92system.cpu.icache.overall_hits::total 6136 # number of overall hits
93system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
94system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
95system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
96system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
97system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
98system.cpu.icache.overall_misses::total 279 # number of overall misses
99system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles
100system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles
101system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles
102system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles
103system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles
104system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles
105system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses)
106system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses)
107system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses
108system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses
109system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses
110system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses
111system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses
112system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses
113system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses
114system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency
115system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
116system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency
117system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
118system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
119system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
120system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
121system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
122system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 121system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
122system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
123system.cpu.icache.fast_writes 0 # number of fast writes performed
124system.cpu.icache.cache_copies 0 # number of cache copies performed
125system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
126system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
127system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
128system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
129system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
130system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
131system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
132system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
133system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
134system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
135system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
136system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
137system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses
138system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses
139system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses
140system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
141system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
142system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
143system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
144system.cpu.dcache.replacements 0 # number of replacements
145system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
146system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
147system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
148system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
149system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
150system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor
151system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy
152system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy
153system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
154system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
155system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
156system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
157system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
158system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
159system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
160system.cpu.dcache.overall_hits::total 1882 # number of overall hits
161system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
162system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
163system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
164system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
165system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
166system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
167system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
168system.cpu.dcache.overall_misses::total 168 # number of overall misses
169system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles
170system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles
171system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles
172system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles
173system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles
174system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles
175system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles
176system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles
177system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
178system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
179system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
180system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
181system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
182system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
183system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
184system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
185system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
186system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
187system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
188system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
189system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
192system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
193system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
194system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
195system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
196system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
| 123system.cpu.icache.fast_writes 0 # number of fast writes performed
124system.cpu.icache.cache_copies 0 # number of cache copies performed
125system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
126system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses
127system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
128system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
129system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
130system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
131system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles
132system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles
133system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles
134system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles
135system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles
136system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles
137system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses
138system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses
139system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses
140system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency
141system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
142system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
143system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
144system.cpu.dcache.replacements 0 # number of replacements
145system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
146system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
147system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
148system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
149system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
150system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor
151system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy
152system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy
153system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
154system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
155system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
156system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
157system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
158system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
159system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
160system.cpu.dcache.overall_hits::total 1882 # number of overall hits
161system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
162system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
163system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
164system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
165system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
166system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
167system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
168system.cpu.dcache.overall_misses::total 168 # number of overall misses
169system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles
170system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles
171system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles
172system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles
173system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles
174system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles
175system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles
176system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles
177system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
178system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
179system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
180system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
181system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
182system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
183system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
184system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
185system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
186system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
187system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
188system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
189system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
190system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
191system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
192system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
193system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
194system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
195system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
196system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
197system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
198system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 197system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
198system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
199system.cpu.dcache.fast_writes 0 # number of fast writes performed
200system.cpu.dcache.cache_copies 0 # number of cache copies performed
201system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
202system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
203system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
204system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
205system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
206system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
207system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
208system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
209system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
210system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
211system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
212system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
213system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
214system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
215system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
216system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
217system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
218system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
219system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
220system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
221system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
224system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
225system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
226system.cpu.l2cache.replacements 0 # number of replacements
227system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
228system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
229system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
230system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
231system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
232system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor
233system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor
234system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy
235system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
236system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy
237system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
238system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
239system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
240system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
241system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
242system.cpu.l2cache.overall_hits::total 1 # number of overall hits
243system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
244system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
245system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
246system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
247system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
248system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
249system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
250system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
251system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
252system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
253system.cpu.l2cache.overall_misses::total 446 # number of overall misses
254system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
255system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
256system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
257system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
258system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
259system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
260system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
261system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
262system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
263system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
264system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
265system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
266system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
267system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
268system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
269system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
270system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
271system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
272system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
273system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
274system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
275system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
276system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
277system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
278system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
279system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
280system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
281system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
282system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
283system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
284system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
285system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
286system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
287system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
288system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
289system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
290system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
291system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
292system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
293system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
| 199system.cpu.dcache.fast_writes 0 # number of fast writes performed
200system.cpu.dcache.cache_copies 0 # number of cache copies performed
201system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
202system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
203system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
204system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
205system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
206system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
207system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
208system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
209system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
210system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
211system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
212system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
213system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
214system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
215system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
216system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
217system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
218system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
219system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
220system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
221system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
222system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
223system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
224system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
225system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
226system.cpu.l2cache.replacements 0 # number of replacements
227system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
228system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
229system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
230system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
231system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
232system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor
233system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor
234system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy
235system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
236system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy
237system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
238system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
239system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
240system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
241system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
242system.cpu.l2cache.overall_hits::total 1 # number of overall hits
243system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
244system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
245system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses
246system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
247system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
248system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
249system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
250system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses
251system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
252system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
253system.cpu.l2cache.overall_misses::total 446 # number of overall misses
254system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
255system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles
256system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles
257system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles
258system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles
259system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
260system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles
261system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles
262system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
263system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles
264system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles
265system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses)
266system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
267system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses)
268system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
269system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
270system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses
271system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
272system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses
273system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses
274system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
275system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses
276system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses
277system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
278system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
279system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
280system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
281system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
282system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
283system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
284system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
285system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
286system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
287system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
288system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
289system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
290system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
291system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
292system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
293system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
294system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
295system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 294system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
295system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
296system.cpu.l2cache.fast_writes 0 # number of fast writes performed
297system.cpu.l2cache.cache_copies 0 # number of cache copies performed
298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
300system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
302system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
303system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
304system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
305system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
306system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
307system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
308system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
309system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
310system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
311system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
312system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
313system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
314system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
315system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
316system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
317system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
318system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
319system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
320system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
321system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
322system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
323system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
324system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
325system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
326system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
327system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
328system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
329system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
330system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
331system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
332system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
333system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
334system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
335
336---------- End Simulation Statistics ----------
| 296system.cpu.l2cache.fast_writes 0 # number of fast writes performed
297system.cpu.l2cache.cache_copies 0 # number of cache copies performed
298system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
299system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
300system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
301system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
302system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
303system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
304system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
305system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
306system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
307system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
308system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
309system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
310system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
311system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
312system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
313system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
314system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
315system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
316system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
317system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
318system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
319system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
320system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
321system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
322system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
323system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
324system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
325system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
326system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
327system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
328system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
329system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
330system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
331system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
332system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
333system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
334system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
335
336---------- End Simulation Statistics ----------
|