1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000033 # Number of seconds simulated
4sim_ticks 32544000 # Number of ticks simulated
5final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 550056 # Simulator instruction rate (inst/s)
8host_op_rate 549394 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2794675827 # Simulator tick rate (ticks/s)
10host_mem_usage 262632 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 6390 # Number of instructions simulated
13sim_ops 6390 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
--- 5 unchanged lines hidden (view full) ---
24system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 877089479 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 373 # Transaction distribution
34system.membus.trans_dist::ReadResp 373 # Transaction distribution
35system.membus.trans_dist::ReadExReq 73 # Transaction distribution
36system.membus.trans_dist::ReadExResp 73 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
40system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
41system.membus.data_through_bus 28544 # Total data (bytes)
42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
43system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
44system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
45system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
46system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
47system.cpu_clk_domain.clock 500 # Clock period in ticks
48system.cpu.dtb.fetch_hits 0 # ITB hits
49system.cpu.dtb.fetch_misses 0 # ITB misses
50system.cpu.dtb.fetch_acv 0 # ITB acv
--- 399 unchanged lines hidden (view full) ---
450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
454system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
455system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
456system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
459system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
463system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
467system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
470system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
471system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
472system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
473system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
474system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
475system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
476system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
477
478---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000033 # Number of seconds simulated
4sim_ticks 32544000 # Number of ticks simulated
5final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 550056 # Simulator instruction rate (inst/s)
8host_op_rate 549394 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2794675827 # Simulator tick rate (ticks/s)
10host_mem_usage 262632 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 6390 # Number of instructions simulated
13sim_ops 6390 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
18system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
--- 5 unchanged lines hidden (view full) ---
24system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
32system.membus.throughput 877089479 # Throughput (bytes/s)
33system.membus.trans_dist::ReadReq 373 # Transaction distribution
34system.membus.trans_dist::ReadResp 373 # Transaction distribution
35system.membus.trans_dist::ReadExReq 73 # Transaction distribution
36system.membus.trans_dist::ReadExResp 73 # Transaction distribution
37system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes)
38system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes)
39system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes)
40system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes)
41system.membus.data_through_bus 28544 # Total data (bytes)
42system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
43system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
44system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
45system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
46system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
47system.cpu_clk_domain.clock 500 # Clock period in ticks
48system.cpu.dtb.fetch_hits 0 # ITB hits
49system.cpu.dtb.fetch_misses 0 # ITB misses
50system.cpu.dtb.fetch_acv 0 # ITB acv
--- 399 unchanged lines hidden (view full) ---
450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
454system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
455system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
456system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
459system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
463system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes)
467system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
470system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
471system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
472system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
473system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
474system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
475system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
476system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
477
478---------- End Simulation Statistics ----------