| config.ini (8835:7c68f84d7c4e) | config.ini (8983:8800b05e1cb3) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 |
| 19physmem=system.physmem | |
| 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 | 19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1 |
| 29system_port=system.membus.port[0] | 28system_port=system.membus.slave[0] |
| 30 31[system.cpu] 32type=TimingSimpleCPU 33children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 34checker=Null 35clock=500 36cpu_id=0 37defer_registration=false --- 16 unchanged lines hidden (view full) --- 54system=system 55tracer=system.cpu.tracer 56workload=system.cpu.workload 57dcache_port=system.cpu.dcache.cpu_side 58icache_port=system.cpu.icache.cpu_side 59 60[system.cpu.dcache] 61type=BaseCache | 29 30[system.cpu] 31type=TimingSimpleCPU 32children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload 33checker=Null 34clock=500 35cpu_id=0 36defer_registration=false --- 16 unchanged lines hidden (view full) --- 53system=system 54tracer=system.cpu.tracer 55workload=system.cpu.workload 56dcache_port=system.cpu.dcache.cpu_side 57icache_port=system.cpu.icache.cpu_side 58 59[system.cpu.dcache] 60type=BaseCache |
| 62addr_range=0:18446744073709551615 | 61addr_ranges=0:18446744073709551615 |
| 63assoc=2 64block_size=64 65forward_snoops=true 66hash_delay=1 67is_top_level=true 68latency=1000 69max_miss_count=0 70mshrs=10 --- 4 unchanged lines hidden (view full) --- 75size=262144 76subblock_size=0 77system=system 78tgts_per_mshr=5 79trace_addr=0 80two_queue=false 81write_buffers=8 82cpu_side=system.cpu.dcache_port | 62assoc=2 63block_size=64 64forward_snoops=true 65hash_delay=1 66is_top_level=true 67latency=1000 68max_miss_count=0 69mshrs=10 --- 4 unchanged lines hidden (view full) --- 74size=262144 75subblock_size=0 76system=system 77tgts_per_mshr=5 78trace_addr=0 79two_queue=false 80write_buffers=8 81cpu_side=system.cpu.dcache_port |
| 83mem_side=system.cpu.toL2Bus.port[1] | 82mem_side=system.cpu.toL2Bus.slave[1] |
| 84 85[system.cpu.dtb] 86type=AlphaTLB 87size=64 88 89[system.cpu.icache] 90type=BaseCache | 83 84[system.cpu.dtb] 85type=AlphaTLB 86size=64 87 88[system.cpu.icache] 89type=BaseCache |
| 91addr_range=0:18446744073709551615 | 90addr_ranges=0:18446744073709551615 |
| 92assoc=2 93block_size=64 94forward_snoops=true 95hash_delay=1 96is_top_level=true 97latency=1000 98max_miss_count=0 99mshrs=10 --- 4 unchanged lines hidden (view full) --- 104size=131072 105subblock_size=0 106system=system 107tgts_per_mshr=5 108trace_addr=0 109two_queue=false 110write_buffers=8 111cpu_side=system.cpu.icache_port | 91assoc=2 92block_size=64 93forward_snoops=true 94hash_delay=1 95is_top_level=true 96latency=1000 97max_miss_count=0 98mshrs=10 --- 4 unchanged lines hidden (view full) --- 103size=131072 104subblock_size=0 105system=system 106tgts_per_mshr=5 107trace_addr=0 108two_queue=false 109write_buffers=8 110cpu_side=system.cpu.icache_port |
| 112mem_side=system.cpu.toL2Bus.port[0] | 111mem_side=system.cpu.toL2Bus.slave[0] |
| 113 114[system.cpu.interrupts] 115type=AlphaInterrupts 116 117[system.cpu.itb] 118type=AlphaTLB 119size=48 120 121[system.cpu.l2cache] 122type=BaseCache | 112 113[system.cpu.interrupts] 114type=AlphaInterrupts 115 116[system.cpu.itb] 117type=AlphaTLB 118size=48 119 120[system.cpu.l2cache] 121type=BaseCache |
| 123addr_range=0:18446744073709551615 | 122addr_ranges=0:18446744073709551615 |
| 124assoc=2 125block_size=64 126forward_snoops=true 127hash_delay=1 128is_top_level=false 129latency=10000 130max_miss_count=0 131mshrs=10 132prefetch_on_access=false 133prefetcher=Null 134prioritizeRequests=false 135repl=Null 136size=2097152 137subblock_size=0 138system=system 139tgts_per_mshr=5 140trace_addr=0 141two_queue=false 142write_buffers=8 | 123assoc=2 124block_size=64 125forward_snoops=true 126hash_delay=1 127is_top_level=false 128latency=10000 129max_miss_count=0 130mshrs=10 131prefetch_on_access=false 132prefetcher=Null 133prioritizeRequests=false 134repl=Null 135size=2097152 136subblock_size=0 137system=system 138tgts_per_mshr=5 139trace_addr=0 140two_queue=false 141write_buffers=8 |
| 143cpu_side=system.cpu.toL2Bus.port[2] 144mem_side=system.membus.port[2] | 142cpu_side=system.cpu.toL2Bus.master[0] 143mem_side=system.membus.slave[1] |
| 145 146[system.cpu.toL2Bus] 147type=Bus 148block_size=64 149bus_id=0 150clock=1000 151header_cycles=1 152use_default_range=false 153width=64 | 144 145[system.cpu.toL2Bus] 146type=Bus 147block_size=64 148bus_id=0 149clock=1000 150header_cycles=1 151use_default_range=false 152width=64 |
| 154port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side | 153master=system.cpu.l2cache.cpu_side 154slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side |
| 155 156[system.cpu.tracer] 157type=ExeTracer 158 159[system.cpu.workload] 160type=LiveProcess 161cmd=hello 162cwd= --- 15 unchanged lines hidden (view full) --- 178[system.membus] 179type=Bus 180block_size=64 181bus_id=0 182clock=1000 183header_cycles=1 184use_default_range=false 185width=64 | 155 156[system.cpu.tracer] 157type=ExeTracer 158 159[system.cpu.workload] 160type=LiveProcess 161cmd=hello 162cwd= --- 15 unchanged lines hidden (view full) --- 178[system.membus] 179type=Bus 180block_size=64 181bus_id=0 182clock=1000 183header_cycles=1 184use_default_range=false 185width=64 |
| 186port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side | 186master=system.physmem.port[0] 187slave=system.system_port system.cpu.l2cache.mem_side |
| 187 188[system.physmem] | 188 189[system.physmem] |
| 189type=PhysicalMemory | 190type=SimpleMemory 191conf_table_reported=false |
| 190file= | 192file= |
| 193in_addr_map=true |
|
| 191latency=30000 192latency_var=0 193null=false 194range=0:134217727 195zero=false | 194latency=30000 195latency_var=0 196null=false 197range=0:134217727 198zero=false |
| 196port=system.membus.port[1] | 199port=system.membus.master[0] |
| 197 | 200 |