| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 50 51[system.cpu] 52type=TimingSimpleCPU 53children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 54branchPred=Null 55checker=Null 56clk_domain=system.cpu_clk_domain 57cpu_id=0 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 |
| 63default_p_state=UNDEFINED |
|
| 58do_checkpoint_insts=true 59do_quiesce=true 60do_statistics_insts=true 61dtb=system.cpu.dtb 62eventq_index=0 63function_trace=false 64function_trace_start=0 65interrupts=system.cpu.interrupts 66isa=system.cpu.isa 67itb=system.cpu.itb 68max_insts_all_threads=0 69max_insts_any_thread=0 70max_loads_all_threads=0 71max_loads_any_thread=0 72numThreads=1 | 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 |
| 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null |
|
| 73profile=0 74progress_interval=0 75simpoint_start_insts= 76socket_id=0 77switched_out=false 78system=system 79tracer=system.cpu.tracer 80workload=system.cpu.workload 81dcache_port=system.cpu.dcache.cpu_side 82icache_port=system.cpu.icache.cpu_side 83 84[system.cpu.dcache] 85type=Cache 86children=tags 87addr_ranges=0:18446744073709551615 88assoc=2 89clk_domain=system.cpu_clk_domain 90clusivity=mostly_incl | 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload 91dcache_port=system.cpu.dcache.cpu_side 92icache_port=system.cpu.icache.cpu_side 93 94[system.cpu.dcache] 95type=Cache 96children=tags 97addr_ranges=0:18446744073709551615 98assoc=2 99clk_domain=system.cpu_clk_domain 100clusivity=mostly_incl |
| 101default_p_state=UNDEFINED |
|
| 91demand_mshr_reserve=1 92eventq_index=0 93hit_latency=2 94is_read_only=false 95max_miss_count=0 96mshrs=4 | 102demand_mshr_reserve=1 103eventq_index=0 104hit_latency=2 105is_read_only=false 106max_miss_count=0 107mshrs=4 |
| 108p_state_clk_gate_bins=20 109p_state_clk_gate_max=1000000000000 110p_state_clk_gate_min=1000 111power_model=Null |
|
| 97prefetch_on_access=false 98prefetcher=Null 99response_latency=2 100sequential_access=false 101size=262144 102system=system 103tags=system.cpu.dcache.tags 104tgts_per_mshr=20 105write_buffers=8 106writeback_clean=false 107cpu_side=system.cpu.dcache_port 108mem_side=system.cpu.toL2Bus.slave[1] 109 110[system.cpu.dcache.tags] 111type=LRU 112assoc=2 113block_size=64 114clk_domain=system.cpu_clk_domain | 112prefetch_on_access=false 113prefetcher=Null 114response_latency=2 115sequential_access=false 116size=262144 117system=system 118tags=system.cpu.dcache.tags 119tgts_per_mshr=20 120write_buffers=8 121writeback_clean=false 122cpu_side=system.cpu.dcache_port 123mem_side=system.cpu.toL2Bus.slave[1] 124 125[system.cpu.dcache.tags] 126type=LRU 127assoc=2 128block_size=64 129clk_domain=system.cpu_clk_domain |
| 130default_p_state=UNDEFINED |
|
| 115eventq_index=0 116hit_latency=2 | 131eventq_index=0 132hit_latency=2 |
| 133p_state_clk_gate_bins=20 134p_state_clk_gate_max=1000000000000 135p_state_clk_gate_min=1000 136power_model=Null |
|
| 117sequential_access=false 118size=262144 119 120[system.cpu.dtb] 121type=AlphaTLB 122eventq_index=0 123size=64 124 125[system.cpu.icache] 126type=Cache 127children=tags 128addr_ranges=0:18446744073709551615 129assoc=2 130clk_domain=system.cpu_clk_domain 131clusivity=mostly_incl | 137sequential_access=false 138size=262144 139 140[system.cpu.dtb] 141type=AlphaTLB 142eventq_index=0 143size=64 144 145[system.cpu.icache] 146type=Cache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain 151clusivity=mostly_incl |
| 152default_p_state=UNDEFINED |
|
| 132demand_mshr_reserve=1 133eventq_index=0 134hit_latency=2 135is_read_only=true 136max_miss_count=0 137mshrs=4 | 153demand_mshr_reserve=1 154eventq_index=0 155hit_latency=2 156is_read_only=true 157max_miss_count=0 158mshrs=4 |
| 159p_state_clk_gate_bins=20 160p_state_clk_gate_max=1000000000000 161p_state_clk_gate_min=1000 162power_model=Null |
|
| 138prefetch_on_access=false 139prefetcher=Null 140response_latency=2 141sequential_access=false 142size=131072 143system=system 144tags=system.cpu.icache.tags 145tgts_per_mshr=20 146write_buffers=8 147writeback_clean=true 148cpu_side=system.cpu.icache_port 149mem_side=system.cpu.toL2Bus.slave[0] 150 151[system.cpu.icache.tags] 152type=LRU 153assoc=2 154block_size=64 155clk_domain=system.cpu_clk_domain | 163prefetch_on_access=false 164prefetcher=Null 165response_latency=2 166sequential_access=false 167size=131072 168system=system 169tags=system.cpu.icache.tags 170tgts_per_mshr=20 171write_buffers=8 172writeback_clean=true 173cpu_side=system.cpu.icache_port 174mem_side=system.cpu.toL2Bus.slave[0] 175 176[system.cpu.icache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain |
| 181default_p_state=UNDEFINED |
|
| 156eventq_index=0 157hit_latency=2 | 182eventq_index=0 183hit_latency=2 |
| 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null |
|
| 158sequential_access=false 159size=131072 160 161[system.cpu.interrupts] 162type=AlphaInterrupts 163eventq_index=0 164 165[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 174 175[system.cpu.l2cache] 176type=Cache 177children=tags 178addr_ranges=0:18446744073709551615 179assoc=8 180clk_domain=system.cpu_clk_domain 181clusivity=mostly_incl | 188sequential_access=false 189size=131072 190 191[system.cpu.interrupts] 192type=AlphaInterrupts 193eventq_index=0 194 195[system.cpu.isa] --- 8 unchanged lines hidden (view full) --- 204 205[system.cpu.l2cache] 206type=Cache 207children=tags 208addr_ranges=0:18446744073709551615 209assoc=8 210clk_domain=system.cpu_clk_domain 211clusivity=mostly_incl |
| 212default_p_state=UNDEFINED |
|
| 182demand_mshr_reserve=1 183eventq_index=0 184hit_latency=20 185is_read_only=false 186max_miss_count=0 187mshrs=20 | 213demand_mshr_reserve=1 214eventq_index=0 215hit_latency=20 216is_read_only=false 217max_miss_count=0 218mshrs=20 |
| 219p_state_clk_gate_bins=20 220p_state_clk_gate_max=1000000000000 221p_state_clk_gate_min=1000 222power_model=Null |
|
| 188prefetch_on_access=false 189prefetcher=Null 190response_latency=20 191sequential_access=false 192size=2097152 193system=system 194tags=system.cpu.l2cache.tags 195tgts_per_mshr=12 196write_buffers=8 197writeback_clean=false 198cpu_side=system.cpu.toL2Bus.master[0] 199mem_side=system.membus.slave[1] 200 201[system.cpu.l2cache.tags] 202type=LRU 203assoc=8 204block_size=64 205clk_domain=system.cpu_clk_domain | 223prefetch_on_access=false 224prefetcher=Null 225response_latency=20 226sequential_access=false 227size=2097152 228system=system 229tags=system.cpu.l2cache.tags 230tgts_per_mshr=12 231write_buffers=8 232writeback_clean=false 233cpu_side=system.cpu.toL2Bus.master[0] 234mem_side=system.membus.slave[1] 235 236[system.cpu.l2cache.tags] 237type=LRU 238assoc=8 239block_size=64 240clk_domain=system.cpu_clk_domain |
| 241default_p_state=UNDEFINED |
|
| 206eventq_index=0 207hit_latency=20 | 242eventq_index=0 243hit_latency=20 |
| 244p_state_clk_gate_bins=20 245p_state_clk_gate_max=1000000000000 246p_state_clk_gate_min=1000 247power_model=Null |
|
| 208sequential_access=false 209size=2097152 210 211[system.cpu.toL2Bus] 212type=CoherentXBar 213children=snoop_filter 214clk_domain=system.cpu_clk_domain | 248sequential_access=false 249size=2097152 250 251[system.cpu.toL2Bus] 252type=CoherentXBar 253children=snoop_filter 254clk_domain=system.cpu_clk_domain |
| 255default_p_state=UNDEFINED |
|
| 215eventq_index=0 216forward_latency=0 217frontend_latency=1 | 256eventq_index=0 257forward_latency=0 258frontend_latency=1 |
| 259p_state_clk_gate_bins=20 260p_state_clk_gate_max=1000000000000 261p_state_clk_gate_min=1000 |
|
| 218point_of_coherency=false | 262point_of_coherency=false |
| 263power_model=Null |
|
| 219response_latency=1 220snoop_filter=system.cpu.toL2Bus.snoop_filter 221snoop_response_latency=1 222system=system 223use_default_range=false 224width=32 225master=system.cpu.l2cache.cpu_side 226slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 241cmd=hello 242cwd= 243drivers= 244egid=100 245env= 246errout=cerr 247euid=100 248eventq_index=0 | 264response_latency=1 265snoop_filter=system.cpu.toL2Bus.snoop_filter 266snoop_response_latency=1 267system=system 268use_default_range=false 269width=32 270master=system.cpu.l2cache.cpu_side 271slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 286cmd=hello 287cwd= 288drivers= 289egid=100 290env= 291errout=cerr 292euid=100 293eventq_index=0 |
| 249executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello | 294executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello |
| 250gid=100 251input=cin 252kvmInSE=false 253max_stack_size=67108864 254output=cout 255pid=100 256ppid=99 257simpoint=0 --- 15 unchanged lines hidden (view full) --- 273enable=false 274eventq_index=0 275sys_clk_domain=system.clk_domain 276transition_latency=100000000 277 278[system.membus] 279type=CoherentXBar 280clk_domain=system.clk_domain | 295gid=100 296input=cin 297kvmInSE=false 298max_stack_size=67108864 299output=cout 300pid=100 301ppid=99 302simpoint=0 --- 15 unchanged lines hidden (view full) --- 318enable=false 319eventq_index=0 320sys_clk_domain=system.clk_domain 321transition_latency=100000000 322 323[system.membus] 324type=CoherentXBar 325clk_domain=system.clk_domain |
| 326default_p_state=UNDEFINED |
|
| 281eventq_index=0 282forward_latency=4 283frontend_latency=3 | 327eventq_index=0 328forward_latency=4 329frontend_latency=3 |
| 330p_state_clk_gate_bins=20 331p_state_clk_gate_max=1000000000000 332p_state_clk_gate_min=1000 |
|
| 284point_of_coherency=true | 333point_of_coherency=true |
| 334power_model=Null |
|
| 285response_latency=2 286snoop_filter=Null 287snoop_response_latency=4 288system=system 289use_default_range=false 290width=16 291master=system.physmem.port 292slave=system.system_port system.cpu.l2cache.mem_side 293 294[system.physmem] 295type=SimpleMemory 296bandwidth=73.000000 297clk_domain=system.clk_domain 298conf_table_reported=true | 335response_latency=2 336snoop_filter=Null 337snoop_response_latency=4 338system=system 339use_default_range=false 340width=16 341master=system.physmem.port 342slave=system.system_port system.cpu.l2cache.mem_side 343 344[system.physmem] 345type=SimpleMemory 346bandwidth=73.000000 347clk_domain=system.clk_domain 348conf_table_reported=true |
| 349default_p_state=UNDEFINED |
|
| 299eventq_index=0 300in_addr_map=true 301latency=30000 302latency_var=0 303null=false | 350eventq_index=0 351in_addr_map=true 352latency=30000 353latency_var=0 354null=false |
| 355p_state_clk_gate_bins=20 356p_state_clk_gate_max=1000000000000 357p_state_clk_gate_min=1000 358power_model=Null |
|
| 304range=0:134217727 305port=system.membus.master[0] 306 307[system.voltage_domain] 308type=VoltageDomain 309eventq_index=0 310voltage=1.000000 311 | 359range=0:134217727 360port=system.membus.master[0] 361 362[system.voltage_domain] 363type=VoltageDomain 364eventq_index=0 365voltage=1.000000 366 |