config.ini (10736:4433fb00fa7d) | config.ini (10900:ac6617bf9967) |
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1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 73 unchanged lines hidden (view full) --- 82children=tags 83addr_ranges=0:18446744073709551615 84assoc=2 85clk_domain=system.cpu_clk_domain 86demand_mshr_reserve=1 87eventq_index=0 88forward_snoops=true 89hit_latency=2 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 73 unchanged lines hidden (view full) --- 82children=tags 83addr_ranges=0:18446744073709551615 84assoc=2 85clk_domain=system.cpu_clk_domain 86demand_mshr_reserve=1 87eventq_index=0 88forward_snoops=true 89hit_latency=2 |
90is_top_level=true | 90is_read_only=false |
91max_miss_count=0 92mshrs=4 93prefetch_on_access=false 94prefetcher=Null 95response_latency=2 96sequential_access=false 97size=262144 98system=system 99tags=system.cpu.dcache.tags 100tgts_per_mshr=20 | 91max_miss_count=0 92mshrs=4 93prefetch_on_access=false 94prefetcher=Null 95response_latency=2 96sequential_access=false 97size=262144 98system=system 99tags=system.cpu.dcache.tags 100tgts_per_mshr=20 |
101two_queue=false | |
102write_buffers=8 103cpu_side=system.cpu.dcache_port 104mem_side=system.cpu.toL2Bus.slave[1] 105 106[system.cpu.dcache.tags] 107type=LRU 108assoc=2 109block_size=64 --- 13 unchanged lines hidden (view full) --- 123children=tags 124addr_ranges=0:18446744073709551615 125assoc=2 126clk_domain=system.cpu_clk_domain 127demand_mshr_reserve=1 128eventq_index=0 129forward_snoops=true 130hit_latency=2 | 101write_buffers=8 102cpu_side=system.cpu.dcache_port 103mem_side=system.cpu.toL2Bus.slave[1] 104 105[system.cpu.dcache.tags] 106type=LRU 107assoc=2 108block_size=64 --- 13 unchanged lines hidden (view full) --- 122children=tags 123addr_ranges=0:18446744073709551615 124assoc=2 125clk_domain=system.cpu_clk_domain 126demand_mshr_reserve=1 127eventq_index=0 128forward_snoops=true 129hit_latency=2 |
131is_top_level=true | 130is_read_only=true |
132max_miss_count=0 133mshrs=4 134prefetch_on_access=false 135prefetcher=Null 136response_latency=2 137sequential_access=false 138size=131072 139system=system 140tags=system.cpu.icache.tags 141tgts_per_mshr=20 | 131max_miss_count=0 132mshrs=4 133prefetch_on_access=false 134prefetcher=Null 135response_latency=2 136sequential_access=false 137size=131072 138system=system 139tags=system.cpu.icache.tags 140tgts_per_mshr=20 |
142two_queue=false | |
143write_buffers=8 144cpu_side=system.cpu.icache_port 145mem_side=system.cpu.toL2Bus.slave[0] 146 147[system.cpu.icache.tags] 148type=LRU 149assoc=2 150block_size=64 --- 22 unchanged lines hidden (view full) --- 173children=tags 174addr_ranges=0:18446744073709551615 175assoc=8 176clk_domain=system.cpu_clk_domain 177demand_mshr_reserve=1 178eventq_index=0 179forward_snoops=true 180hit_latency=20 | 141write_buffers=8 142cpu_side=system.cpu.icache_port 143mem_side=system.cpu.toL2Bus.slave[0] 144 145[system.cpu.icache.tags] 146type=LRU 147assoc=2 148block_size=64 --- 22 unchanged lines hidden (view full) --- 171children=tags 172addr_ranges=0:18446744073709551615 173assoc=8 174clk_domain=system.cpu_clk_domain 175demand_mshr_reserve=1 176eventq_index=0 177forward_snoops=true 178hit_latency=20 |
181is_top_level=false | 179is_read_only=false |
182max_miss_count=0 183mshrs=20 184prefetch_on_access=false 185prefetcher=Null 186response_latency=20 187sequential_access=false 188size=2097152 189system=system 190tags=system.cpu.l2cache.tags 191tgts_per_mshr=12 | 180max_miss_count=0 181mshrs=20 182prefetch_on_access=false 183prefetcher=Null 184response_latency=20 185sequential_access=false 186size=2097152 187system=system 188tags=system.cpu.l2cache.tags 189tgts_per_mshr=12 |
192two_queue=false | |
193write_buffers=8 194cpu_side=system.cpu.toL2Bus.master[0] 195mem_side=system.membus.slave[1] 196 197[system.cpu.l2cache.tags] 198type=LRU 199assoc=8 200block_size=64 --- 97 unchanged lines hidden --- | 190write_buffers=8 191cpu_side=system.cpu.toL2Bus.master[0] 192mem_side=system.membus.slave[1] 193 194[system.cpu.l2cache.tags] 195type=LRU 196assoc=8 197block_size=64 --- 97 unchanged lines hidden --- |