Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt

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stats.txt (11219:b65d4e878ed2)	stats.txt (11268:8b4b55d79ddd)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000107 # Number of seconds simulated 4sim_ticks 107210 # Number of ticks simulated 5final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000107 # Number of seconds simulated 4sim_ticks 107210 # Number of ticks simulated 5final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks
7host_inst_rate 51155 # Simulator instruction rate (inst/s) 8host_op_rate 51148 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 858029 # Simulator tick rate (ticks/s) 10host_mem_usage 447104 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host	7host_inst_rate 30588 # Simulator instruction rate (inst/s) 8host_op_rate 30584 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 513061 # Simulator tick rate (ticks/s) 10host_mem_usage 388380 # Number of bytes of host memory used 11host_seconds 0.21 # Real time elapsed on the host
12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032739483 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 1032739483 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 1030351646 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 1030351646 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 2063091130 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 2063091130 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1730 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1726 # Number of write requests accepted 32system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 56896 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 53824 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 56448 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 841 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 48 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 85 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 116 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 24 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 31 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 19 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 266 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 49 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 44 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 29 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 13 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 262 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 79 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 107138 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 889 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 253 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 437.122530 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 269.105572 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 371.515393 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 63 24.90% 24.90% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 51 20.16% 45.06% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 24 9.49% 54.55% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 18 7.11% 61.66% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 14 5.53% 67.19% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 10 3.95% 71.15% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 18 7.11% 78.26% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 10 3.95% 82.21% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 45 17.79% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 253 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 16.028046 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 2.999243 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::12-13 1 1.85% 1.85% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::14-15 20 37.04% 38.89% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::16-17 27 50.00% 88.89% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::18-19 4 7.41% 96.30% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::20-21 1 1.85% 98.15% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes 211system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes 212system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::gmean 16.311361 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::stdev 0.890198 # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::16 47 87.04% 87.04% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::18 3 5.56% 92.59% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::19 4 7.41% 100.00% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads 220system.mem_ctrls.totQLat 10919 # Total ticks spent queuing 221system.mem_ctrls.totMemAccLat 27810 # Total ticks spent from burst creation until serviced by the DRAM 222system.mem_ctrls.totBusLat 4445 # Total ticks spent in databus transfers 223system.mem_ctrls.avgQLat 12.28 # Average queueing delay per DRAM burst 224system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 225system.mem_ctrls.avgMemAccLat 31.28 # Average memory access latency per DRAM burst 226system.mem_ctrls.avgRdBW 530.70 # Average DRAM read bandwidth in MiByte/s 227system.mem_ctrls.avgWrBW 526.52 # Average achieved write bandwidth in MiByte/s 228system.mem_ctrls.avgRdBWSys 1032.74 # Average system read bandwidth in MiByte/s 229system.mem_ctrls.avgWrBWSys 1030.35 # Average system write bandwidth in MiByte/s 230system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 231system.mem_ctrls.busUtil 8.26 # Data bus utilization in percentage 232system.mem_ctrls.busUtilRead 4.15 # Data bus utilization in percentage for reads 233system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes 234system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 235system.mem_ctrls.avgWrQLen 25.52 # Average write queue length when enqueuing 236system.mem_ctrls.readRowHits 682 # Number of row buffer hits during reads 237system.mem_ctrls.writeRowHits 829 # Number of row buffer hits during writes 238system.mem_ctrls.readRowHitRate 76.72 # Row buffer hit rate for reads 239system.mem_ctrls.writeRowHitRate 90.90 # Row buffer hit rate for writes 240system.mem_ctrls.avgGap 31.00 # Average gap between requests 241system.mem_ctrls.pageHitRate 83.90 # Row buffer hit rate, read and write combined 242system.mem_ctrls_0.actEnergy 748440 # Energy for activate commands per rank (pJ) 243system.mem_ctrls_0.preEnergy 415800 # Energy for precharge commands per rank (pJ) 244system.mem_ctrls_0.readEnergy 5166720 # Energy for read commands per rank (pJ) 245system.mem_ctrls_0.writeEnergy 4447872 # Energy for write commands per rank (pJ) 246system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 247system.mem_ctrls_0.actBackEnergy 64735128 # Energy for active background per rank (pJ) 248system.mem_ctrls_0.preBackEnergy 4101600 # Energy for precharge background per rank (pJ) 249system.mem_ctrls_0.totalEnergy 86226840 # Total energy per rank (pJ) 250system.mem_ctrls_0.averagePower 849.709691 # Core power per rank (mW) 251system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states 252system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::ACT 91640 # Time in different power states 255system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ) 257system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ) 258system.mem_ctrls_1.readEnergy 5241600 # Energy for read commands per rank (pJ) 259system.mem_ctrls_1.writeEnergy 4167936 # Energy for write commands per rank (pJ) 260system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 261system.mem_ctrls_1.actBackEnergy 64577808 # Energy for active background per rank (pJ) 262system.mem_ctrls_1.preBackEnergy 4239600 # Energy for precharge background per rank (pJ) 263system.mem_ctrls_1.totalEnergy 86531664 # Total energy per rank (pJ) 264system.mem_ctrls_1.averagePower 852.713534 # Core power per rank (mW) 265system.mem_ctrls_1.memoryStateTime::IDLE 6460 # Time in different power states 266system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::ACT 91652 # Time in different power states 269system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 270system.cpu.clk_domain.clock 1 # Clock period in ticks 271system.cpu.dtb.fetch_hits 0 # ITB hits 272system.cpu.dtb.fetch_misses 0 # ITB misses 273system.cpu.dtb.fetch_acv 0 # ITB acv 274system.cpu.dtb.fetch_accesses 0 # ITB accesses 275system.cpu.dtb.read_hits 1183 # DTB read hits 276system.cpu.dtb.read_misses 7 # DTB read misses 277system.cpu.dtb.read_acv 0 # DTB read access violations 278system.cpu.dtb.read_accesses 1190 # DTB read accesses 279system.cpu.dtb.write_hits 865 # DTB write hits 280system.cpu.dtb.write_misses 3 # DTB write misses 281system.cpu.dtb.write_acv 0 # DTB write access violations 282system.cpu.dtb.write_accesses 868 # DTB write accesses 283system.cpu.dtb.data_hits 2048 # DTB hits 284system.cpu.dtb.data_misses 10 # DTB misses 285system.cpu.dtb.data_acv 0 # DTB access violations 286system.cpu.dtb.data_accesses 2058 # DTB accesses 287system.cpu.itb.fetch_hits 6401 # ITB hits 288system.cpu.itb.fetch_misses 17 # ITB misses 289system.cpu.itb.fetch_acv 0 # ITB acv 290system.cpu.itb.fetch_accesses 6418 # ITB accesses 291system.cpu.itb.read_hits 0 # DTB read hits 292system.cpu.itb.read_misses 0 # DTB read misses 293system.cpu.itb.read_acv 0 # DTB read access violations 294system.cpu.itb.read_accesses 0 # DTB read accesses 295system.cpu.itb.write_hits 0 # DTB write hits 296system.cpu.itb.write_misses 0 # DTB write misses 297system.cpu.itb.write_acv 0 # DTB write access violations 298system.cpu.itb.write_accesses 0 # DTB write accesses 299system.cpu.itb.data_hits 0 # DTB hits 300system.cpu.itb.data_misses 0 # DTB misses 301system.cpu.itb.data_acv 0 # DTB access violations 302system.cpu.itb.data_accesses 0 # DTB accesses 303system.cpu.workload.num_syscalls 17 # Number of system calls 304system.cpu.numCycles 107210 # number of cpu cycles simulated 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 307system.cpu.committedInsts 6390 # Number of instructions committed 308system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 309system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 310system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 311system.cpu.num_func_calls 251 # number of times a function call or return occured 312system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 313system.cpu.num_int_insts 6317 # number of integer instructions 314system.cpu.num_fp_insts 10 # number of float instructions 315system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 316system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 317system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 318system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 319system.cpu.num_mem_refs 2058 # number of memory refs 320system.cpu.num_load_insts 1190 # Number of load instructions 321system.cpu.num_store_insts 868 # Number of store instructions 322system.cpu.num_idle_cycles 0 # Number of idle cycles 323system.cpu.num_busy_cycles 107210 # Number of busy cycles 324system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 325system.cpu.idle_fraction 0 # Percentage of idle cycles 326system.cpu.Branches 1050 # Number of branches fetched 327system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 328system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 329system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 330system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 331system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction 332system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction 333system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction 334system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction 335system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction 336system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction 337system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction 338system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction 339system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction 340system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction 341system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction 342system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction 343system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction 344system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction 345system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction 346system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction 347system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction 348system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction 349system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction 350system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction 351system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction 352system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction 353system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction 354system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction 355system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 356system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 357system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 358system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 359system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 360system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 361system.cpu.op_class::total 6400 # Class of executed instruction 362system.ruby.clk_domain.clock 1 # Clock period in ticks 363system.ruby.delayHist::bucket_size 1 # delay histogram for all message 364system.ruby.delayHist::max_bucket 9 # delay histogram for all message 365system.ruby.delayHist::samples 3456 # delay histogram for all message 366system.ruby.delayHist \| 3456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for all message 367system.ruby.delayHist::total 3456 # delay histogram for all message 368system.ruby.outstanding_req_hist::bucket_size 1 369system.ruby.outstanding_req_hist::max_bucket 9 370system.ruby.outstanding_req_hist::samples 8449 371system.ruby.outstanding_req_hist::mean 1 372system.ruby.outstanding_req_hist::gmean 1 373system.ruby.outstanding_req_hist \| 0 0.00% 0.00% \| 8449 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 374system.ruby.outstanding_req_hist::total 8449 375system.ruby.latency_hist::bucket_size 64 376system.ruby.latency_hist::max_bucket 639 377system.ruby.latency_hist::samples 8448 378system.ruby.latency_hist::mean 11.690578 379system.ruby.latency_hist::gmean 2.205273 380system.ruby.latency_hist::stdev 25.830363 381system.ruby.latency_hist \| 8209 97.17% 97.17% \| 184 2.18% 99.35% \| 38 0.45% 99.80% \| 7 0.08% 99.88% \| 6 0.07% 99.95% \| 3 0.04% 99.99% \| 0 0.00% 99.99% \| 1 0.01% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 382system.ruby.latency_hist::total 8448 383system.ruby.hit_latency_hist::bucket_size 1 384system.ruby.hit_latency_hist::max_bucket 9 385system.ruby.hit_latency_hist::samples 6718 386system.ruby.hit_latency_hist::mean 1 387system.ruby.hit_latency_hist::gmean 1 388system.ruby.hit_latency_hist \| 0 0.00% 0.00% \| 6718 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 389system.ruby.hit_latency_hist::total 6718 390system.ruby.miss_latency_hist::bucket_size 64 391system.ruby.miss_latency_hist::max_bucket 639 392system.ruby.miss_latency_hist::samples 1730 393system.ruby.miss_latency_hist::mean 53.204624 394system.ruby.miss_latency_hist::gmean 47.556283 395system.ruby.miss_latency_hist::stdev 33.032605 396system.ruby.miss_latency_hist \| 1491 86.18% 86.18% \| 184 10.64% 96.82% \| 38 2.20% 99.02% \| 7 0.40% 99.42% \| 6 0.35% 99.77% \| 3 0.17% 99.94% \| 0 0.00% 99.94% \| 1 0.06% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 397system.ruby.miss_latency_hist::total 1730 398system.ruby.Directory.incomplete_times 1729 399system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits 400system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses 401system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses 402system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 403system.ruby.network.routers0.percent_links_utilized 8.058950 404system.ruby.network.routers0.msg_count.Control::2 1730 405system.ruby.network.routers0.msg_count.Data::2 1726 406system.ruby.network.routers0.msg_count.Response_Data::4 1730 407system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 408system.ruby.network.routers0.msg_bytes.Control::2 13840 409system.ruby.network.routers0.msg_bytes.Data::2 124272 410system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 411system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 412system.ruby.network.routers1.percent_links_utilized 8.058950 413system.ruby.network.routers1.msg_count.Control::2 1730 414system.ruby.network.routers1.msg_count.Data::2 1726 415system.ruby.network.routers1.msg_count.Response_Data::4 1730 416system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 417system.ruby.network.routers1.msg_bytes.Control::2 13840 418system.ruby.network.routers1.msg_bytes.Data::2 124272 419system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 420system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 421system.ruby.network.routers2.percent_links_utilized 8.058950 422system.ruby.network.routers2.msg_count.Control::2 1730 423system.ruby.network.routers2.msg_count.Data::2 1726 424system.ruby.network.routers2.msg_count.Response_Data::4 1730 425system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 426system.ruby.network.routers2.msg_bytes.Control::2 13840 427system.ruby.network.routers2.msg_bytes.Data::2 124272 428system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 429system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 430system.ruby.network.msg_count.Control 5190 431system.ruby.network.msg_count.Data 5178 432system.ruby.network.msg_count.Response_Data 5190 433system.ruby.network.msg_count.Writeback_Control 5178 434system.ruby.network.msg_byte.Control 41520 435system.ruby.network.msg_byte.Data 372816 436system.ruby.network.msg_byte.Response_Data 373680 437system.ruby.network.msg_byte.Writeback_Control 41424 438system.ruby.network.routers0.throttle0.link_utilization 8.066412 439system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 440system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 441system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 442system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 443system.ruby.network.routers0.throttle1.link_utilization 8.051488 444system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 445system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 446system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 447system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 448system.ruby.network.routers1.throttle0.link_utilization 8.051488 449system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 450system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 451system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 452system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 453system.ruby.network.routers1.throttle1.link_utilization 8.066412 454system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 455system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 456system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 457system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 458system.ruby.network.routers2.throttle0.link_utilization 8.066412 459system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 460system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 461system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 462system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 463system.ruby.network.routers2.throttle1.link_utilization 8.051488 464system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 465system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 466system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 467system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272 468system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 469system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 470system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1 471system.ruby.delayVCHist.vnet_1 \| 1730 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_1 472system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1 473system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 474system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 475system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 476system.ruby.delayVCHist.vnet_2 \| 1726 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_2 477system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 478system.ruby.LD.latency_hist::bucket_size 64 479system.ruby.LD.latency_hist::max_bucket 639 480system.ruby.LD.latency_hist::samples 1183 481system.ruby.LD.latency_hist::mean 31.638208 482system.ruby.LD.latency_hist::gmean 10.419015 483system.ruby.LD.latency_hist::stdev 35.065266 484system.ruby.LD.latency_hist \| 1085 91.72% 91.72% \| 74 6.26% 97.97% \| 18 1.52% 99.49% \| 2 0.17% 99.66% \| 3 0.25% 99.92% \| 1 0.08% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 485system.ruby.LD.latency_hist::total 1183 486system.ruby.LD.hit_latency_hist::bucket_size 1 487system.ruby.LD.hit_latency_hist::max_bucket 9 488system.ruby.LD.hit_latency_hist::samples 456 489system.ruby.LD.hit_latency_hist::mean 1 490system.ruby.LD.hit_latency_hist::gmean 1 491system.ruby.LD.hit_latency_hist \| 0 0.00% 0.00% \| 456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 492system.ruby.LD.hit_latency_hist::total 456 493system.ruby.LD.miss_latency_hist::bucket_size 64 494system.ruby.LD.miss_latency_hist::max_bucket 639 495system.ruby.LD.miss_latency_hist::samples 727 496system.ruby.LD.miss_latency_hist::mean 50.855571 497system.ruby.LD.miss_latency_hist::gmean 45.315147 498system.ruby.LD.miss_latency_hist::stdev 32.287061 499system.ruby.LD.miss_latency_hist \| 629 86.52% 86.52% \| 74 10.18% 96.70% \| 18 2.48% 99.17% \| 2 0.28% 99.45% \| 3 0.41% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 500system.ruby.LD.miss_latency_hist::total 727 501system.ruby.ST.latency_hist::bucket_size 32 502system.ruby.ST.latency_hist::max_bucket 319 503system.ruby.ST.latency_hist::samples 865 504system.ruby.ST.latency_hist::mean 16.483237 505system.ruby.ST.latency_hist::gmean 3.324735 506system.ruby.ST.latency_hist::stdev 28.016571 507system.ruby.ST.latency_hist \| 592 68.44% 68.44% \| 244 28.21% 96.65% \| 18 2.08% 98.73% \| 2 0.23% 98.96% \| 5 0.58% 99.54% \| 2 0.23% 99.77% \| 1 0.12% 99.88% \| 0 0.00% 99.88% \| 1 0.12% 100.00% \| 0 0.00% 100.00% 508system.ruby.ST.latency_hist::total 865 509system.ruby.ST.hit_latency_hist::bucket_size 1 510system.ruby.ST.hit_latency_hist::max_bucket 9 511system.ruby.ST.hit_latency_hist::samples 592 512system.ruby.ST.hit_latency_hist::mean 1 513system.ruby.ST.hit_latency_hist::gmean 1 514system.ruby.ST.hit_latency_hist \| 0 0.00% 0.00% \| 592 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 515system.ruby.ST.hit_latency_hist::total 592 516system.ruby.ST.miss_latency_hist::bucket_size 32 517system.ruby.ST.miss_latency_hist::max_bucket 319 518system.ruby.ST.miss_latency_hist::samples 273 519system.ruby.ST.miss_latency_hist::mean 50.058608 520system.ruby.ST.miss_latency_hist::gmean 44.997273 521system.ruby.ST.miss_latency_hist::stdev 28.984216 522system.ruby.ST.miss_latency_hist \| 0 0.00% 0.00% \| 244 89.38% 89.38% \| 18 6.59% 95.97% \| 2 0.73% 96.70% \| 5 1.83% 98.53% \| 2 0.73% 99.27% \| 1 0.37% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% 523system.ruby.ST.miss_latency_hist::total 273 524system.ruby.IFETCH.latency_hist::bucket_size 64 525system.ruby.IFETCH.latency_hist::max_bucket 639 526system.ruby.IFETCH.latency_hist::samples 6400 527system.ruby.IFETCH.latency_hist::mean 7.355625 528system.ruby.IFETCH.latency_hist::gmean 1.565715 529system.ruby.IFETCH.latency_hist::stdev 21.264557 530system.ruby.IFETCH.latency_hist \| 6288 98.25% 98.25% \| 90 1.41% 99.66% \| 13 0.20% 99.86% \| 4 0.06% 99.92% \| 2 0.03% 99.95% \| 2 0.03% 99.98% \| 0 0.00% 99.98% \| 1 0.02% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 531system.ruby.IFETCH.latency_hist::total 6400 532system.ruby.IFETCH.hit_latency_hist::bucket_size 1 533system.ruby.IFETCH.hit_latency_hist::max_bucket 9 534system.ruby.IFETCH.hit_latency_hist::samples 5670 535system.ruby.IFETCH.hit_latency_hist::mean 1 536system.ruby.IFETCH.hit_latency_hist::gmean 1 537system.ruby.IFETCH.hit_latency_hist \| 0 0.00% 0.00% \| 5670 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 538system.ruby.IFETCH.hit_latency_hist::total 5670 539system.ruby.IFETCH.miss_latency_hist::bucket_size 64 540system.ruby.IFETCH.miss_latency_hist::max_bucket 639 541system.ruby.IFETCH.miss_latency_hist::samples 730 542system.ruby.IFETCH.miss_latency_hist::mean 56.720548 543system.ruby.IFETCH.miss_latency_hist::gmean 50.941265 544system.ruby.IFETCH.miss_latency_hist::stdev 34.853032 545system.ruby.IFETCH.miss_latency_hist \| 618 84.66% 84.66% \| 90 12.33% 96.99% \| 13 1.78% 98.77% \| 4 0.55% 99.32% \| 2 0.27% 99.59% \| 2 0.27% 99.86% \| 0 0.00% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 546system.ruby.IFETCH.miss_latency_hist::total 730 547system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 548system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 549system.ruby.Directory.miss_mach_latency_hist::samples 1730 550system.ruby.Directory.miss_mach_latency_hist::mean 53.204624 551system.ruby.Directory.miss_mach_latency_hist::gmean 47.556283 552system.ruby.Directory.miss_mach_latency_hist::stdev 33.032605 553system.ruby.Directory.miss_mach_latency_hist \| 1491 86.18% 86.18% \| 184 10.64% 96.82% \| 38 2.20% 99.02% \| 7 0.40% 99.42% \| 6 0.35% 99.77% \| 3 0.17% 99.94% \| 0 0.00% 99.94% \| 1 0.06% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 554system.ruby.Directory.miss_mach_latency_hist::total 1730 555system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 556system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 557system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 558system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 559system.ruby.Directory.miss_latency_hist.issue_to_initial_request \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 560system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 561system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 562system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 563system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 564system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 565system.ruby.Directory.miss_latency_hist.initial_to_forward \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 566system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 567system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 568system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 569system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 570system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 571system.ruby.Directory.miss_latency_hist.forward_to_first_response \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 572system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 573system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 574system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 575system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 576system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 577system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 578system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 579system.ruby.Directory.miss_latency_hist.first_response_to_completion \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% 580system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 581system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 582system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 583system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 584system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 50.855571 585system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 45.315147 586system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.287061 587system.ruby.LD.Directory.miss_type_mach_latency_hist \| 629 86.52% 86.52% \| 74 10.18% 96.70% \| 18 2.48% 99.17% \| 2 0.28% 99.45% \| 3 0.41% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 588system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 589system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 590system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 591system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 592system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 50.058608 593system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.997273 594system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 28.984216 595system.ruby.ST.Directory.miss_type_mach_latency_hist \| 0 0.00% 0.00% \| 244 89.38% 89.38% \| 18 6.59% 95.97% \| 2 0.73% 96.70% \| 5 1.83% 98.53% \| 2 0.73% 99.27% \| 1 0.37% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% 596system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 599system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 600system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.720548 601system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.941265 602system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.853032 603system.ruby.IFETCH.Directory.miss_type_mach_latency_hist \| 618 84.66% 84.66% \| 90 12.33% 96.99% \| 13 1.78% 98.77% \| 4 0.55% 99.32% \| 2 0.27% 99.59% \| 2 0.27% 99.86% \| 0 0.00% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 604system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 605system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% 606system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% 607system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% 608system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% 609system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% 610system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% 611system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% 612system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% 613system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% 614system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% 615system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% 616system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00% 617system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00% 618system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00% 619system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00% 620system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% 621system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% 622system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00% 623system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00% 624system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% 625system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% 626system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% 627system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% 628system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% 629 630---------- End Simulation Statistics ----------	12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032739483 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 1032739483 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 1030351646 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 1030351646 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 2063091130 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 2063091130 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1730 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1726 # Number of write requests accepted 32system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 56896 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 53824 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 56448 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 841 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 48 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 85 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 116 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 24 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 31 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 19 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 266 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 49 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 44 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 29 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 13 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 262 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 79 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 107138 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 889 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 253 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 437.122530 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 269.105572 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 371.515393 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 63 24.90% 24.90% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 51 20.16% 45.06% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 24 9.49% 54.55% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 18 7.11% 61.66% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 14 5.53% 67.19% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 10 3.95% 71.15% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 18 7.11% 78.26% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 10 3.95% 82.21% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 45 17.79% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 253 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 16.028046 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 2.999243 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::12-13 1 1.85% 1.85% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::14-15 20 37.04% 38.89% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::16-17 27 50.00% 88.89% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::18-19 4 7.41% 96.30% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::20-21 1 1.85% 98.15% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes 211system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes 212system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::gmean 16.311361 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::stdev 0.890198 # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::16 47 87.04% 87.04% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::18 3 5.56% 92.59% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::19 4 7.41% 100.00% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads 220system.mem_ctrls.totQLat 10919 # Total ticks spent queuing 221system.mem_ctrls.totMemAccLat 27810 # Total ticks spent from burst creation until serviced by the DRAM 222system.mem_ctrls.totBusLat 4445 # Total ticks spent in databus transfers 223system.mem_ctrls.avgQLat 12.28 # Average queueing delay per DRAM burst 224system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 225system.mem_ctrls.avgMemAccLat 31.28 # Average memory access latency per DRAM burst 226system.mem_ctrls.avgRdBW 530.70 # Average DRAM read bandwidth in MiByte/s 227system.mem_ctrls.avgWrBW 526.52 # Average achieved write bandwidth in MiByte/s 228system.mem_ctrls.avgRdBWSys 1032.74 # Average system read bandwidth in MiByte/s 229system.mem_ctrls.avgWrBWSys 1030.35 # Average system write bandwidth in MiByte/s 230system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 231system.mem_ctrls.busUtil 8.26 # Data bus utilization in percentage 232system.mem_ctrls.busUtilRead 4.15 # Data bus utilization in percentage for reads 233system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes 234system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 235system.mem_ctrls.avgWrQLen 25.52 # Average write queue length when enqueuing 236system.mem_ctrls.readRowHits 682 # Number of row buffer hits during reads 237system.mem_ctrls.writeRowHits 829 # Number of row buffer hits during writes 238system.mem_ctrls.readRowHitRate 76.72 # Row buffer hit rate for reads 239system.mem_ctrls.writeRowHitRate 90.90 # Row buffer hit rate for writes 240system.mem_ctrls.avgGap 31.00 # Average gap between requests 241system.mem_ctrls.pageHitRate 83.90 # Row buffer hit rate, read and write combined 242system.mem_ctrls_0.actEnergy 748440 # Energy for activate commands per rank (pJ) 243system.mem_ctrls_0.preEnergy 415800 # Energy for precharge commands per rank (pJ) 244system.mem_ctrls_0.readEnergy 5166720 # Energy for read commands per rank (pJ) 245system.mem_ctrls_0.writeEnergy 4447872 # Energy for write commands per rank (pJ) 246system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 247system.mem_ctrls_0.actBackEnergy 64735128 # Energy for active background per rank (pJ) 248system.mem_ctrls_0.preBackEnergy 4101600 # Energy for precharge background per rank (pJ) 249system.mem_ctrls_0.totalEnergy 86226840 # Total energy per rank (pJ) 250system.mem_ctrls_0.averagePower 849.709691 # Core power per rank (mW) 251system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states 252system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::ACT 91640 # Time in different power states 255system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 256system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ) 257system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ) 258system.mem_ctrls_1.readEnergy 5241600 # Energy for read commands per rank (pJ) 259system.mem_ctrls_1.writeEnergy 4167936 # Energy for write commands per rank (pJ) 260system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) 261system.mem_ctrls_1.actBackEnergy 64577808 # Energy for active background per rank (pJ) 262system.mem_ctrls_1.preBackEnergy 4239600 # Energy for precharge background per rank (pJ) 263system.mem_ctrls_1.totalEnergy 86531664 # Total energy per rank (pJ) 264system.mem_ctrls_1.averagePower 852.713534 # Core power per rank (mW) 265system.mem_ctrls_1.memoryStateTime::IDLE 6460 # Time in different power states 266system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::ACT 91652 # Time in different power states 269system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 270system.cpu.clk_domain.clock 1 # Clock period in ticks 271system.cpu.dtb.fetch_hits 0 # ITB hits 272system.cpu.dtb.fetch_misses 0 # ITB misses 273system.cpu.dtb.fetch_acv 0 # ITB acv 274system.cpu.dtb.fetch_accesses 0 # ITB accesses 275system.cpu.dtb.read_hits 1183 # DTB read hits 276system.cpu.dtb.read_misses 7 # DTB read misses 277system.cpu.dtb.read_acv 0 # DTB read access violations 278system.cpu.dtb.read_accesses 1190 # DTB read accesses 279system.cpu.dtb.write_hits 865 # DTB write hits 280system.cpu.dtb.write_misses 3 # DTB write misses 281system.cpu.dtb.write_acv 0 # DTB write access violations 282system.cpu.dtb.write_accesses 868 # DTB write accesses 283system.cpu.dtb.data_hits 2048 # DTB hits 284system.cpu.dtb.data_misses 10 # DTB misses 285system.cpu.dtb.data_acv 0 # DTB access violations 286system.cpu.dtb.data_accesses 2058 # DTB accesses 287system.cpu.itb.fetch_hits 6401 # ITB hits 288system.cpu.itb.fetch_misses 17 # ITB misses 289system.cpu.itb.fetch_acv 0 # ITB acv 290system.cpu.itb.fetch_accesses 6418 # ITB accesses 291system.cpu.itb.read_hits 0 # DTB read hits 292system.cpu.itb.read_misses 0 # DTB read misses 293system.cpu.itb.read_acv 0 # DTB read access violations 294system.cpu.itb.read_accesses 0 # DTB read accesses 295system.cpu.itb.write_hits 0 # DTB write hits 296system.cpu.itb.write_misses 0 # DTB write misses 297system.cpu.itb.write_acv 0 # DTB write access violations 298system.cpu.itb.write_accesses 0 # DTB write accesses 299system.cpu.itb.data_hits 0 # DTB hits 300system.cpu.itb.data_misses 0 # DTB misses 301system.cpu.itb.data_acv 0 # DTB access violations 302system.cpu.itb.data_accesses 0 # DTB accesses 303system.cpu.workload.num_syscalls 17 # Number of system calls 304system.cpu.numCycles 107210 # number of cpu cycles simulated 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 307system.cpu.committedInsts 6390 # Number of instructions committed 308system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 309system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 310system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 311system.cpu.num_func_calls 251 # number of times a function call or return occured 312system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 313system.cpu.num_int_insts 6317 # number of integer instructions 314system.cpu.num_fp_insts 10 # number of float instructions 315system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 316system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 317system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 318system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 319system.cpu.num_mem_refs 2058 # number of memory refs 320system.cpu.num_load_insts 1190 # Number of load instructions 321system.cpu.num_store_insts 868 # Number of store instructions 322system.cpu.num_idle_cycles 0 # Number of idle cycles 323system.cpu.num_busy_cycles 107210 # Number of busy cycles 324system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 325system.cpu.idle_fraction 0 # Percentage of idle cycles 326system.cpu.Branches 1050 # Number of branches fetched 327system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 328system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 329system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 330system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 331system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction 332system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction 333system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction 334system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction 335system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction 336system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction 337system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction 338system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction 339system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction 340system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction 341system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction 342system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction 343system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction 344system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction 345system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction 346system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction 347system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction 348system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction 349system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction 350system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction 351system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction 352system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction 353system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction 354system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction 355system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 356system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 357system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 358system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 359system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 360system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 361system.cpu.op_class::total 6400 # Class of executed instruction 362system.ruby.clk_domain.clock 1 # Clock period in ticks 363system.ruby.delayHist::bucket_size 1 # delay histogram for all message 364system.ruby.delayHist::max_bucket 9 # delay histogram for all message 365system.ruby.delayHist::samples 3456 # delay histogram for all message 366system.ruby.delayHist \| 3456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for all message 367system.ruby.delayHist::total 3456 # delay histogram for all message 368system.ruby.outstanding_req_hist::bucket_size 1 369system.ruby.outstanding_req_hist::max_bucket 9 370system.ruby.outstanding_req_hist::samples 8449 371system.ruby.outstanding_req_hist::mean 1 372system.ruby.outstanding_req_hist::gmean 1 373system.ruby.outstanding_req_hist \| 0 0.00% 0.00% \| 8449 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 374system.ruby.outstanding_req_hist::total 8449 375system.ruby.latency_hist::bucket_size 64 376system.ruby.latency_hist::max_bucket 639 377system.ruby.latency_hist::samples 8448 378system.ruby.latency_hist::mean 11.690578 379system.ruby.latency_hist::gmean 2.205273 380system.ruby.latency_hist::stdev 25.830363 381system.ruby.latency_hist \| 8209 97.17% 97.17% \| 184 2.18% 99.35% \| 38 0.45% 99.80% \| 7 0.08% 99.88% \| 6 0.07% 99.95% \| 3 0.04% 99.99% \| 0 0.00% 99.99% \| 1 0.01% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 382system.ruby.latency_hist::total 8448 383system.ruby.hit_latency_hist::bucket_size 1 384system.ruby.hit_latency_hist::max_bucket 9 385system.ruby.hit_latency_hist::samples 6718 386system.ruby.hit_latency_hist::mean 1 387system.ruby.hit_latency_hist::gmean 1 388system.ruby.hit_latency_hist \| 0 0.00% 0.00% \| 6718 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 389system.ruby.hit_latency_hist::total 6718 390system.ruby.miss_latency_hist::bucket_size 64 391system.ruby.miss_latency_hist::max_bucket 639 392system.ruby.miss_latency_hist::samples 1730 393system.ruby.miss_latency_hist::mean 53.204624 394system.ruby.miss_latency_hist::gmean 47.556283 395system.ruby.miss_latency_hist::stdev 33.032605 396system.ruby.miss_latency_hist \| 1491 86.18% 86.18% \| 184 10.64% 96.82% \| 38 2.20% 99.02% \| 7 0.40% 99.42% \| 6 0.35% 99.77% \| 3 0.17% 99.94% \| 0 0.00% 99.94% \| 1 0.06% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 397system.ruby.miss_latency_hist::total 1730 398system.ruby.Directory.incomplete_times 1729 399system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits 400system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses 401system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses 402system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 403system.ruby.network.routers0.percent_links_utilized 8.058950 404system.ruby.network.routers0.msg_count.Control::2 1730 405system.ruby.network.routers0.msg_count.Data::2 1726 406system.ruby.network.routers0.msg_count.Response_Data::4 1730 407system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 408system.ruby.network.routers0.msg_bytes.Control::2 13840 409system.ruby.network.routers0.msg_bytes.Data::2 124272 410system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 411system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 412system.ruby.network.routers1.percent_links_utilized 8.058950 413system.ruby.network.routers1.msg_count.Control::2 1730 414system.ruby.network.routers1.msg_count.Data::2 1726 415system.ruby.network.routers1.msg_count.Response_Data::4 1730 416system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 417system.ruby.network.routers1.msg_bytes.Control::2 13840 418system.ruby.network.routers1.msg_bytes.Data::2 124272 419system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 420system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 421system.ruby.network.routers2.percent_links_utilized 8.058950 422system.ruby.network.routers2.msg_count.Control::2 1730 423system.ruby.network.routers2.msg_count.Data::2 1726 424system.ruby.network.routers2.msg_count.Response_Data::4 1730 425system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 426system.ruby.network.routers2.msg_bytes.Control::2 13840 427system.ruby.network.routers2.msg_bytes.Data::2 124272 428system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 429system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 430system.ruby.network.msg_count.Control 5190 431system.ruby.network.msg_count.Data 5178 432system.ruby.network.msg_count.Response_Data 5190 433system.ruby.network.msg_count.Writeback_Control 5178 434system.ruby.network.msg_byte.Control 41520 435system.ruby.network.msg_byte.Data 372816 436system.ruby.network.msg_byte.Response_Data 373680 437system.ruby.network.msg_byte.Writeback_Control 41424 438system.ruby.network.routers0.throttle0.link_utilization 8.066412 439system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 440system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 441system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 442system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 443system.ruby.network.routers0.throttle1.link_utilization 8.051488 444system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 445system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 446system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 447system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 448system.ruby.network.routers1.throttle0.link_utilization 8.051488 449system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 450system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 451system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 452system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 453system.ruby.network.routers1.throttle1.link_utilization 8.066412 454system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 455system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 456system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 457system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 458system.ruby.network.routers2.throttle0.link_utilization 8.066412 459system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 460system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 461system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 462system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 463system.ruby.network.routers2.throttle1.link_utilization 8.051488 464system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 465system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 466system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 467system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272 468system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 469system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 470system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1 471system.ruby.delayVCHist.vnet_1 \| 1730 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_1 472system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1 473system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 474system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 475system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 476system.ruby.delayVCHist.vnet_2 \| 1726 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_2 477system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 478system.ruby.LD.latency_hist::bucket_size 64 479system.ruby.LD.latency_hist::max_bucket 639 480system.ruby.LD.latency_hist::samples 1183 481system.ruby.LD.latency_hist::mean 31.638208 482system.ruby.LD.latency_hist::gmean 10.419015 483system.ruby.LD.latency_hist::stdev 35.065266 484system.ruby.LD.latency_hist \| 1085 91.72% 91.72% \| 74 6.26% 97.97% \| 18 1.52% 99.49% \| 2 0.17% 99.66% \| 3 0.25% 99.92% \| 1 0.08% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 485system.ruby.LD.latency_hist::total 1183 486system.ruby.LD.hit_latency_hist::bucket_size 1 487system.ruby.LD.hit_latency_hist::max_bucket 9 488system.ruby.LD.hit_latency_hist::samples 456 489system.ruby.LD.hit_latency_hist::mean 1 490system.ruby.LD.hit_latency_hist::gmean 1 491system.ruby.LD.hit_latency_hist \| 0 0.00% 0.00% \| 456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 492system.ruby.LD.hit_latency_hist::total 456 493system.ruby.LD.miss_latency_hist::bucket_size 64 494system.ruby.LD.miss_latency_hist::max_bucket 639 495system.ruby.LD.miss_latency_hist::samples 727 496system.ruby.LD.miss_latency_hist::mean 50.855571 497system.ruby.LD.miss_latency_hist::gmean 45.315147 498system.ruby.LD.miss_latency_hist::stdev 32.287061 499system.ruby.LD.miss_latency_hist \| 629 86.52% 86.52% \| 74 10.18% 96.70% \| 18 2.48% 99.17% \| 2 0.28% 99.45% \| 3 0.41% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 500system.ruby.LD.miss_latency_hist::total 727 501system.ruby.ST.latency_hist::bucket_size 32 502system.ruby.ST.latency_hist::max_bucket 319 503system.ruby.ST.latency_hist::samples 865 504system.ruby.ST.latency_hist::mean 16.483237 505system.ruby.ST.latency_hist::gmean 3.324735 506system.ruby.ST.latency_hist::stdev 28.016571 507system.ruby.ST.latency_hist \| 592 68.44% 68.44% \| 244 28.21% 96.65% \| 18 2.08% 98.73% \| 2 0.23% 98.96% \| 5 0.58% 99.54% \| 2 0.23% 99.77% \| 1 0.12% 99.88% \| 0 0.00% 99.88% \| 1 0.12% 100.00% \| 0 0.00% 100.00% 508system.ruby.ST.latency_hist::total 865 509system.ruby.ST.hit_latency_hist::bucket_size 1 510system.ruby.ST.hit_latency_hist::max_bucket 9 511system.ruby.ST.hit_latency_hist::samples 592 512system.ruby.ST.hit_latency_hist::mean 1 513system.ruby.ST.hit_latency_hist::gmean 1 514system.ruby.ST.hit_latency_hist \| 0 0.00% 0.00% \| 592 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 515system.ruby.ST.hit_latency_hist::total 592 516system.ruby.ST.miss_latency_hist::bucket_size 32 517system.ruby.ST.miss_latency_hist::max_bucket 319 518system.ruby.ST.miss_latency_hist::samples 273 519system.ruby.ST.miss_latency_hist::mean 50.058608 520system.ruby.ST.miss_latency_hist::gmean 44.997273 521system.ruby.ST.miss_latency_hist::stdev 28.984216 522system.ruby.ST.miss_latency_hist \| 0 0.00% 0.00% \| 244 89.38% 89.38% \| 18 6.59% 95.97% \| 2 0.73% 96.70% \| 5 1.83% 98.53% \| 2 0.73% 99.27% \| 1 0.37% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% 523system.ruby.ST.miss_latency_hist::total 273 524system.ruby.IFETCH.latency_hist::bucket_size 64 525system.ruby.IFETCH.latency_hist::max_bucket 639 526system.ruby.IFETCH.latency_hist::samples 6400 527system.ruby.IFETCH.latency_hist::mean 7.355625 528system.ruby.IFETCH.latency_hist::gmean 1.565715 529system.ruby.IFETCH.latency_hist::stdev 21.264557 530system.ruby.IFETCH.latency_hist \| 6288 98.25% 98.25% \| 90 1.41% 99.66% \| 13 0.20% 99.86% \| 4 0.06% 99.92% \| 2 0.03% 99.95% \| 2 0.03% 99.98% \| 0 0.00% 99.98% \| 1 0.02% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 531system.ruby.IFETCH.latency_hist::total 6400 532system.ruby.IFETCH.hit_latency_hist::bucket_size 1 533system.ruby.IFETCH.hit_latency_hist::max_bucket 9 534system.ruby.IFETCH.hit_latency_hist::samples 5670 535system.ruby.IFETCH.hit_latency_hist::mean 1 536system.ruby.IFETCH.hit_latency_hist::gmean 1 537system.ruby.IFETCH.hit_latency_hist \| 0 0.00% 0.00% \| 5670 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 538system.ruby.IFETCH.hit_latency_hist::total 5670 539system.ruby.IFETCH.miss_latency_hist::bucket_size 64 540system.ruby.IFETCH.miss_latency_hist::max_bucket 639 541system.ruby.IFETCH.miss_latency_hist::samples 730 542system.ruby.IFETCH.miss_latency_hist::mean 56.720548 543system.ruby.IFETCH.miss_latency_hist::gmean 50.941265 544system.ruby.IFETCH.miss_latency_hist::stdev 34.853032 545system.ruby.IFETCH.miss_latency_hist \| 618 84.66% 84.66% \| 90 12.33% 96.99% \| 13 1.78% 98.77% \| 4 0.55% 99.32% \| 2 0.27% 99.59% \| 2 0.27% 99.86% \| 0 0.00% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 546system.ruby.IFETCH.miss_latency_hist::total 730 547system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 548system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 549system.ruby.Directory.miss_mach_latency_hist::samples 1730 550system.ruby.Directory.miss_mach_latency_hist::mean 53.204624 551system.ruby.Directory.miss_mach_latency_hist::gmean 47.556283 552system.ruby.Directory.miss_mach_latency_hist::stdev 33.032605 553system.ruby.Directory.miss_mach_latency_hist \| 1491 86.18% 86.18% \| 184 10.64% 96.82% \| 38 2.20% 99.02% \| 7 0.40% 99.42% \| 6 0.35% 99.77% \| 3 0.17% 99.94% \| 0 0.00% 99.94% \| 1 0.06% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 554system.ruby.Directory.miss_mach_latency_hist::total 1730 555system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 556system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 557system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 558system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 559system.ruby.Directory.miss_latency_hist.issue_to_initial_request \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 560system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 561system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 562system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 563system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 564system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 565system.ruby.Directory.miss_latency_hist.initial_to_forward \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 566system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 567system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 568system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 569system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 570system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 571system.ruby.Directory.miss_latency_hist.forward_to_first_response \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 572system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 573system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 574system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 575system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 576system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 577system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 578system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 579system.ruby.Directory.miss_latency_hist.first_response_to_completion \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% 580system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 581system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 582system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 583system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 584system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 50.855571 585system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 45.315147 586system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.287061 587system.ruby.LD.Directory.miss_type_mach_latency_hist \| 629 86.52% 86.52% \| 74 10.18% 96.70% \| 18 2.48% 99.17% \| 2 0.28% 99.45% \| 3 0.41% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 588system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 589system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 590system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 591system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 592system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 50.058608 593system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 44.997273 594system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 28.984216 595system.ruby.ST.Directory.miss_type_mach_latency_hist \| 0 0.00% 0.00% \| 244 89.38% 89.38% \| 18 6.59% 95.97% \| 2 0.73% 96.70% \| 5 1.83% 98.53% \| 2 0.73% 99.27% \| 1 0.37% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% 596system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 599system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 600system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.720548 601system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.941265 602system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.853032 603system.ruby.IFETCH.Directory.miss_type_mach_latency_hist \| 618 84.66% 84.66% \| 90 12.33% 96.99% \| 13 1.78% 98.77% \| 4 0.55% 99.32% \| 2 0.27% 99.59% \| 2 0.27% 99.86% \| 0 0.00% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 604system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 605system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% 606system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% 607system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% 608system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% 609system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% 610system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% 611system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% 612system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% 613system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% 614system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% 615system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% 616system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00% 617system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00% 618system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00% 619system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00% 620system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% 621system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% 622system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00% 623system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00% 624system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% 625system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% 626system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% 627system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% 628system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% 629 630---------- End Simulation Statistics ----------