Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt

stats.txt (10526:0068ad93a67e)	stats.txt (10628:c9b7e0c69f88)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000124 # Number of seconds simulated 4sim_ticks 123564 # Number of ticks simulated 5final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000124 # Number of seconds simulated 4sim_ticks 123564 # Number of ticks simulated 5final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks
7host_inst_rate 34581 # Simulator instruction rate (inst/s) 8host_op_rate 34578 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 668563 # Simulator tick rate (ticks/s) 10host_mem_usage 436724 # Number of bytes of host memory used 11host_seconds 0.19 # Real time elapsed on the host	7host_inst_rate 69668 # Simulator instruction rate (inst/s) 8host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1346306 # Simulator tick rate (ticks/s) 10host_mem_usage 450680 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host
12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 896053867 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 896053867 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 893982066 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 893982066 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790035933 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 1790035933 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1730 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1726 # Number of write requests accepted 32system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 54016 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 57536 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 844 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 44 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 65 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 20 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 80 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 84 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 44 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 130 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 23 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 53 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 15 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 277 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 123476 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 55 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 258 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 429.147287 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 269.046347 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 361.589640 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 63 24.42% 24.42% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 51 19.77% 44.19% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 24 9.30% 53.49% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 27 10.47% 63.95% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 14 5.43% 69.38% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 11 4.26% 73.64% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 12 4.65% 78.29% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 14 5.43% 83.72% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 42 16.28% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 258 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 15.927273 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 15.760356 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 2.949291 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::14-15 29 52.73% 52.73% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::36-37 1 1.82% 100.00% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes 210system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads 211system.mem_ctrls.wrPerTurnAround::mean 16.345455 # Writes before turning the bus around for reads 212system.mem_ctrls.wrPerTurnAround::gmean 16.329469 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::stdev 0.750757 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::16 44 80.00% 80.00% # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::17 4 7.27% 87.27% # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::18 6 10.91% 98.18% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads 219system.mem_ctrls.totQLat 10464 # Total ticks spent queuing 220system.mem_ctrls.totMemAccLat 27298 # Total ticks spent from burst creation until serviced by the DRAM 221system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers 222system.mem_ctrls.avgQLat 11.81 # Average queueing delay per DRAM burst 223system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 224system.mem_ctrls.avgMemAccLat 30.81 # Average memory access latency per DRAM burst 225system.mem_ctrls.avgRdBW 458.90 # Average DRAM read bandwidth in MiByte/s 226system.mem_ctrls.avgWrBW 465.64 # Average achieved write bandwidth in MiByte/s 227system.mem_ctrls.avgRdBWSys 896.05 # Average system read bandwidth in MiByte/s 228system.mem_ctrls.avgWrBWSys 893.98 # Average system write bandwidth in MiByte/s 229system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 230system.mem_ctrls.busUtil 7.22 # Data bus utilization in percentage 231system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads 232system.mem_ctrls.busUtilWrite 3.64 # Data bus utilization in percentage for writes 233system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 234system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing 235system.mem_ctrls.readRowHits 665 # Number of row buffer hits during reads 236system.mem_ctrls.writeRowHits 854 # Number of row buffer hits during writes 237system.mem_ctrls.readRowHitRate 75.06 # Row buffer hit rate for reads 238system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes 239system.mem_ctrls.avgGap 35.73 # Average gap between requests 240system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined	12sim_insts 6390 # Number of instructions simulated 13sim_ops 6390 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks 16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory 17system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory 18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory 19system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory 20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory 21system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory 22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory 23system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory 24system.mem_ctrls.bw_read::ruby.dir_cntrl0 896053867 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrls.bw_read::total 896053867 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_write::ruby.dir_cntrl0 893982066 # Write bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::total 893982066 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790035933 # Total bandwidth to/from this memory (bytes/s) 29system.mem_ctrls.bw_total::total 1790035933 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.readReqs 1730 # Number of read requests accepted 31system.mem_ctrls.writeReqs 1726 # Number of write requests accepted 32system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue 33system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue 34system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM 35system.mem_ctrls.bytesReadWrQ 54016 # Total number of bytes read from write queue 36system.mem_ctrls.bytesWritten 57536 # Total number of bytes written to DRAM 37system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side 38system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side 39system.mem_ctrls.servicedByWrQ 844 # Number of DRAM read bursts serviced by the write queue 40system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one 41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 42system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts 43system.mem_ctrls.perBankRdBursts::1 44 # Per bank write bursts 44system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::3 65 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts 50system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts 51system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts 52system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::12 20 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::14 80 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts 58system.mem_ctrls.perBankWrBursts::0 84 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::1 44 # Per bank write bursts 60system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::4 130 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::5 23 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts 66system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts 67system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts 68system.mem_ctrls.perBankWrBursts::10 53 # Per bank write bursts 69system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts 70system.mem_ctrls.perBankWrBursts::12 15 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::13 277 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts 74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry 76system.mem_ctrls.totGap 123476 # Total gap between requests 77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2) 84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) 91system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see 92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see 101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see 102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see 103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see 104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see 105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see 107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see 108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see 110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see 111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see 112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see 113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see 114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see 116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see 117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see 118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see 119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see 120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see 121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see 122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see 123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see 124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see 125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see 126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see 127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see 128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see 129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see 130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see 139system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see 143system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see 144system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see 145system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see 146system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::30 55 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see 166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see 168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see 169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see 170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see 171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see 172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see 173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see 174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see 175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see 176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see 177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see 178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see 179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see 187system.mem_ctrls.bytesPerActivate::samples 258 # Bytes accessed per row activation 188system.mem_ctrls.bytesPerActivate::mean 429.147287 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::gmean 269.046347 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::stdev 361.589640 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::0-127 63 24.42% 24.42% # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::128-255 51 19.77% 44.19% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::256-383 24 9.30% 53.49% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::384-511 27 10.47% 63.95% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::512-639 14 5.43% 69.38% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::640-767 11 4.26% 73.64% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::768-895 12 4.65% 78.29% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::896-1023 14 5.43% 83.72% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::1024-1151 42 16.28% 100.00% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::total 258 # Bytes accessed per row activation 201system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes 202system.mem_ctrls.rdPerTurnAround::mean 15.927273 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::gmean 15.760356 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::stdev 2.949291 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::14-15 29 52.73% 52.73% # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::36-37 1 1.82% 100.00% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes 210system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads 211system.mem_ctrls.wrPerTurnAround::mean 16.345455 # Writes before turning the bus around for reads 212system.mem_ctrls.wrPerTurnAround::gmean 16.329469 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::stdev 0.750757 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::16 44 80.00% 80.00% # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::17 4 7.27% 87.27% # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::18 6 10.91% 98.18% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads 219system.mem_ctrls.totQLat 10464 # Total ticks spent queuing 220system.mem_ctrls.totMemAccLat 27298 # Total ticks spent from burst creation until serviced by the DRAM 221system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers 222system.mem_ctrls.avgQLat 11.81 # Average queueing delay per DRAM burst 223system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst 224system.mem_ctrls.avgMemAccLat 30.81 # Average memory access latency per DRAM burst 225system.mem_ctrls.avgRdBW 458.90 # Average DRAM read bandwidth in MiByte/s 226system.mem_ctrls.avgWrBW 465.64 # Average achieved write bandwidth in MiByte/s 227system.mem_ctrls.avgRdBWSys 896.05 # Average system read bandwidth in MiByte/s 228system.mem_ctrls.avgWrBWSys 893.98 # Average system write bandwidth in MiByte/s 229system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 230system.mem_ctrls.busUtil 7.22 # Data bus utilization in percentage 231system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads 232system.mem_ctrls.busUtilWrite 3.64 # Data bus utilization in percentage for writes 233system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing 234system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing 235system.mem_ctrls.readRowHits 665 # Number of row buffer hits during reads 236system.mem_ctrls.writeRowHits 854 # Number of row buffer hits during writes 237system.mem_ctrls.readRowHitRate 75.06 # Row buffer hit rate for reads 238system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes 239system.mem_ctrls.avgGap 35.73 # Average gap between requests 240system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined
241system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states 242system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states 243system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states 244system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states 245system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states 246system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ) 247system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ) 248system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ) 249system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ) 250system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ) 251system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ) 252system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ) 253system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ) 254system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ) 255system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ) 256system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ) 257system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ) 258system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ) 259system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ) 260system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ) 261system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ) 262system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW) 263system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW) 264system.ruby.clk_domain.clock 1 # Clock period in ticks 265system.ruby.delayHist::bucket_size 1 # delay histogram for all message 266system.ruby.delayHist::max_bucket 9 # delay histogram for all message 267system.ruby.delayHist::samples 3456 # delay histogram for all message 268system.ruby.delayHist \| 3456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for all message 269system.ruby.delayHist::total 3456 # delay histogram for all message 270system.ruby.outstanding_req_hist::bucket_size 1 271system.ruby.outstanding_req_hist::max_bucket 9 272system.ruby.outstanding_req_hist::samples 8449 273system.ruby.outstanding_req_hist::mean 1 274system.ruby.outstanding_req_hist::gmean 1 275system.ruby.outstanding_req_hist \| 0 0.00% 0.00% \| 8449 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 276system.ruby.outstanding_req_hist::total 8449 277system.ruby.latency_hist::bucket_size 64 278system.ruby.latency_hist::max_bucket 639 279system.ruby.latency_hist::samples 8448 280system.ruby.latency_hist::mean 13.626420 281system.ruby.latency_hist::gmean 5.329740 282system.ruby.latency_hist::stdev 25.242996 283system.ruby.latency_hist \| 8195 97.01% 97.01% \| 199 2.36% 99.36% \| 43 0.51% 99.87% \| 2 0.02% 99.89% \| 5 0.06% 99.95% \| 4 0.05% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 284system.ruby.latency_hist::total 8448 285system.ruby.hit_latency_hist::bucket_size 1 286system.ruby.hit_latency_hist::max_bucket 9 287system.ruby.hit_latency_hist::samples 6718 288system.ruby.hit_latency_hist::mean 3 289system.ruby.hit_latency_hist::gmean 3.000000 290system.ruby.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 6718 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 291system.ruby.hit_latency_hist::total 6718 292system.ruby.miss_latency_hist::bucket_size 64 293system.ruby.miss_latency_hist::max_bucket 639 294system.ruby.miss_latency_hist::samples 1730 295system.ruby.miss_latency_hist::mean 54.891329 296system.ruby.miss_latency_hist::gmean 49.648144 297system.ruby.miss_latency_hist::stdev 31.153546 298system.ruby.miss_latency_hist \| 1477 85.38% 85.38% \| 199 11.50% 96.88% \| 43 2.49% 99.36% \| 2 0.12% 99.48% \| 5 0.29% 99.77% \| 4 0.23% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 299system.ruby.miss_latency_hist::total 1730 300system.ruby.Directory.incomplete_times 1729 301system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 302system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits 303system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses 304system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses	241system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) 242system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) 243system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) 244system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) 245system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) 246system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) 247system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) 248system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) 249system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) 250system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states 251system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states 252system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 255system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) 256system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) 257system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) 258system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) 259system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) 260system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) 261system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) 262system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) 263system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) 264system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states 265system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states 266system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
305system.cpu.clk_domain.clock 1 # Clock period in ticks	269system.cpu.clk_domain.clock 1 # Clock period in ticks
306system.ruby.network.routers0.percent_links_utilized 6.992328 307system.ruby.network.routers0.msg_count.Control::2 1730 308system.ruby.network.routers0.msg_count.Data::2 1726 309system.ruby.network.routers0.msg_count.Response_Data::4 1730 310system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 311system.ruby.network.routers0.msg_bytes.Control::2 13840 312system.ruby.network.routers0.msg_bytes.Data::2 124272 313system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 314system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 315system.ruby.network.routers1.percent_links_utilized 6.992328 316system.ruby.network.routers1.msg_count.Control::2 1730 317system.ruby.network.routers1.msg_count.Data::2 1726 318system.ruby.network.routers1.msg_count.Response_Data::4 1730 319system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 320system.ruby.network.routers1.msg_bytes.Control::2 13840 321system.ruby.network.routers1.msg_bytes.Data::2 124272 322system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 323system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 324system.ruby.network.routers2.percent_links_utilized 6.992328 325system.ruby.network.routers2.msg_count.Control::2 1730 326system.ruby.network.routers2.msg_count.Data::2 1726 327system.ruby.network.routers2.msg_count.Response_Data::4 1730 328system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 329system.ruby.network.routers2.msg_bytes.Control::2 13840 330system.ruby.network.routers2.msg_bytes.Data::2 124272 331system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 332system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 333system.ruby.network.msg_count.Control 5190 334system.ruby.network.msg_count.Data 5178 335system.ruby.network.msg_count.Response_Data 5190 336system.ruby.network.msg_count.Writeback_Control 5178 337system.ruby.network.msg_byte.Control 41520 338system.ruby.network.msg_byte.Data 372816 339system.ruby.network.msg_byte.Response_Data 373680 340system.ruby.network.msg_byte.Writeback_Control 41424
341system.cpu.dtb.fetch_hits 0 # ITB hits 342system.cpu.dtb.fetch_misses 0 # ITB misses 343system.cpu.dtb.fetch_acv 0 # ITB acv 344system.cpu.dtb.fetch_accesses 0 # ITB accesses 345system.cpu.dtb.read_hits 1183 # DTB read hits 346system.cpu.dtb.read_misses 7 # DTB read misses 347system.cpu.dtb.read_acv 0 # DTB read access violations 348system.cpu.dtb.read_accesses 1190 # DTB read accesses 349system.cpu.dtb.write_hits 865 # DTB write hits 350system.cpu.dtb.write_misses 3 # DTB write misses 351system.cpu.dtb.write_acv 0 # DTB write access violations 352system.cpu.dtb.write_accesses 868 # DTB write accesses 353system.cpu.dtb.data_hits 2048 # DTB hits 354system.cpu.dtb.data_misses 10 # DTB misses 355system.cpu.dtb.data_acv 0 # DTB access violations 356system.cpu.dtb.data_accesses 2058 # DTB accesses 357system.cpu.itb.fetch_hits 6401 # ITB hits 358system.cpu.itb.fetch_misses 17 # ITB misses 359system.cpu.itb.fetch_acv 0 # ITB acv 360system.cpu.itb.fetch_accesses 6418 # ITB accesses 361system.cpu.itb.read_hits 0 # DTB read hits 362system.cpu.itb.read_misses 0 # DTB read misses 363system.cpu.itb.read_acv 0 # DTB read access violations 364system.cpu.itb.read_accesses 0 # DTB read accesses 365system.cpu.itb.write_hits 0 # DTB write hits 366system.cpu.itb.write_misses 0 # DTB write misses 367system.cpu.itb.write_acv 0 # DTB write access violations 368system.cpu.itb.write_accesses 0 # DTB write accesses 369system.cpu.itb.data_hits 0 # DTB hits 370system.cpu.itb.data_misses 0 # DTB misses 371system.cpu.itb.data_acv 0 # DTB access violations 372system.cpu.itb.data_accesses 0 # DTB accesses 373system.cpu.workload.num_syscalls 17 # Number of system calls 374system.cpu.numCycles 123564 # number of cpu cycles simulated 375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 377system.cpu.committedInsts 6390 # Number of instructions committed 378system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 379system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 380system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 381system.cpu.num_func_calls 251 # number of times a function call or return occured 382system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 383system.cpu.num_int_insts 6317 # number of integer instructions 384system.cpu.num_fp_insts 10 # number of float instructions 385system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 386system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 387system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 388system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 389system.cpu.num_mem_refs 2058 # number of memory refs 390system.cpu.num_load_insts 1190 # Number of load instructions 391system.cpu.num_store_insts 868 # Number of store instructions 392system.cpu.num_idle_cycles 0 # Number of idle cycles 393system.cpu.num_busy_cycles 123564 # Number of busy cycles 394system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 395system.cpu.idle_fraction 0 # Percentage of idle cycles 396system.cpu.Branches 1050 # Number of branches fetched 397system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 398system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 399system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 400system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 401system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction 402system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction 403system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction 404system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction 405system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction 406system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction 407system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction 408system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction 409system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction 410system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction 411system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction 412system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction 413system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction 414system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction 415system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction 416system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction 417system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction 418system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction 419system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction 420system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction 421system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction 422system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction 423system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction 424system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction 425system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 426system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 427system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 428system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 429system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 430system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 431system.cpu.op_class::total 6400 # Class of executed instruction	270system.cpu.dtb.fetch_hits 0 # ITB hits 271system.cpu.dtb.fetch_misses 0 # ITB misses 272system.cpu.dtb.fetch_acv 0 # ITB acv 273system.cpu.dtb.fetch_accesses 0 # ITB accesses 274system.cpu.dtb.read_hits 1183 # DTB read hits 275system.cpu.dtb.read_misses 7 # DTB read misses 276system.cpu.dtb.read_acv 0 # DTB read access violations 277system.cpu.dtb.read_accesses 1190 # DTB read accesses 278system.cpu.dtb.write_hits 865 # DTB write hits 279system.cpu.dtb.write_misses 3 # DTB write misses 280system.cpu.dtb.write_acv 0 # DTB write access violations 281system.cpu.dtb.write_accesses 868 # DTB write accesses 282system.cpu.dtb.data_hits 2048 # DTB hits 283system.cpu.dtb.data_misses 10 # DTB misses 284system.cpu.dtb.data_acv 0 # DTB access violations 285system.cpu.dtb.data_accesses 2058 # DTB accesses 286system.cpu.itb.fetch_hits 6401 # ITB hits 287system.cpu.itb.fetch_misses 17 # ITB misses 288system.cpu.itb.fetch_acv 0 # ITB acv 289system.cpu.itb.fetch_accesses 6418 # ITB accesses 290system.cpu.itb.read_hits 0 # DTB read hits 291system.cpu.itb.read_misses 0 # DTB read misses 292system.cpu.itb.read_acv 0 # DTB read access violations 293system.cpu.itb.read_accesses 0 # DTB read accesses 294system.cpu.itb.write_hits 0 # DTB write hits 295system.cpu.itb.write_misses 0 # DTB write misses 296system.cpu.itb.write_acv 0 # DTB write access violations 297system.cpu.itb.write_accesses 0 # DTB write accesses 298system.cpu.itb.data_hits 0 # DTB hits 299system.cpu.itb.data_misses 0 # DTB misses 300system.cpu.itb.data_acv 0 # DTB access violations 301system.cpu.itb.data_accesses 0 # DTB accesses 302system.cpu.workload.num_syscalls 17 # Number of system calls 303system.cpu.numCycles 123564 # number of cpu cycles simulated 304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 306system.cpu.committedInsts 6390 # Number of instructions committed 307system.cpu.committedOps 6390 # Number of ops (including micro ops) committed 308system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses 309system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 310system.cpu.num_func_calls 251 # number of times a function call or return occured 311system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls 312system.cpu.num_int_insts 6317 # number of integer instructions 313system.cpu.num_fp_insts 10 # number of float instructions 314system.cpu.num_int_register_reads 8285 # number of times the integer registers were read 315system.cpu.num_int_register_writes 4568 # number of times the integer registers were written 316system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 317system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 318system.cpu.num_mem_refs 2058 # number of memory refs 319system.cpu.num_load_insts 1190 # Number of load instructions 320system.cpu.num_store_insts 868 # Number of store instructions 321system.cpu.num_idle_cycles 0 # Number of idle cycles 322system.cpu.num_busy_cycles 123564 # Number of busy cycles 323system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 324system.cpu.idle_fraction 0 # Percentage of idle cycles 325system.cpu.Branches 1050 # Number of branches fetched 326system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction 327system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction 328system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction 329system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction 330system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction 331system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction 332system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction 333system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction 334system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction 335system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction 336system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction 337system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction 338system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction 339system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction 340system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction 341system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction 342system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction 343system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction 344system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction 345system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction 346system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction 347system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction 348system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction 349system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction 350system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction 351system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction 352system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction 353system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction 354system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction 355system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction 356system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction 357system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction 358system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 359system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 360system.cpu.op_class::total 6400 # Class of executed instruction
	361system.ruby.clk_domain.clock 1 # Clock period in ticks 362system.ruby.delayHist::bucket_size 1 # delay histogram for all message 363system.ruby.delayHist::max_bucket 9 # delay histogram for all message 364system.ruby.delayHist::samples 3456 # delay histogram for all message 365system.ruby.delayHist \| 3456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for all message 366system.ruby.delayHist::total 3456 # delay histogram for all message 367system.ruby.outstanding_req_hist::bucket_size 1 368system.ruby.outstanding_req_hist::max_bucket 9 369system.ruby.outstanding_req_hist::samples 8449 370system.ruby.outstanding_req_hist::mean 1 371system.ruby.outstanding_req_hist::gmean 1 372system.ruby.outstanding_req_hist \| 0 0.00% 0.00% \| 8449 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 373system.ruby.outstanding_req_hist::total 8449 374system.ruby.latency_hist::bucket_size 64 375system.ruby.latency_hist::max_bucket 639 376system.ruby.latency_hist::samples 8448 377system.ruby.latency_hist::mean 13.626420 378system.ruby.latency_hist::gmean 5.329740 379system.ruby.latency_hist::stdev 25.242996 380system.ruby.latency_hist \| 8195 97.01% 97.01% \| 199 2.36% 99.36% \| 43 0.51% 99.87% \| 2 0.02% 99.89% \| 5 0.06% 99.95% \| 4 0.05% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 381system.ruby.latency_hist::total 8448 382system.ruby.hit_latency_hist::bucket_size 1 383system.ruby.hit_latency_hist::max_bucket 9 384system.ruby.hit_latency_hist::samples 6718 385system.ruby.hit_latency_hist::mean 3 386system.ruby.hit_latency_hist::gmean 3.000000 387system.ruby.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 6718 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 388system.ruby.hit_latency_hist::total 6718 389system.ruby.miss_latency_hist::bucket_size 64 390system.ruby.miss_latency_hist::max_bucket 639 391system.ruby.miss_latency_hist::samples 1730 392system.ruby.miss_latency_hist::mean 54.891329 393system.ruby.miss_latency_hist::gmean 49.648144 394system.ruby.miss_latency_hist::stdev 31.153546 395system.ruby.miss_latency_hist \| 1477 85.38% 85.38% \| 199 11.50% 96.88% \| 43 2.49% 99.36% \| 2 0.12% 99.48% \| 5 0.29% 99.77% \| 4 0.23% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 396system.ruby.miss_latency_hist::total 1730 397system.ruby.Directory.incomplete_times 1729 398system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits 399system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses 400system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses 401system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks 402system.ruby.network.routers0.percent_links_utilized 6.992328 403system.ruby.network.routers0.msg_count.Control::2 1730 404system.ruby.network.routers0.msg_count.Data::2 1726 405system.ruby.network.routers0.msg_count.Response_Data::4 1730 406system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 407system.ruby.network.routers0.msg_bytes.Control::2 13840 408system.ruby.network.routers0.msg_bytes.Data::2 124272 409system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 410system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 411system.ruby.network.routers1.percent_links_utilized 6.992328 412system.ruby.network.routers1.msg_count.Control::2 1730 413system.ruby.network.routers1.msg_count.Data::2 1726 414system.ruby.network.routers1.msg_count.Response_Data::4 1730 415system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 416system.ruby.network.routers1.msg_bytes.Control::2 13840 417system.ruby.network.routers1.msg_bytes.Data::2 124272 418system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 419system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 420system.ruby.network.routers2.percent_links_utilized 6.992328 421system.ruby.network.routers2.msg_count.Control::2 1730 422system.ruby.network.routers2.msg_count.Data::2 1726 423system.ruby.network.routers2.msg_count.Response_Data::4 1730 424system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 425system.ruby.network.routers2.msg_bytes.Control::2 13840 426system.ruby.network.routers2.msg_bytes.Data::2 124272 427system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 428system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 429system.ruby.network.msg_count.Control 5190 430system.ruby.network.msg_count.Data 5178 431system.ruby.network.msg_count.Response_Data 5190 432system.ruby.network.msg_count.Writeback_Control 5178 433system.ruby.network.msg_byte.Control 41520 434system.ruby.network.msg_byte.Data 372816 435system.ruby.network.msg_byte.Response_Data 373680 436system.ruby.network.msg_byte.Writeback_Control 41424
432system.ruby.network.routers0.throttle0.link_utilization 6.998802 433system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 434system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 435system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 436system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 437system.ruby.network.routers0.throttle1.link_utilization 6.985853 438system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 439system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 440system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 441system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 442system.ruby.network.routers1.throttle0.link_utilization 6.985853 443system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 444system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 445system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 446system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 447system.ruby.network.routers1.throttle1.link_utilization 6.998802 448system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 449system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 450system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 451system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 452system.ruby.network.routers2.throttle0.link_utilization 6.998802 453system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 454system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 455system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 456system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 457system.ruby.network.routers2.throttle1.link_utilization 6.985853 458system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 459system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 460system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 461system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272 462system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 463system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 464system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1 465system.ruby.delayVCHist.vnet_1 \| 1730 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_1 466system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1 467system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 468system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 469system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 470system.ruby.delayVCHist.vnet_2 \| 1726 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_2 471system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 472system.ruby.LD.latency_hist::bucket_size 64 473system.ruby.LD.latency_hist::max_bucket 639 474system.ruby.LD.latency_hist::samples 1183 475system.ruby.LD.latency_hist::mean 33.711750 476system.ruby.LD.latency_hist::gmean 16.462445 477system.ruby.LD.latency_hist::stdev 33.973523 478system.ruby.LD.latency_hist \| 1077 91.04% 91.04% \| 86 7.27% 98.31% \| 15 1.27% 99.58% \| 2 0.17% 99.75% \| 2 0.17% 99.92% \| 1 0.08% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 479system.ruby.LD.latency_hist::total 1183 480system.ruby.LD.hit_latency_hist::bucket_size 1 481system.ruby.LD.hit_latency_hist::max_bucket 9 482system.ruby.LD.hit_latency_hist::samples 456 483system.ruby.LD.hit_latency_hist::mean 3 484system.ruby.LD.hit_latency_hist::gmean 3.000000 485system.ruby.LD.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 486system.ruby.LD.hit_latency_hist::total 456 487system.ruby.LD.miss_latency_hist::bucket_size 64 488system.ruby.LD.miss_latency_hist::max_bucket 639 489system.ruby.LD.miss_latency_hist::samples 727 490system.ruby.LD.miss_latency_hist::mean 52.975241 491system.ruby.LD.miss_latency_hist::gmean 47.891138 492system.ruby.LD.miss_latency_hist::stdev 30.251097 493system.ruby.LD.miss_latency_hist \| 621 85.42% 85.42% \| 86 11.83% 97.25% \| 15 2.06% 99.31% \| 2 0.28% 99.59% \| 2 0.28% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 494system.ruby.LD.miss_latency_hist::total 727 495system.ruby.ST.latency_hist::bucket_size 64 496system.ruby.ST.latency_hist::max_bucket 639 497system.ruby.ST.latency_hist::samples 865 498system.ruby.ST.latency_hist::mean 18.557225 499system.ruby.ST.latency_hist::gmean 7.162336 500system.ruby.ST.latency_hist::stdev 28.547301 501system.ruby.ST.latency_hist \| 834 96.42% 96.42% \| 21 2.43% 98.84% \| 9 1.04% 99.88% \| 0 0.00% 99.88% \| 0 0.00% 99.88% \| 1 0.12% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 502system.ruby.ST.latency_hist::total 865 503system.ruby.ST.hit_latency_hist::bucket_size 1 504system.ruby.ST.hit_latency_hist::max_bucket 9 505system.ruby.ST.hit_latency_hist::samples 592 506system.ruby.ST.hit_latency_hist::mean 3 507system.ruby.ST.hit_latency_hist::gmean 3.000000 508system.ruby.ST.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 592 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 509system.ruby.ST.hit_latency_hist::total 592 510system.ruby.ST.miss_latency_hist::bucket_size 64 511system.ruby.ST.miss_latency_hist::max_bucket 639 512system.ruby.ST.miss_latency_hist::samples 273 513system.ruby.ST.miss_latency_hist::mean 52.293040 514system.ruby.ST.miss_latency_hist::gmean 47.271858 515system.ruby.ST.miss_latency_hist::stdev 30.324989 516system.ruby.ST.miss_latency_hist \| 242 88.64% 88.64% \| 21 7.69% 96.34% \| 9 3.30% 99.63% \| 0 0.00% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 517system.ruby.ST.miss_latency_hist::total 273 518system.ruby.IFETCH.latency_hist::bucket_size 64 519system.ruby.IFETCH.latency_hist::max_bucket 639 520system.ruby.IFETCH.latency_hist::samples 6400 521system.ruby.IFETCH.latency_hist::mean 9.247344 522system.ruby.IFETCH.latency_hist::gmean 4.157427 523system.ruby.IFETCH.latency_hist::stdev 20.515003 524system.ruby.IFETCH.latency_hist \| 6284 98.19% 98.19% \| 92 1.44% 99.63% \| 19 0.30% 99.92% \| 0 0.00% 99.92% \| 3 0.05% 99.97% \| 2 0.03% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 525system.ruby.IFETCH.latency_hist::total 6400 526system.ruby.IFETCH.hit_latency_hist::bucket_size 1 527system.ruby.IFETCH.hit_latency_hist::max_bucket 9 528system.ruby.IFETCH.hit_latency_hist::samples 5670 529system.ruby.IFETCH.hit_latency_hist::mean 3 530system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 531system.ruby.IFETCH.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 5670 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 532system.ruby.IFETCH.hit_latency_hist::total 5670 533system.ruby.IFETCH.miss_latency_hist::bucket_size 64 534system.ruby.IFETCH.miss_latency_hist::max_bucket 639 535system.ruby.IFETCH.miss_latency_hist::samples 730 536system.ruby.IFETCH.miss_latency_hist::mean 57.771233 537system.ruby.IFETCH.miss_latency_hist::gmean 52.414605 538system.ruby.IFETCH.miss_latency_hist::stdev 32.138819 539system.ruby.IFETCH.miss_latency_hist \| 614 84.11% 84.11% \| 92 12.60% 96.71% \| 19 2.60% 99.32% \| 0 0.00% 99.32% \| 3 0.41% 99.73% \| 2 0.27% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 540system.ruby.IFETCH.miss_latency_hist::total 730 541system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 542system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 543system.ruby.Directory.miss_mach_latency_hist::samples 1730 544system.ruby.Directory.miss_mach_latency_hist::mean 54.891329 545system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144 546system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546 547system.ruby.Directory.miss_mach_latency_hist \| 1477 85.38% 85.38% \| 199 11.50% 96.88% \| 43 2.49% 99.36% \| 2 0.12% 99.48% \| 5 0.29% 99.77% \| 4 0.23% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 548system.ruby.Directory.miss_mach_latency_hist::total 1730 549system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 550system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 551system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 552system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 553system.ruby.Directory.miss_latency_hist.issue_to_initial_request \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 554system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 555system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 556system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 557system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 558system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 559system.ruby.Directory.miss_latency_hist.initial_to_forward \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 560system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 561system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 562system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 563system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 564system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 565system.ruby.Directory.miss_latency_hist.forward_to_first_response \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 566system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 567system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 568system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 569system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 570system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 571system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 572system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 573system.ruby.Directory.miss_latency_hist.first_response_to_completion \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% 574system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 575system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 576system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 577system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 578system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241 579system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138 580system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097 581system.ruby.LD.Directory.miss_type_mach_latency_hist \| 621 85.42% 85.42% \| 86 11.83% 97.25% \| 15 2.06% 99.31% \| 2 0.28% 99.59% \| 2 0.28% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 582system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 583system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 584system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 585system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 586system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040 587system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858 588system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989 589system.ruby.ST.Directory.miss_type_mach_latency_hist \| 242 88.64% 88.64% \| 21 7.69% 96.34% \| 9 3.30% 99.63% \| 0 0.00% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 590system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 591system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 592system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 593system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 594system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233 595system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 596system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist \| 614 84.11% 84.11% \| 92 12.60% 96.71% \| 19 2.60% 99.32% \| 0 0.00% 99.32% \| 3 0.41% 99.73% \| 2 0.27% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730	437system.ruby.network.routers0.throttle0.link_utilization 6.998802 438system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 439system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 440system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 441system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 442system.ruby.network.routers0.throttle1.link_utilization 6.985853 443system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 444system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 445system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 446system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 447system.ruby.network.routers1.throttle0.link_utilization 6.985853 448system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 449system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 450system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 451system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 452system.ruby.network.routers1.throttle1.link_utilization 6.998802 453system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 454system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 455system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 456system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 457system.ruby.network.routers2.throttle0.link_utilization 6.998802 458system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 459system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 460system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 461system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 462system.ruby.network.routers2.throttle1.link_utilization 6.985853 463system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 464system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 465system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 466system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272 467system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 468system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 469system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1 470system.ruby.delayVCHist.vnet_1 \| 1730 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_1 471system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1 472system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 473system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 474system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 475system.ruby.delayVCHist.vnet_2 \| 1726 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% # delay histogram for vnet_2 476system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 477system.ruby.LD.latency_hist::bucket_size 64 478system.ruby.LD.latency_hist::max_bucket 639 479system.ruby.LD.latency_hist::samples 1183 480system.ruby.LD.latency_hist::mean 33.711750 481system.ruby.LD.latency_hist::gmean 16.462445 482system.ruby.LD.latency_hist::stdev 33.973523 483system.ruby.LD.latency_hist \| 1077 91.04% 91.04% \| 86 7.27% 98.31% \| 15 1.27% 99.58% \| 2 0.17% 99.75% \| 2 0.17% 99.92% \| 1 0.08% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 484system.ruby.LD.latency_hist::total 1183 485system.ruby.LD.hit_latency_hist::bucket_size 1 486system.ruby.LD.hit_latency_hist::max_bucket 9 487system.ruby.LD.hit_latency_hist::samples 456 488system.ruby.LD.hit_latency_hist::mean 3 489system.ruby.LD.hit_latency_hist::gmean 3.000000 490system.ruby.LD.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 456 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 491system.ruby.LD.hit_latency_hist::total 456 492system.ruby.LD.miss_latency_hist::bucket_size 64 493system.ruby.LD.miss_latency_hist::max_bucket 639 494system.ruby.LD.miss_latency_hist::samples 727 495system.ruby.LD.miss_latency_hist::mean 52.975241 496system.ruby.LD.miss_latency_hist::gmean 47.891138 497system.ruby.LD.miss_latency_hist::stdev 30.251097 498system.ruby.LD.miss_latency_hist \| 621 85.42% 85.42% \| 86 11.83% 97.25% \| 15 2.06% 99.31% \| 2 0.28% 99.59% \| 2 0.28% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 499system.ruby.LD.miss_latency_hist::total 727 500system.ruby.ST.latency_hist::bucket_size 64 501system.ruby.ST.latency_hist::max_bucket 639 502system.ruby.ST.latency_hist::samples 865 503system.ruby.ST.latency_hist::mean 18.557225 504system.ruby.ST.latency_hist::gmean 7.162336 505system.ruby.ST.latency_hist::stdev 28.547301 506system.ruby.ST.latency_hist \| 834 96.42% 96.42% \| 21 2.43% 98.84% \| 9 1.04% 99.88% \| 0 0.00% 99.88% \| 0 0.00% 99.88% \| 1 0.12% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 507system.ruby.ST.latency_hist::total 865 508system.ruby.ST.hit_latency_hist::bucket_size 1 509system.ruby.ST.hit_latency_hist::max_bucket 9 510system.ruby.ST.hit_latency_hist::samples 592 511system.ruby.ST.hit_latency_hist::mean 3 512system.ruby.ST.hit_latency_hist::gmean 3.000000 513system.ruby.ST.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 592 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 514system.ruby.ST.hit_latency_hist::total 592 515system.ruby.ST.miss_latency_hist::bucket_size 64 516system.ruby.ST.miss_latency_hist::max_bucket 639 517system.ruby.ST.miss_latency_hist::samples 273 518system.ruby.ST.miss_latency_hist::mean 52.293040 519system.ruby.ST.miss_latency_hist::gmean 47.271858 520system.ruby.ST.miss_latency_hist::stdev 30.324989 521system.ruby.ST.miss_latency_hist \| 242 88.64% 88.64% \| 21 7.69% 96.34% \| 9 3.30% 99.63% \| 0 0.00% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 522system.ruby.ST.miss_latency_hist::total 273 523system.ruby.IFETCH.latency_hist::bucket_size 64 524system.ruby.IFETCH.latency_hist::max_bucket 639 525system.ruby.IFETCH.latency_hist::samples 6400 526system.ruby.IFETCH.latency_hist::mean 9.247344 527system.ruby.IFETCH.latency_hist::gmean 4.157427 528system.ruby.IFETCH.latency_hist::stdev 20.515003 529system.ruby.IFETCH.latency_hist \| 6284 98.19% 98.19% \| 92 1.44% 99.63% \| 19 0.30% 99.92% \| 0 0.00% 99.92% \| 3 0.05% 99.97% \| 2 0.03% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 530system.ruby.IFETCH.latency_hist::total 6400 531system.ruby.IFETCH.hit_latency_hist::bucket_size 1 532system.ruby.IFETCH.hit_latency_hist::max_bucket 9 533system.ruby.IFETCH.hit_latency_hist::samples 5670 534system.ruby.IFETCH.hit_latency_hist::mean 3 535system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 536system.ruby.IFETCH.hit_latency_hist \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 5670 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 537system.ruby.IFETCH.hit_latency_hist::total 5670 538system.ruby.IFETCH.miss_latency_hist::bucket_size 64 539system.ruby.IFETCH.miss_latency_hist::max_bucket 639 540system.ruby.IFETCH.miss_latency_hist::samples 730 541system.ruby.IFETCH.miss_latency_hist::mean 57.771233 542system.ruby.IFETCH.miss_latency_hist::gmean 52.414605 543system.ruby.IFETCH.miss_latency_hist::stdev 32.138819 544system.ruby.IFETCH.miss_latency_hist \| 614 84.11% 84.11% \| 92 12.60% 96.71% \| 19 2.60% 99.32% \| 0 0.00% 99.32% \| 3 0.41% 99.73% \| 2 0.27% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 545system.ruby.IFETCH.miss_latency_hist::total 730 546system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 547system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 548system.ruby.Directory.miss_mach_latency_hist::samples 1730 549system.ruby.Directory.miss_mach_latency_hist::mean 54.891329 550system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144 551system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546 552system.ruby.Directory.miss_mach_latency_hist \| 1477 85.38% 85.38% \| 199 11.50% 96.88% \| 43 2.49% 99.36% \| 2 0.12% 99.48% \| 5 0.29% 99.77% \| 4 0.23% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 553system.ruby.Directory.miss_mach_latency_hist::total 1730 554system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 555system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 556system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 557system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan 558system.ruby.Directory.miss_latency_hist.issue_to_initial_request \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 559system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1 560system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1 561system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9 562system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1 563system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan 564system.ruby.Directory.miss_latency_hist.initial_to_forward \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 565system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1 566system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1 567system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9 568system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1 569system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan 570system.ruby.Directory.miss_latency_hist.forward_to_first_response \| 1 100.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 571system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1 572system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 573system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 574system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 575system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 576system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 577system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan 578system.ruby.Directory.miss_latency_hist.first_response_to_completion \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 0 0.00% 0.00% \| 1 100.00% 100.00% 579system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 580system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 581system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 582system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 583system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241 584system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138 585system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097 586system.ruby.LD.Directory.miss_type_mach_latency_hist \| 621 85.42% 85.42% \| 86 11.83% 97.25% \| 15 2.06% 99.31% \| 2 0.28% 99.59% \| 2 0.28% 99.86% \| 1 0.14% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 587system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 588system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 589system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 590system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 591system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040 592system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858 593system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989 594system.ruby.ST.Directory.miss_type_mach_latency_hist \| 242 88.64% 88.64% \| 21 7.69% 96.34% \| 9 3.30% 99.63% \| 0 0.00% 99.63% \| 0 0.00% 99.63% \| 1 0.37% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 595system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 596system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 599system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233 600system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 601system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 602system.ruby.IFETCH.Directory.miss_type_mach_latency_hist \| 614 84.11% 84.11% \| 92 12.60% 96.71% \| 19 2.60% 99.32% \| 0 0.00% 99.32% \| 3 0.41% 99.73% \| 2 0.27% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% \| 0 0.00% 100.00% 603system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730
	604system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% 605system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% 606system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% 607system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% 608system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% 609system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% 610system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% 611system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00%
599system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% 600system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% 601system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% 602system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00% 603system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00% 604system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00% 605system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00% 606system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% 607system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% 608system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00% 609system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00% 610system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% 611system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% 612system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% 613system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% 614system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00%	612system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% 613system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% 614system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% 615system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00% 616system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00% 617system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00% 618system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00% 619system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% 620system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% 621system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00% 622system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00% 623system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% 624system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% 625system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% 626system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% 627system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00%
615system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% 616system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% 617system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% 618system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% 619system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% 620system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% 621system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% 622system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00%
623 624---------- End Simulation Statistics ----------	628 629---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000124 # Number of seconds simulated
4sim_ticks 123564 # Number of ticks simulated
5final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000 # Frequency of simulated ticks

7host_inst_rate 34581 # Simulator instruction rate (inst/s)
8host_op_rate 34578 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 668563 # Simulator tick rate (ticks/s)
10host_mem_usage 436724 # Number of bytes of host memory used
11host_seconds 0.19 # Real time elapsed on the host

7host_inst_rate 69668 # Simulator instruction rate (inst/s)
8host_op_rate 69633 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1346306 # Simulator tick rate (ticks/s)
10host_mem_usage 450680 # Number of bytes of host memory used
11host_seconds 0.09 # Real time elapsed on the host

12sim_insts 6390 # Number of instructions simulated
13sim_ops 6390 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1 # Clock period in ticks
16system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory
17system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory
18system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory
19system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory
20system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory
21system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory
22system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory
23system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory
24system.mem_ctrls.bw_read::ruby.dir_cntrl0 896053867 # Total read bandwidth from this memory (bytes/s)
25system.mem_ctrls.bw_read::total 896053867 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrls.bw_write::ruby.dir_cntrl0 893982066 # Write bandwidth from this memory (bytes/s)
27system.mem_ctrls.bw_write::total 893982066 # Write bandwidth from this memory (bytes/s)
28system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790035933 # Total bandwidth to/from this memory (bytes/s)
29system.mem_ctrls.bw_total::total 1790035933 # Total bandwidth to/from this memory (bytes/s)
30system.mem_ctrls.readReqs 1730 # Number of read requests accepted
31system.mem_ctrls.writeReqs 1726 # Number of write requests accepted
32system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue
33system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue
34system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM
35system.mem_ctrls.bytesReadWrQ 54016 # Total number of bytes read from write queue
36system.mem_ctrls.bytesWritten 57536 # Total number of bytes written to DRAM
37system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side
38system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side
39system.mem_ctrls.servicedByWrQ 844 # Number of DRAM read bursts serviced by the write queue
40system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one
41system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
42system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts
43system.mem_ctrls.perBankRdBursts::1 44 # Per bank write bursts
44system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts
45system.mem_ctrls.perBankRdBursts::3 65 # Per bank write bursts
46system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts
47system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts
48system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
49system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
50system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
51system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
52system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts
53system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts
54system.mem_ctrls.perBankRdBursts::12 20 # Per bank write bursts
55system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts
56system.mem_ctrls.perBankRdBursts::14 80 # Per bank write bursts
57system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts
58system.mem_ctrls.perBankWrBursts::0 84 # Per bank write bursts
59system.mem_ctrls.perBankWrBursts::1 44 # Per bank write bursts
60system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts
61system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts
62system.mem_ctrls.perBankWrBursts::4 130 # Per bank write bursts
63system.mem_ctrls.perBankWrBursts::5 23 # Per bank write bursts
64system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
65system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
66system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
67system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
68system.mem_ctrls.perBankWrBursts::10 53 # Per bank write bursts
69system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts
70system.mem_ctrls.perBankWrBursts::12 15 # Per bank write bursts
71system.mem_ctrls.perBankWrBursts::13 277 # Per bank write bursts
72system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
73system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts
74system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
75system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
76system.mem_ctrls.totGap 123476 # Total gap between requests
77system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
78system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
79system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
80system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
81system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
82system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
83system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2)
84system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
85system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
86system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
87system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
88system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
89system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
90system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2)
91system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see
92system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
93system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
94system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
95system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
96system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
97system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
98system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
99system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
100system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
101system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
102system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
103system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
104system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
105system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
106system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
107system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
108system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
109system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
110system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
111system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
112system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
113system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
114system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
115system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
116system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
117system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
118system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
119system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
120system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
121system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
122system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
123system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
124system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
125system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
126system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
127system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
128system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
129system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
130system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
131system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
132system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
133system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
134system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
135system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
136system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
137system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
138system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see
139system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see
140system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see
141system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
142system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see
143system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see
144system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see
145system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see
146system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see
147system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see
148system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see
149system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see
150system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see
151system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see
152system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see
153system.mem_ctrls.wrQLenPdf::30 55 # What write queue length does an incoming req see
154system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see
155system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
156system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
157system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
158system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
159system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
160system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
161system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
162system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
163system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
164system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
165system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
166system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
167system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
168system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
169system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
170system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
171system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
172system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
173system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
174system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
175system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
176system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
177system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
178system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
179system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
180system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
181system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
182system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
183system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
184system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
185system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
186system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
187system.mem_ctrls.bytesPerActivate::samples 258 # Bytes accessed per row activation
188system.mem_ctrls.bytesPerActivate::mean 429.147287 # Bytes accessed per row activation
189system.mem_ctrls.bytesPerActivate::gmean 269.046347 # Bytes accessed per row activation
190system.mem_ctrls.bytesPerActivate::stdev 361.589640 # Bytes accessed per row activation
191system.mem_ctrls.bytesPerActivate::0-127 63 24.42% 24.42% # Bytes accessed per row activation
192system.mem_ctrls.bytesPerActivate::128-255 51 19.77% 44.19% # Bytes accessed per row activation
193system.mem_ctrls.bytesPerActivate::256-383 24 9.30% 53.49% # Bytes accessed per row activation
194system.mem_ctrls.bytesPerActivate::384-511 27 10.47% 63.95% # Bytes accessed per row activation
195system.mem_ctrls.bytesPerActivate::512-639 14 5.43% 69.38% # Bytes accessed per row activation
196system.mem_ctrls.bytesPerActivate::640-767 11 4.26% 73.64% # Bytes accessed per row activation
197system.mem_ctrls.bytesPerActivate::768-895 12 4.65% 78.29% # Bytes accessed per row activation
198system.mem_ctrls.bytesPerActivate::896-1023 14 5.43% 83.72% # Bytes accessed per row activation
199system.mem_ctrls.bytesPerActivate::1024-1151 42 16.28% 100.00% # Bytes accessed per row activation
200system.mem_ctrls.bytesPerActivate::total 258 # Bytes accessed per row activation
201system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
202system.mem_ctrls.rdPerTurnAround::mean 15.927273 # Reads before turning the bus around for writes
203system.mem_ctrls.rdPerTurnAround::gmean 15.760356 # Reads before turning the bus around for writes
204system.mem_ctrls.rdPerTurnAround::stdev 2.949291 # Reads before turning the bus around for writes
205system.mem_ctrls.rdPerTurnAround::14-15 29 52.73% 52.73% # Reads before turning the bus around for writes
206system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes
207system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
208system.mem_ctrls.rdPerTurnAround::36-37 1 1.82% 100.00% # Reads before turning the bus around for writes
209system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
210system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
211system.mem_ctrls.wrPerTurnAround::mean 16.345455 # Writes before turning the bus around for reads
212system.mem_ctrls.wrPerTurnAround::gmean 16.329469 # Writes before turning the bus around for reads
213system.mem_ctrls.wrPerTurnAround::stdev 0.750757 # Writes before turning the bus around for reads
214system.mem_ctrls.wrPerTurnAround::16 44 80.00% 80.00% # Writes before turning the bus around for reads
215system.mem_ctrls.wrPerTurnAround::17 4 7.27% 87.27% # Writes before turning the bus around for reads
216system.mem_ctrls.wrPerTurnAround::18 6 10.91% 98.18% # Writes before turning the bus around for reads
217system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads
218system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
219system.mem_ctrls.totQLat 10464 # Total ticks spent queuing
220system.mem_ctrls.totMemAccLat 27298 # Total ticks spent from burst creation until serviced by the DRAM
221system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers
222system.mem_ctrls.avgQLat 11.81 # Average queueing delay per DRAM burst
223system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
224system.mem_ctrls.avgMemAccLat 30.81 # Average memory access latency per DRAM burst
225system.mem_ctrls.avgRdBW 458.90 # Average DRAM read bandwidth in MiByte/s
226system.mem_ctrls.avgWrBW 465.64 # Average achieved write bandwidth in MiByte/s
227system.mem_ctrls.avgRdBWSys 896.05 # Average system read bandwidth in MiByte/s
228system.mem_ctrls.avgWrBWSys 893.98 # Average system write bandwidth in MiByte/s
229system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
230system.mem_ctrls.busUtil 7.22 # Data bus utilization in percentage
231system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads
232system.mem_ctrls.busUtilWrite 3.64 # Data bus utilization in percentage for writes
233system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
234system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing
235system.mem_ctrls.readRowHits 665 # Number of row buffer hits during reads
236system.mem_ctrls.writeRowHits 854 # Number of row buffer hits during writes
237system.mem_ctrls.readRowHitRate 75.06 # Row buffer hit rate for reads
238system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes
239system.mem_ctrls.avgGap 35.73 # Average gap between requests
240system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined

241system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states
242system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states
243system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states
244system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states
245system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states
246system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ)
247system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ)
248system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ)
249system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ)
250system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ)
251system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ)
252system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ)
253system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ)
254system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ)
255system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ)
256system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ)
257system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ)
258system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ)
259system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ)
260system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ)
261system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ)
262system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW)
263system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW)
264system.ruby.clk_domain.clock 1 # Clock period in ticks
265system.ruby.delayHist::bucket_size 1 # delay histogram for all message
266system.ruby.delayHist::max_bucket 9 # delay histogram for all message
267system.ruby.delayHist::samples 3456 # delay histogram for all message
268system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
269system.ruby.delayHist::total 3456 # delay histogram for all message
270system.ruby.outstanding_req_hist::bucket_size 1
271system.ruby.outstanding_req_hist::max_bucket 9
272system.ruby.outstanding_req_hist::samples 8449
273system.ruby.outstanding_req_hist::mean 1
274system.ruby.outstanding_req_hist::gmean 1
275system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
276system.ruby.outstanding_req_hist::total 8449
277system.ruby.latency_hist::bucket_size 64
278system.ruby.latency_hist::max_bucket 639
279system.ruby.latency_hist::samples 8448
280system.ruby.latency_hist::mean 13.626420
281system.ruby.latency_hist::gmean 5.329740
282system.ruby.latency_hist::stdev 25.242996
283system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
284system.ruby.latency_hist::total 8448
285system.ruby.hit_latency_hist::bucket_size 1
286system.ruby.hit_latency_hist::max_bucket 9
287system.ruby.hit_latency_hist::samples 6718
288system.ruby.hit_latency_hist::mean 3
289system.ruby.hit_latency_hist::gmean 3.000000
290system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
291system.ruby.hit_latency_hist::total 6718
292system.ruby.miss_latency_hist::bucket_size 64
293system.ruby.miss_latency_hist::max_bucket 639
294system.ruby.miss_latency_hist::samples 1730
295system.ruby.miss_latency_hist::mean 54.891329
296system.ruby.miss_latency_hist::gmean 49.648144
297system.ruby.miss_latency_hist::stdev 31.153546
298system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
299system.ruby.miss_latency_hist::total 1730
300system.ruby.Directory.incomplete_times 1729
301system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
302system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
303system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
304system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses

241system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ)
242system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ)
243system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ)
244system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ)
245system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
246system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ)
247system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ)
248system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ)
249system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW)
250system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states
251system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states
252system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
253system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states
254system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
255system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ)
256system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ)
257system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ)
258system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ)
259system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
260system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ)
261system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ)
262system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ)
263system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW)
264system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states
265system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states
266system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
267system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states
268system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states

305system.cpu.clk_domain.clock 1 # Clock period in ticks

269system.cpu.clk_domain.clock 1 # Clock period in ticks

306system.ruby.network.routers0.percent_links_utilized 6.992328
307system.ruby.network.routers0.msg_count.Control::2 1730
308system.ruby.network.routers0.msg_count.Data::2 1726
309system.ruby.network.routers0.msg_count.Response_Data::4 1730
310system.ruby.network.routers0.msg_count.Writeback_Control::3 1726
311system.ruby.network.routers0.msg_bytes.Control::2 13840
312system.ruby.network.routers0.msg_bytes.Data::2 124272
313system.ruby.network.routers0.msg_bytes.Response_Data::4 124560
314system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808
315system.ruby.network.routers1.percent_links_utilized 6.992328
316system.ruby.network.routers1.msg_count.Control::2 1730
317system.ruby.network.routers1.msg_count.Data::2 1726
318system.ruby.network.routers1.msg_count.Response_Data::4 1730
319system.ruby.network.routers1.msg_count.Writeback_Control::3 1726
320system.ruby.network.routers1.msg_bytes.Control::2 13840
321system.ruby.network.routers1.msg_bytes.Data::2 124272
322system.ruby.network.routers1.msg_bytes.Response_Data::4 124560
323system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808
324system.ruby.network.routers2.percent_links_utilized 6.992328
325system.ruby.network.routers2.msg_count.Control::2 1730
326system.ruby.network.routers2.msg_count.Data::2 1726
327system.ruby.network.routers2.msg_count.Response_Data::4 1730
328system.ruby.network.routers2.msg_count.Writeback_Control::3 1726
329system.ruby.network.routers2.msg_bytes.Control::2 13840
330system.ruby.network.routers2.msg_bytes.Data::2 124272
331system.ruby.network.routers2.msg_bytes.Response_Data::4 124560
332system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808
333system.ruby.network.msg_count.Control 5190
334system.ruby.network.msg_count.Data 5178
335system.ruby.network.msg_count.Response_Data 5190
336system.ruby.network.msg_count.Writeback_Control 5178
337system.ruby.network.msg_byte.Control 41520
338system.ruby.network.msg_byte.Data 372816
339system.ruby.network.msg_byte.Response_Data 373680
340system.ruby.network.msg_byte.Writeback_Control 41424

341system.cpu.dtb.fetch_hits 0 # ITB hits
342system.cpu.dtb.fetch_misses 0 # ITB misses
343system.cpu.dtb.fetch_acv 0 # ITB acv
344system.cpu.dtb.fetch_accesses 0 # ITB accesses
345system.cpu.dtb.read_hits 1183 # DTB read hits
346system.cpu.dtb.read_misses 7 # DTB read misses
347system.cpu.dtb.read_acv 0 # DTB read access violations
348system.cpu.dtb.read_accesses 1190 # DTB read accesses
349system.cpu.dtb.write_hits 865 # DTB write hits
350system.cpu.dtb.write_misses 3 # DTB write misses
351system.cpu.dtb.write_acv 0 # DTB write access violations
352system.cpu.dtb.write_accesses 868 # DTB write accesses
353system.cpu.dtb.data_hits 2048 # DTB hits
354system.cpu.dtb.data_misses 10 # DTB misses
355system.cpu.dtb.data_acv 0 # DTB access violations
356system.cpu.dtb.data_accesses 2058 # DTB accesses
357system.cpu.itb.fetch_hits 6401 # ITB hits
358system.cpu.itb.fetch_misses 17 # ITB misses
359system.cpu.itb.fetch_acv 0 # ITB acv
360system.cpu.itb.fetch_accesses 6418 # ITB accesses
361system.cpu.itb.read_hits 0 # DTB read hits
362system.cpu.itb.read_misses 0 # DTB read misses
363system.cpu.itb.read_acv 0 # DTB read access violations
364system.cpu.itb.read_accesses 0 # DTB read accesses
365system.cpu.itb.write_hits 0 # DTB write hits
366system.cpu.itb.write_misses 0 # DTB write misses
367system.cpu.itb.write_acv 0 # DTB write access violations
368system.cpu.itb.write_accesses 0 # DTB write accesses
369system.cpu.itb.data_hits 0 # DTB hits
370system.cpu.itb.data_misses 0 # DTB misses
371system.cpu.itb.data_acv 0 # DTB access violations
372system.cpu.itb.data_accesses 0 # DTB accesses
373system.cpu.workload.num_syscalls 17 # Number of system calls
374system.cpu.numCycles 123564 # number of cpu cycles simulated
375system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
376system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
377system.cpu.committedInsts 6390 # Number of instructions committed
378system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
379system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
380system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
381system.cpu.num_func_calls 251 # number of times a function call or return occured
382system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
383system.cpu.num_int_insts 6317 # number of integer instructions
384system.cpu.num_fp_insts 10 # number of float instructions
385system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
386system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
387system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
388system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
389system.cpu.num_mem_refs 2058 # number of memory refs
390system.cpu.num_load_insts 1190 # Number of load instructions
391system.cpu.num_store_insts 868 # Number of store instructions
392system.cpu.num_idle_cycles 0 # Number of idle cycles
393system.cpu.num_busy_cycles 123564 # Number of busy cycles
394system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
395system.cpu.idle_fraction 0 # Percentage of idle cycles
396system.cpu.Branches 1050 # Number of branches fetched
397system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
398system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
399system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
400system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
401system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
402system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
403system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
404system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
405system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
406system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
407system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
408system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
409system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
410system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
411system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
412system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
413system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
414system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
415system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
416system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
417system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
418system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
419system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
420system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
421system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
422system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
423system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
424system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
425system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
426system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
427system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
428system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
429system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
430system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
431system.cpu.op_class::total 6400 # Class of executed instruction

270system.cpu.dtb.fetch_hits 0 # ITB hits
271system.cpu.dtb.fetch_misses 0 # ITB misses
272system.cpu.dtb.fetch_acv 0 # ITB acv
273system.cpu.dtb.fetch_accesses 0 # ITB accesses
274system.cpu.dtb.read_hits 1183 # DTB read hits
275system.cpu.dtb.read_misses 7 # DTB read misses
276system.cpu.dtb.read_acv 0 # DTB read access violations
277system.cpu.dtb.read_accesses 1190 # DTB read accesses
278system.cpu.dtb.write_hits 865 # DTB write hits
279system.cpu.dtb.write_misses 3 # DTB write misses
280system.cpu.dtb.write_acv 0 # DTB write access violations
281system.cpu.dtb.write_accesses 868 # DTB write accesses
282system.cpu.dtb.data_hits 2048 # DTB hits
283system.cpu.dtb.data_misses 10 # DTB misses
284system.cpu.dtb.data_acv 0 # DTB access violations
285system.cpu.dtb.data_accesses 2058 # DTB accesses
286system.cpu.itb.fetch_hits 6401 # ITB hits
287system.cpu.itb.fetch_misses 17 # ITB misses
288system.cpu.itb.fetch_acv 0 # ITB acv
289system.cpu.itb.fetch_accesses 6418 # ITB accesses
290system.cpu.itb.read_hits 0 # DTB read hits
291system.cpu.itb.read_misses 0 # DTB read misses
292system.cpu.itb.read_acv 0 # DTB read access violations
293system.cpu.itb.read_accesses 0 # DTB read accesses
294system.cpu.itb.write_hits 0 # DTB write hits
295system.cpu.itb.write_misses 0 # DTB write misses
296system.cpu.itb.write_acv 0 # DTB write access violations
297system.cpu.itb.write_accesses 0 # DTB write accesses
298system.cpu.itb.data_hits 0 # DTB hits
299system.cpu.itb.data_misses 0 # DTB misses
300system.cpu.itb.data_acv 0 # DTB access violations
301system.cpu.itb.data_accesses 0 # DTB accesses
302system.cpu.workload.num_syscalls 17 # Number of system calls
303system.cpu.numCycles 123564 # number of cpu cycles simulated
304system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
305system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
306system.cpu.committedInsts 6390 # Number of instructions committed
307system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
308system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
309system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
310system.cpu.num_func_calls 251 # number of times a function call or return occured
311system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
312system.cpu.num_int_insts 6317 # number of integer instructions
313system.cpu.num_fp_insts 10 # number of float instructions
314system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
315system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
316system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
317system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
318system.cpu.num_mem_refs 2058 # number of memory refs
319system.cpu.num_load_insts 1190 # Number of load instructions
320system.cpu.num_store_insts 868 # Number of store instructions
321system.cpu.num_idle_cycles 0 # Number of idle cycles
322system.cpu.num_busy_cycles 123564 # Number of busy cycles
323system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
324system.cpu.idle_fraction 0 # Percentage of idle cycles
325system.cpu.Branches 1050 # Number of branches fetched
326system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
327system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
328system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
329system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
330system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
331system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
332system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
333system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
334system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
335system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
336system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
337system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
338system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
339system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
340system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
341system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
342system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
343system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
344system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
345system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
346system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
347system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
348system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
349system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
350system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
351system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
352system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
353system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
354system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
355system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
356system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
357system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
358system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
359system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
360system.cpu.op_class::total 6400 # Class of executed instruction

361system.ruby.clk_domain.clock 1 # Clock period in ticks
362system.ruby.delayHist::bucket_size 1 # delay histogram for all message
363system.ruby.delayHist::max_bucket 9 # delay histogram for all message
364system.ruby.delayHist::samples 3456 # delay histogram for all message
365system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
366system.ruby.delayHist::total 3456 # delay histogram for all message
367system.ruby.outstanding_req_hist::bucket_size 1
368system.ruby.outstanding_req_hist::max_bucket 9
369system.ruby.outstanding_req_hist::samples 8449
370system.ruby.outstanding_req_hist::mean 1
371system.ruby.outstanding_req_hist::gmean 1
372system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
373system.ruby.outstanding_req_hist::total 8449
374system.ruby.latency_hist::bucket_size 64
375system.ruby.latency_hist::max_bucket 639
376system.ruby.latency_hist::samples 8448
377system.ruby.latency_hist::mean 13.626420
378system.ruby.latency_hist::gmean 5.329740
379system.ruby.latency_hist::stdev 25.242996
380system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
381system.ruby.latency_hist::total 8448
382system.ruby.hit_latency_hist::bucket_size 1
383system.ruby.hit_latency_hist::max_bucket 9
384system.ruby.hit_latency_hist::samples 6718
385system.ruby.hit_latency_hist::mean 3
386system.ruby.hit_latency_hist::gmean 3.000000
387system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
388system.ruby.hit_latency_hist::total 6718
389system.ruby.miss_latency_hist::bucket_size 64
390system.ruby.miss_latency_hist::max_bucket 639
391system.ruby.miss_latency_hist::samples 1730
392system.ruby.miss_latency_hist::mean 54.891329
393system.ruby.miss_latency_hist::gmean 49.648144
394system.ruby.miss_latency_hist::stdev 31.153546
395system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
396system.ruby.miss_latency_hist::total 1730
397system.ruby.Directory.incomplete_times 1729
398system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
399system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
400system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses
401system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
402system.ruby.network.routers0.percent_links_utilized 6.992328
403system.ruby.network.routers0.msg_count.Control::2 1730
404system.ruby.network.routers0.msg_count.Data::2 1726
405system.ruby.network.routers0.msg_count.Response_Data::4 1730
406system.ruby.network.routers0.msg_count.Writeback_Control::3 1726
407system.ruby.network.routers0.msg_bytes.Control::2 13840
408system.ruby.network.routers0.msg_bytes.Data::2 124272
409system.ruby.network.routers0.msg_bytes.Response_Data::4 124560
410system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808
411system.ruby.network.routers1.percent_links_utilized 6.992328
412system.ruby.network.routers1.msg_count.Control::2 1730
413system.ruby.network.routers1.msg_count.Data::2 1726
414system.ruby.network.routers1.msg_count.Response_Data::4 1730
415system.ruby.network.routers1.msg_count.Writeback_Control::3 1726
416system.ruby.network.routers1.msg_bytes.Control::2 13840
417system.ruby.network.routers1.msg_bytes.Data::2 124272
418system.ruby.network.routers1.msg_bytes.Response_Data::4 124560
419system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808
420system.ruby.network.routers2.percent_links_utilized 6.992328
421system.ruby.network.routers2.msg_count.Control::2 1730
422system.ruby.network.routers2.msg_count.Data::2 1726
423system.ruby.network.routers2.msg_count.Response_Data::4 1730
424system.ruby.network.routers2.msg_count.Writeback_Control::3 1726
425system.ruby.network.routers2.msg_bytes.Control::2 13840
426system.ruby.network.routers2.msg_bytes.Data::2 124272
427system.ruby.network.routers2.msg_bytes.Response_Data::4 124560
428system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808
429system.ruby.network.msg_count.Control 5190
430system.ruby.network.msg_count.Data 5178
431system.ruby.network.msg_count.Response_Data 5190
432system.ruby.network.msg_count.Writeback_Control 5178
433system.ruby.network.msg_byte.Control 41520
434system.ruby.network.msg_byte.Data 372816
435system.ruby.network.msg_byte.Response_Data 373680
436system.ruby.network.msg_byte.Writeback_Control 41424

432system.ruby.network.routers0.throttle0.link_utilization 6.998802
433system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
434system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
435system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560
436system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808
437system.ruby.network.routers0.throttle1.link_utilization 6.985853
438system.ruby.network.routers0.throttle1.msg_count.Control::2 1730
439system.ruby.network.routers0.throttle1.msg_count.Data::2 1726
440system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840
441system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272
442system.ruby.network.routers1.throttle0.link_utilization 6.985853
443system.ruby.network.routers1.throttle0.msg_count.Control::2 1730
444system.ruby.network.routers1.throttle0.msg_count.Data::2 1726
445system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840
446system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272
447system.ruby.network.routers1.throttle1.link_utilization 6.998802
448system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730
449system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726
450system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560
451system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808
452system.ruby.network.routers2.throttle0.link_utilization 6.998802
453system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730
454system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726
455system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560
456system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808
457system.ruby.network.routers2.throttle1.link_utilization 6.985853
458system.ruby.network.routers2.throttle1.msg_count.Control::2 1730
459system.ruby.network.routers2.throttle1.msg_count.Data::2 1726
460system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840
461system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272
462system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
463system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
464system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1
465system.ruby.delayVCHist.vnet_1 | 1730 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
466system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1
467system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
468system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
469system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2
470system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
471system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2
472system.ruby.LD.latency_hist::bucket_size 64
473system.ruby.LD.latency_hist::max_bucket 639
474system.ruby.LD.latency_hist::samples 1183
475system.ruby.LD.latency_hist::mean 33.711750
476system.ruby.LD.latency_hist::gmean 16.462445
477system.ruby.LD.latency_hist::stdev 33.973523
478system.ruby.LD.latency_hist | 1077 91.04% 91.04% | 86 7.27% 98.31% | 15 1.27% 99.58% | 2 0.17% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
479system.ruby.LD.latency_hist::total 1183
480system.ruby.LD.hit_latency_hist::bucket_size 1
481system.ruby.LD.hit_latency_hist::max_bucket 9
482system.ruby.LD.hit_latency_hist::samples 456
483system.ruby.LD.hit_latency_hist::mean 3
484system.ruby.LD.hit_latency_hist::gmean 3.000000
485system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
486system.ruby.LD.hit_latency_hist::total 456
487system.ruby.LD.miss_latency_hist::bucket_size 64
488system.ruby.LD.miss_latency_hist::max_bucket 639
489system.ruby.LD.miss_latency_hist::samples 727
490system.ruby.LD.miss_latency_hist::mean 52.975241
491system.ruby.LD.miss_latency_hist::gmean 47.891138
492system.ruby.LD.miss_latency_hist::stdev 30.251097
493system.ruby.LD.miss_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
494system.ruby.LD.miss_latency_hist::total 727
495system.ruby.ST.latency_hist::bucket_size 64
496system.ruby.ST.latency_hist::max_bucket 639
497system.ruby.ST.latency_hist::samples 865
498system.ruby.ST.latency_hist::mean 18.557225
499system.ruby.ST.latency_hist::gmean 7.162336
500system.ruby.ST.latency_hist::stdev 28.547301
501system.ruby.ST.latency_hist | 834 96.42% 96.42% | 21 2.43% 98.84% | 9 1.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
502system.ruby.ST.latency_hist::total 865
503system.ruby.ST.hit_latency_hist::bucket_size 1
504system.ruby.ST.hit_latency_hist::max_bucket 9
505system.ruby.ST.hit_latency_hist::samples 592
506system.ruby.ST.hit_latency_hist::mean 3
507system.ruby.ST.hit_latency_hist::gmean 3.000000
508system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
509system.ruby.ST.hit_latency_hist::total 592
510system.ruby.ST.miss_latency_hist::bucket_size 64
511system.ruby.ST.miss_latency_hist::max_bucket 639
512system.ruby.ST.miss_latency_hist::samples 273
513system.ruby.ST.miss_latency_hist::mean 52.293040
514system.ruby.ST.miss_latency_hist::gmean 47.271858
515system.ruby.ST.miss_latency_hist::stdev 30.324989
516system.ruby.ST.miss_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
517system.ruby.ST.miss_latency_hist::total 273
518system.ruby.IFETCH.latency_hist::bucket_size 64
519system.ruby.IFETCH.latency_hist::max_bucket 639
520system.ruby.IFETCH.latency_hist::samples 6400
521system.ruby.IFETCH.latency_hist::mean 9.247344
522system.ruby.IFETCH.latency_hist::gmean 4.157427
523system.ruby.IFETCH.latency_hist::stdev 20.515003
524system.ruby.IFETCH.latency_hist | 6284 98.19% 98.19% | 92 1.44% 99.63% | 19 0.30% 99.92% | 0 0.00% 99.92% | 3 0.05% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
525system.ruby.IFETCH.latency_hist::total 6400
526system.ruby.IFETCH.hit_latency_hist::bucket_size 1
527system.ruby.IFETCH.hit_latency_hist::max_bucket 9
528system.ruby.IFETCH.hit_latency_hist::samples 5670
529system.ruby.IFETCH.hit_latency_hist::mean 3
530system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
531system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
532system.ruby.IFETCH.hit_latency_hist::total 5670
533system.ruby.IFETCH.miss_latency_hist::bucket_size 64
534system.ruby.IFETCH.miss_latency_hist::max_bucket 639
535system.ruby.IFETCH.miss_latency_hist::samples 730
536system.ruby.IFETCH.miss_latency_hist::mean 57.771233
537system.ruby.IFETCH.miss_latency_hist::gmean 52.414605
538system.ruby.IFETCH.miss_latency_hist::stdev 32.138819
539system.ruby.IFETCH.miss_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
540system.ruby.IFETCH.miss_latency_hist::total 730
541system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
542system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
543system.ruby.Directory.miss_mach_latency_hist::samples 1730
544system.ruby.Directory.miss_mach_latency_hist::mean 54.891329
545system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144
546system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546
547system.ruby.Directory.miss_mach_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
548system.ruby.Directory.miss_mach_latency_hist::total 1730
549system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
550system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
551system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
552system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
553system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
554system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
555system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
556system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
557system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
558system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
559system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
560system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
561system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
562system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
563system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
564system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
565system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
566system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
567system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
568system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
569system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
570system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
571system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
572system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
573system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
574system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
575system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
576system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
577system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727
578system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241
579system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138
580system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097
581system.ruby.LD.Directory.miss_type_mach_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
582system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727
583system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
584system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
585system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273
586system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040
587system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858
588system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989
589system.ruby.ST.Directory.miss_type_mach_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
590system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273
591system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
592system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
593system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730
594system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233
595system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605
596system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819
597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730

437system.ruby.network.routers0.throttle0.link_utilization 6.998802
438system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
439system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
440system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560
441system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808
442system.ruby.network.routers0.throttle1.link_utilization 6.985853
443system.ruby.network.routers0.throttle1.msg_count.Control::2 1730
444system.ruby.network.routers0.throttle1.msg_count.Data::2 1726
445system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840
446system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272
447system.ruby.network.routers1.throttle0.link_utilization 6.985853
448system.ruby.network.routers1.throttle0.msg_count.Control::2 1730
449system.ruby.network.routers1.throttle0.msg_count.Data::2 1726
450system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840
451system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272
452system.ruby.network.routers1.throttle1.link_utilization 6.998802
453system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730
454system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726
455system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560
456system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808
457system.ruby.network.routers2.throttle0.link_utilization 6.998802
458system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730
459system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726
460system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560
461system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808
462system.ruby.network.routers2.throttle1.link_utilization 6.985853
463system.ruby.network.routers2.throttle1.msg_count.Control::2 1730
464system.ruby.network.routers2.throttle1.msg_count.Data::2 1726
465system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840
466system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272
467system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
468system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
469system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1
470system.ruby.delayVCHist.vnet_1 | 1730 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
471system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1
472system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
473system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
474system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2
475system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
476system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2
477system.ruby.LD.latency_hist::bucket_size 64
478system.ruby.LD.latency_hist::max_bucket 639
479system.ruby.LD.latency_hist::samples 1183
480system.ruby.LD.latency_hist::mean 33.711750
481system.ruby.LD.latency_hist::gmean 16.462445
482system.ruby.LD.latency_hist::stdev 33.973523
483system.ruby.LD.latency_hist | 1077 91.04% 91.04% | 86 7.27% 98.31% | 15 1.27% 99.58% | 2 0.17% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
484system.ruby.LD.latency_hist::total 1183
485system.ruby.LD.hit_latency_hist::bucket_size 1
486system.ruby.LD.hit_latency_hist::max_bucket 9
487system.ruby.LD.hit_latency_hist::samples 456
488system.ruby.LD.hit_latency_hist::mean 3
489system.ruby.LD.hit_latency_hist::gmean 3.000000
490system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
491system.ruby.LD.hit_latency_hist::total 456
492system.ruby.LD.miss_latency_hist::bucket_size 64
493system.ruby.LD.miss_latency_hist::max_bucket 639
494system.ruby.LD.miss_latency_hist::samples 727
495system.ruby.LD.miss_latency_hist::mean 52.975241
496system.ruby.LD.miss_latency_hist::gmean 47.891138
497system.ruby.LD.miss_latency_hist::stdev 30.251097
498system.ruby.LD.miss_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
499system.ruby.LD.miss_latency_hist::total 727
500system.ruby.ST.latency_hist::bucket_size 64
501system.ruby.ST.latency_hist::max_bucket 639
502system.ruby.ST.latency_hist::samples 865
503system.ruby.ST.latency_hist::mean 18.557225
504system.ruby.ST.latency_hist::gmean 7.162336
505system.ruby.ST.latency_hist::stdev 28.547301
506system.ruby.ST.latency_hist | 834 96.42% 96.42% | 21 2.43% 98.84% | 9 1.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
507system.ruby.ST.latency_hist::total 865
508system.ruby.ST.hit_latency_hist::bucket_size 1
509system.ruby.ST.hit_latency_hist::max_bucket 9
510system.ruby.ST.hit_latency_hist::samples 592
511system.ruby.ST.hit_latency_hist::mean 3
512system.ruby.ST.hit_latency_hist::gmean 3.000000
513system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
514system.ruby.ST.hit_latency_hist::total 592
515system.ruby.ST.miss_latency_hist::bucket_size 64
516system.ruby.ST.miss_latency_hist::max_bucket 639
517system.ruby.ST.miss_latency_hist::samples 273
518system.ruby.ST.miss_latency_hist::mean 52.293040
519system.ruby.ST.miss_latency_hist::gmean 47.271858
520system.ruby.ST.miss_latency_hist::stdev 30.324989
521system.ruby.ST.miss_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
522system.ruby.ST.miss_latency_hist::total 273
523system.ruby.IFETCH.latency_hist::bucket_size 64
524system.ruby.IFETCH.latency_hist::max_bucket 639
525system.ruby.IFETCH.latency_hist::samples 6400
526system.ruby.IFETCH.latency_hist::mean 9.247344
527system.ruby.IFETCH.latency_hist::gmean 4.157427
528system.ruby.IFETCH.latency_hist::stdev 20.515003
529system.ruby.IFETCH.latency_hist | 6284 98.19% 98.19% | 92 1.44% 99.63% | 19 0.30% 99.92% | 0 0.00% 99.92% | 3 0.05% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
530system.ruby.IFETCH.latency_hist::total 6400
531system.ruby.IFETCH.hit_latency_hist::bucket_size 1
532system.ruby.IFETCH.hit_latency_hist::max_bucket 9
533system.ruby.IFETCH.hit_latency_hist::samples 5670
534system.ruby.IFETCH.hit_latency_hist::mean 3
535system.ruby.IFETCH.hit_latency_hist::gmean 3.000000
536system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
537system.ruby.IFETCH.hit_latency_hist::total 5670
538system.ruby.IFETCH.miss_latency_hist::bucket_size 64
539system.ruby.IFETCH.miss_latency_hist::max_bucket 639
540system.ruby.IFETCH.miss_latency_hist::samples 730
541system.ruby.IFETCH.miss_latency_hist::mean 57.771233
542system.ruby.IFETCH.miss_latency_hist::gmean 52.414605
543system.ruby.IFETCH.miss_latency_hist::stdev 32.138819
544system.ruby.IFETCH.miss_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
545system.ruby.IFETCH.miss_latency_hist::total 730
546system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
547system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
548system.ruby.Directory.miss_mach_latency_hist::samples 1730
549system.ruby.Directory.miss_mach_latency_hist::mean 54.891329
550system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144
551system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546
552system.ruby.Directory.miss_mach_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
553system.ruby.Directory.miss_mach_latency_hist::total 1730
554system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
555system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
556system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
557system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
558system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
559system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
560system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
561system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
562system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
563system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
564system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
565system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
566system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
567system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
568system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
569system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
570system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
571system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
572system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
573system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
574system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
575system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
576system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
577system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
578system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
579system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
580system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64
581system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639
582system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727
583system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241
584system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138
585system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097
586system.ruby.LD.Directory.miss_type_mach_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
587system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727
588system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
589system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
590system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273
591system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040
592system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858
593system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989
594system.ruby.ST.Directory.miss_type_mach_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
595system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273
596system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730
599system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233
600system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605
601system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819
602system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
603system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730

604system.ruby.Directory_Controller.GETX 1730 0.00% 0.00%
605system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00%
606system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00%
607system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00%
608system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00%
609system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00%
610system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00%
611system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00%

599system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
600system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
601system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
602system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00%
603system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00%
604system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00%
605system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00%
606system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00%
607system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00%
608system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00%
609system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00%
610system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00%
611system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00%
612system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00%
613system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00%
614system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00%

612system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
613system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
614system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
615system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00%
616system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00%
617system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00%
618system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00%
619system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00%
620system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00%
621system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00%
622system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00%
623system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00%
624system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00%
625system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00%
626system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00%
627system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00%

615system.ruby.Directory_Controller.GETX 1730 0.00% 0.00%
616system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00%
617system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00%
618system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00%
619system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00%
620system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00%
621system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00%
622system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00%