1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000112 # Number of seconds simulated
4sim_ticks 112490 # Number of ticks simulated
5final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000 # Frequency of simulated ticks
7host_inst_rate 94486 # Simulator instruction rate (inst/s)
8host_op_rate 94411 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1658372 # Simulator tick rate (ticks/s)
10host_mem_usage 414356 # Number of bytes of host memory used
11host_seconds 0.07 # Real time elapsed on the host
12sim_insts 6403 # Number of instructions simulated
13sim_ops 6403 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1 # Clock period in ticks
16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
17system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
18system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
19system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
20system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory
21system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory
22system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory
23system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory
24system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory
25system.mem_ctrls.bw_read::ruby.dir_cntrl0 984834207 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrls.bw_read::total 984834207 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrls.bw_write::ruby.dir_cntrl0 982558450 # Write bandwidth from this memory (bytes/s)
28system.mem_ctrls.bw_write::total 982558450 # Write bandwidth from this memory (bytes/s)
29system.mem_ctrls.bw_total::ruby.dir_cntrl0 1967392657 # Total bandwidth to/from this memory (bytes/s)
30system.mem_ctrls.bw_total::total 1967392657 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrls.readReqs 1731 # Number of read requests accepted
32system.mem_ctrls.writeReqs 1727 # Number of write requests accepted
33system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue
34system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue
35system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM
36system.mem_ctrls.bytesReadWrQ 54080 # Total number of bytes read from write queue
37system.mem_ctrls.bytesWritten 57088 # Total number of bytes written to DRAM
38system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side
39system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side
40system.mem_ctrls.servicedByWrQ 845 # Number of DRAM read bursts serviced by the write queue
41system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one
42system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
43system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
44system.mem_ctrls.perBankRdBursts::1 50 # Per bank write bursts
45system.mem_ctrls.perBankRdBursts::2 70 # Per bank write bursts
46system.mem_ctrls.perBankRdBursts::3 63 # Per bank write bursts
47system.mem_ctrls.perBankRdBursts::4 108 # Per bank write bursts
48system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts
49system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
50system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
51system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
52system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
53system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts
54system.mem_ctrls.perBankRdBursts::11 36 # Per bank write bursts
55system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts
56system.mem_ctrls.perBankRdBursts::13 270 # Per bank write bursts
57system.mem_ctrls.perBankRdBursts::14 81 # Per bank write bursts
58system.mem_ctrls.perBankRdBursts::15 24 # Per bank write bursts
59system.mem_ctrls.perBankWrBursts::0 82 # Per bank write bursts
60system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts
61system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts
62system.mem_ctrls.perBankWrBursts::3 60 # Per bank write bursts
63system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts
64system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts
65system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
66system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
67system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
68system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
69system.mem_ctrls.perBankWrBursts::10 50 # Per bank write bursts
70system.mem_ctrls.perBankWrBursts::11 33 # Per bank write bursts
71system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts
72system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts
73system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
74system.mem_ctrls.perBankWrBursts::15 24 # Per bank write bursts
75system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
76system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
77system.mem_ctrls.totGap 112412 # Total gap between requests
78system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
79system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
80system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
81system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
82system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
83system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
84system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2)
85system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
86system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
87system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
88system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
89system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
90system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
91system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2)
92system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see
93system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
94system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
95system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
96system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
97system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
98system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
99system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
100system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
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131system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
132system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
133system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
134system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
135system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
136system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
137system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
138system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
139system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
140system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
141system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see
142system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
143system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see
144system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see
145system.mem_ctrls.wrQLenPdf::21 60 # What write queue length does an incoming req see
146system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
147system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see
148system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see
149system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
150system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
151system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see
152system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
153system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
154system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
155system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see
156system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
157system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
158system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
159system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
160system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
161system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
162system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
163system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
164system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
165system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
--- 14 unchanged lines hidden (view full) ---
180system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
181system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
182system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
183system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
184system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
185system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
186system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
187system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
188system.mem_ctrls.bytesPerActivate::samples 264 # Bytes accessed per row activation
189system.mem_ctrls.bytesPerActivate::mean 424 # Bytes accessed per row activation
190system.mem_ctrls.bytesPerActivate::gmean 260.079273 # Bytes accessed per row activation
191system.mem_ctrls.bytesPerActivate::stdev 372.426347 # Bytes accessed per row activation
192system.mem_ctrls.bytesPerActivate::0-127 66 25.00% 25.00% # Bytes accessed per row activation
193system.mem_ctrls.bytesPerActivate::128-255 58 21.97% 46.97% # Bytes accessed per row activation
194system.mem_ctrls.bytesPerActivate::256-383 27 10.23% 57.20% # Bytes accessed per row activation
195system.mem_ctrls.bytesPerActivate::384-511 16 6.06% 63.26% # Bytes accessed per row activation
196system.mem_ctrls.bytesPerActivate::512-639 17 6.44% 69.70% # Bytes accessed per row activation
197system.mem_ctrls.bytesPerActivate::640-767 8 3.03% 72.73% # Bytes accessed per row activation
198system.mem_ctrls.bytesPerActivate::768-895 12 4.55% 77.27% # Bytes accessed per row activation
199system.mem_ctrls.bytesPerActivate::896-1023 10 3.79% 81.06% # Bytes accessed per row activation
200system.mem_ctrls.bytesPerActivate::1024-1151 50 18.94% 100.00% # Bytes accessed per row activation
201system.mem_ctrls.bytesPerActivate::total 264 # Bytes accessed per row activation
202system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
203system.mem_ctrls.rdPerTurnAround::mean 15.818182 # Reads before turning the bus around for writes
204system.mem_ctrls.rdPerTurnAround::gmean 15.638991 # Reads before turning the bus around for writes
205system.mem_ctrls.rdPerTurnAround::stdev 2.938196 # Reads before turning the bus around for writes
206system.mem_ctrls.rdPerTurnAround::12-13 3 5.45% 5.45% # Reads before turning the bus around for writes
207system.mem_ctrls.rdPerTurnAround::14-15 24 43.64% 49.09% # Reads before turning the bus around for writes
208system.mem_ctrls.rdPerTurnAround::16-17 23 41.82% 90.91% # Reads before turning the bus around for writes
209system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
210system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes
211system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
212system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
213system.mem_ctrls.wrPerTurnAround::mean 16.218182 # Writes before turning the bus around for reads
214system.mem_ctrls.wrPerTurnAround::gmean 16.206001 # Writes before turning the bus around for reads
215system.mem_ctrls.wrPerTurnAround::stdev 0.658025 # Writes before turning the bus around for reads
216system.mem_ctrls.wrPerTurnAround::16 49 89.09% 89.09% # Writes before turning the bus around for reads
217system.mem_ctrls.wrPerTurnAround::17 1 1.82% 90.91% # Writes before turning the bus around for reads
218system.mem_ctrls.wrPerTurnAround::18 4 7.27% 98.18% # Writes before turning the bus around for reads
219system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads
220system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
221system.mem_ctrls.totQLat 16225 # Total ticks spent queuing
222system.mem_ctrls.totMemAccLat 33059 # Total ticks spent from burst creation until serviced by the DRAM
223system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers
224system.mem_ctrls.avgQLat 18.31 # Average queueing delay per DRAM burst
225system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
226system.mem_ctrls.avgMemAccLat 37.31 # Average memory access latency per DRAM burst
227system.mem_ctrls.avgRdBW 504.08 # Average DRAM read bandwidth in MiByte/s
228system.mem_ctrls.avgWrBW 507.49 # Average achieved write bandwidth in MiByte/s
229system.mem_ctrls.avgRdBWSys 984.83 # Average system read bandwidth in MiByte/s
230system.mem_ctrls.avgWrBWSys 982.56 # Average system write bandwidth in MiByte/s
231system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
232system.mem_ctrls.busUtil 7.90 # Data bus utilization in percentage
233system.mem_ctrls.busUtilRead 3.94 # Data bus utilization in percentage for reads
234system.mem_ctrls.busUtilWrite 3.96 # Data bus utilization in percentage for writes
235system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
236system.mem_ctrls.avgWrQLen 26.10 # Average write queue length when enqueuing
237system.mem_ctrls.readRowHits 674 # Number of row buffer hits during reads
238system.mem_ctrls.writeRowHits 833 # Number of row buffer hits during writes
239system.mem_ctrls.readRowHitRate 76.07 # Row buffer hit rate for reads
240system.mem_ctrls.writeRowHitRate 90.15 # Row buffer hit rate for writes
241system.mem_ctrls.avgGap 32.51 # Average gap between requests
242system.mem_ctrls.pageHitRate 83.26 # Row buffer hit rate, read and write combined
243system.mem_ctrls_0.actEnergy 735420 # Energy for activate commands per rank (pJ)
244system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ)
245system.mem_ctrls_0.readEnergy 4581024 # Energy for read commands per rank (pJ)
246system.mem_ctrls_0.writeEnergy 3532896 # Energy for write commands per rank (pJ)
247system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
248system.mem_ctrls_0.actBackEnergy 13923048 # Energy for active background per rank (pJ)
249system.mem_ctrls_0.preBackEnergy 195072 # Energy for precharge background per rank (pJ)
250system.mem_ctrls_0.actPowerDownEnergy 30921360 # Energy for active power-down per rank (pJ)
251system.mem_ctrls_0.prePowerDownEnergy 5237376 # Energy for precharge power-down per rank (pJ)
252system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
253system.mem_ctrls_0.totalEnergy 68117556 # Total energy per rank (pJ)
254system.mem_ctrls_0.averagePower 605.543213 # Core power per rank (mW)
255system.mem_ctrls_0.totalIdleTime 81406 # Total Idle time Per DRAM Rank
256system.mem_ctrls_0.memoryStateTime::IDLE 88 # Time in different power states
257system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states
258system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
259system.mem_ctrls_0.memoryStateTime::PRE_PDN 13639 # Time in different power states
260system.mem_ctrls_0.memoryStateTime::ACT 27313 # Time in different power states
261system.mem_ctrls_0.memoryStateTime::ACT_PDN 67810 # Time in different power states
262system.mem_ctrls_1.actEnergy 1199520 # Energy for activate commands per rank (pJ)
263system.mem_ctrls_1.preEnergy 633696 # Energy for precharge commands per rank (pJ)
264system.mem_ctrls_1.readEnergy 5540640 # Energy for read commands per rank (pJ)
265system.mem_ctrls_1.writeEnergy 3917088 # Energy for write commands per rank (pJ)
266system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
267system.mem_ctrls_1.actBackEnergy 12524952 # Energy for active background per rank (pJ)
268system.mem_ctrls_1.preBackEnergy 314880 # Energy for precharge background per rank (pJ)
269system.mem_ctrls_1.actPowerDownEnergy 33139344 # Energy for active power-down per rank (pJ)
270system.mem_ctrls_1.prePowerDownEnergy 4427136 # Energy for precharge power-down per rank (pJ)
271system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
272system.mem_ctrls_1.totalEnergy 70302216 # Total energy per rank (pJ)
273system.mem_ctrls_1.averagePower 624.964139 # Core power per rank (mW)
274system.mem_ctrls_1.totalIdleTime 83983 # Total Idle time Per DRAM Rank
275system.mem_ctrls_1.memoryStateTime::IDLE 260 # Time in different power states
276system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
277system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
278system.mem_ctrls_1.memoryStateTime::PRE_PDN 11529 # Time in different power states
279system.mem_ctrls_1.memoryStateTime::ACT 24387 # Time in different power states
280system.mem_ctrls_1.memoryStateTime::ACT_PDN 72674 # Time in different power states
281system.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
282system.cpu.clk_domain.clock 1 # Clock period in ticks
283system.cpu.dtb.fetch_hits 0 # ITB hits
284system.cpu.dtb.fetch_misses 0 # ITB misses
285system.cpu.dtb.fetch_acv 0 # ITB acv
286system.cpu.dtb.fetch_accesses 0 # ITB accesses
287system.cpu.dtb.read_hits 1185 # DTB read hits
288system.cpu.dtb.read_misses 7 # DTB read misses
289system.cpu.dtb.read_acv 0 # DTB read access violations
--- 18 unchanged lines hidden (view full) ---
308system.cpu.itb.write_misses 0 # DTB write misses
309system.cpu.itb.write_acv 0 # DTB write access violations
310system.cpu.itb.write_accesses 0 # DTB write accesses
311system.cpu.itb.data_hits 0 # DTB hits
312system.cpu.itb.data_misses 0 # DTB misses
313system.cpu.itb.data_acv 0 # DTB access violations
314system.cpu.itb.data_accesses 0 # DTB accesses
315system.cpu.workload.num_syscalls 17 # Number of system calls
316system.cpu.pwrStateResidencyTicks::ON 112490 # Cumulative time (in ticks) in various power states
317system.cpu.numCycles 112490 # number of cpu cycles simulated
318system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
319system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
320system.cpu.committedInsts 6403 # Number of instructions committed
321system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
322system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
323system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
324system.cpu.num_func_calls 251 # number of times a function call or return occured
325system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
326system.cpu.num_int_insts 6329 # number of integer instructions
327system.cpu.num_fp_insts 10 # number of float instructions
328system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
329system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
330system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
331system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
332system.cpu.num_mem_refs 2060 # number of memory refs
333system.cpu.num_load_insts 1192 # Number of load instructions
334system.cpu.num_store_insts 868 # Number of store instructions
335system.cpu.num_idle_cycles 0 # Number of idle cycles
336system.cpu.num_busy_cycles 112490 # Number of busy cycles
337system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
338system.cpu.idle_fraction 0 # Percentage of idle cycles
339system.cpu.Branches 1056 # Number of branches fetched
340system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
341system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
342system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
343system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
344system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
--- 23 unchanged lines hidden (view full) ---
368system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
369system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
370system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
371system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
372system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
373system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
374system.cpu.op_class::total 6413 # Class of executed instruction
375system.ruby.clk_domain.clock 1 # Clock period in ticks
376system.ruby.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
377system.ruby.delayHist::bucket_size 1 # delay histogram for all message
378system.ruby.delayHist::max_bucket 9 # delay histogram for all message
379system.ruby.delayHist::samples 3458 # delay histogram for all message
380system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
381system.ruby.delayHist::total 3458 # delay histogram for all message
382system.ruby.outstanding_req_hist_seqr::bucket_size 1
383system.ruby.outstanding_req_hist_seqr::max_bucket 9
384system.ruby.outstanding_req_hist_seqr::samples 8464
385system.ruby.outstanding_req_hist_seqr::mean 1
386system.ruby.outstanding_req_hist_seqr::gmean 1
387system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
388system.ruby.outstanding_req_hist_seqr::total 8464
389system.ruby.latency_hist_seqr::bucket_size 64
390system.ruby.latency_hist_seqr::max_bucket 639
391system.ruby.latency_hist_seqr::samples 8463
392system.ruby.latency_hist_seqr::mean 12.291977
393system.ruby.latency_hist_seqr::gmean 2.221869
394system.ruby.latency_hist_seqr::stdev 27.407806
395system.ruby.latency_hist_seqr | 7608 89.90% 89.90% | 798 9.43% 99.33% | 40 0.47% 99.80% | 5 0.06% 99.86% | 6 0.07% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
396system.ruby.latency_hist_seqr::total 8463
397system.ruby.hit_latency_hist_seqr::bucket_size 1
398system.ruby.hit_latency_hist_seqr::max_bucket 9
399system.ruby.hit_latency_hist_seqr::samples 6732
400system.ruby.hit_latency_hist_seqr::mean 1
401system.ruby.hit_latency_hist_seqr::gmean 1
402system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
403system.ruby.hit_latency_hist_seqr::total 6732
404system.ruby.miss_latency_hist_seqr::bucket_size 64
405system.ruby.miss_latency_hist_seqr::max_bucket 639
406system.ruby.miss_latency_hist_seqr::samples 1731
407system.ruby.miss_latency_hist_seqr::mean 56.207395
408system.ruby.miss_latency_hist_seqr::gmean 49.560362
409system.ruby.miss_latency_hist_seqr::stdev 35.333412
410system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
411system.ruby.miss_latency_hist_seqr::total 1731
412system.ruby.Directory.incomplete_times_seqr 1730
413system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
414system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
415system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
416system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
417system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
418system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
419system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
420system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
421system.ruby.network.routers0.percent_links_utilized 7.685128
422system.ruby.network.routers0.msg_count.Control::2 1731
423system.ruby.network.routers0.msg_count.Data::2 1727
424system.ruby.network.routers0.msg_count.Response_Data::4 1731
425system.ruby.network.routers0.msg_count.Writeback_Control::3 1727
426system.ruby.network.routers0.msg_bytes.Control::2 13848
427system.ruby.network.routers0.msg_bytes.Data::2 124344
428system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
429system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
430system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
431system.ruby.network.routers1.percent_links_utilized 7.685128
432system.ruby.network.routers1.msg_count.Control::2 1731
433system.ruby.network.routers1.msg_count.Data::2 1727
434system.ruby.network.routers1.msg_count.Response_Data::4 1731
435system.ruby.network.routers1.msg_count.Writeback_Control::3 1727
436system.ruby.network.routers1.msg_bytes.Control::2 13848
437system.ruby.network.routers1.msg_bytes.Data::2 124344
438system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
439system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
440system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
441system.ruby.network.routers2.percent_links_utilized 7.685128
442system.ruby.network.routers2.msg_count.Control::2 1731
443system.ruby.network.routers2.msg_count.Data::2 1727
444system.ruby.network.routers2.msg_count.Response_Data::4 1731
445system.ruby.network.routers2.msg_count.Writeback_Control::3 1727
446system.ruby.network.routers2.msg_bytes.Control::2 13848
447system.ruby.network.routers2.msg_bytes.Data::2 124344
448system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
449system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
450system.ruby.network.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
451system.ruby.network.msg_count.Control 5193
452system.ruby.network.msg_count.Data 5181
453system.ruby.network.msg_count.Response_Data 5193
454system.ruby.network.msg_count.Writeback_Control 5181
455system.ruby.network.msg_byte.Control 41544
456system.ruby.network.msg_byte.Data 373032
457system.ruby.network.msg_byte.Response_Data 373896
458system.ruby.network.msg_byte.Writeback_Control 41448
459system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
460system.ruby.network.routers0.throttle0.link_utilization 7.692239
461system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
462system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
463system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632
464system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816
465system.ruby.network.routers0.throttle1.link_utilization 7.678016
466system.ruby.network.routers0.throttle1.msg_count.Control::2 1731
467system.ruby.network.routers0.throttle1.msg_count.Data::2 1727
468system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848
469system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344
470system.ruby.network.routers1.throttle0.link_utilization 7.678016
471system.ruby.network.routers1.throttle0.msg_count.Control::2 1731
472system.ruby.network.routers1.throttle0.msg_count.Data::2 1727
473system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848
474system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344
475system.ruby.network.routers1.throttle1.link_utilization 7.692239
476system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731
477system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727
478system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632
479system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816
480system.ruby.network.routers2.throttle0.link_utilization 7.692239
481system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731
482system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727
483system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632
484system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816
485system.ruby.network.routers2.throttle1.link_utilization 7.678016
486system.ruby.network.routers2.throttle1.msg_count.Control::2 1731
487system.ruby.network.routers2.throttle1.msg_count.Data::2 1727
488system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848
489system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344
490system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
491system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
492system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1
493system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
494system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1
495system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
496system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
497system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2
498system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
499system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2
500system.ruby.LD.latency_hist_seqr::bucket_size 64
501system.ruby.LD.latency_hist_seqr::max_bucket 639
502system.ruby.LD.latency_hist_seqr::samples 1185
503system.ruby.LD.latency_hist_seqr::mean 33.356118
504system.ruby.LD.latency_hist_seqr::gmean 10.708915
505system.ruby.LD.latency_hist_seqr::stdev 36.387225
506system.ruby.LD.latency_hist_seqr | 862 72.74% 72.74% | 301 25.40% 98.14% | 16 1.35% 99.49% | 3 0.25% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
507system.ruby.LD.latency_hist_seqr::total 1185
508system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
509system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
510system.ruby.LD.hit_latency_hist_seqr::samples 457
511system.ruby.LD.hit_latency_hist_seqr::mean 1
512system.ruby.LD.hit_latency_hist_seqr::gmean 1
513system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
514system.ruby.LD.hit_latency_hist_seqr::total 457
515system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
516system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
517system.ruby.LD.miss_latency_hist_seqr::samples 728
518system.ruby.LD.miss_latency_hist_seqr::mean 53.667582
519system.ruby.LD.miss_latency_hist_seqr::gmean 47.442261
520system.ruby.LD.miss_latency_hist_seqr::stdev 32.940895
521system.ruby.LD.miss_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
522system.ruby.LD.miss_latency_hist_seqr::total 728
523system.ruby.ST.latency_hist_seqr::bucket_size 32
524system.ruby.ST.latency_hist_seqr::max_bucket 319
525system.ruby.ST.latency_hist_seqr::samples 865
526system.ruby.ST.latency_hist_seqr::mean 17.479769
527system.ruby.ST.latency_hist_seqr::gmean 3.361529
528system.ruby.ST.latency_hist_seqr::stdev 31.340829
529system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 160 18.50% 86.94% | 102 11.79% 98.73% | 0 0.00% 98.73% | 4 0.46% 99.19% | 4 0.46% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00%
530system.ruby.ST.latency_hist_seqr::total 865
531system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
532system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
533system.ruby.ST.hit_latency_hist_seqr::samples 592
534system.ruby.ST.hit_latency_hist_seqr::mean 1
535system.ruby.ST.hit_latency_hist_seqr::gmean 1
536system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
537system.ruby.ST.hit_latency_hist_seqr::total 592
538system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
539system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
540system.ruby.ST.miss_latency_hist_seqr::samples 273
541system.ruby.ST.miss_latency_hist_seqr::mean 53.216117
542system.ruby.ST.miss_latency_hist_seqr::gmean 46.594106
543system.ruby.ST.miss_latency_hist_seqr::stdev 35.315815
544system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00%
545system.ruby.ST.miss_latency_hist_seqr::total 273
546system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
547system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
548system.ruby.IFETCH.latency_hist_seqr::samples 6413
549system.ruby.IFETCH.latency_hist_seqr::mean 7.699984
550system.ruby.IFETCH.latency_hist_seqr::gmean 1.571280
551system.ruby.IFETCH.latency_hist_seqr::stdev 22.534194
552system.ruby.IFETCH.latency_hist_seqr | 5994 93.47% 93.47% | 395 6.16% 99.63% | 16 0.25% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
553system.ruby.IFETCH.latency_hist_seqr::total 6413
554system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
555system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
556system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683
557system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
558system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
559system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
560system.ruby.IFETCH.hit_latency_hist_seqr::total 5683
561system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
562system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
563system.ruby.IFETCH.miss_latency_hist_seqr::samples 730
564system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.858904
565system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.975537
566system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.310775
567system.ruby.IFETCH.miss_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
568system.ruby.IFETCH.miss_latency_hist_seqr::total 730
569system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
570system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
571system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731
572system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.207395
573system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.560362
574system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.333412
575system.ruby.Directory.miss_mach_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
576system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731
577system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
578system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
579system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
580system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
581system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
582system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
583system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
--- 14 unchanged lines hidden (view full) ---
598system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
599system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
600system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
601system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
602system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
603system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
604system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
605system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728
606system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.667582
607system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.442261
608system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.940895
609system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
610system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728
611system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
612system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
613system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273
614system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.216117
615system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.594106
616system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.315815
617system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00%
618system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273
619system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
620system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
621system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730
622system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.858904
623system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.975537
624system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.310775
625system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
626system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730
627system.ruby.Directory_Controller.GETX 1731 0.00% 0.00%
628system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00%
629system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00%
630system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00%
631system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00%
632system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00%
633system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00%
--- 19 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000112 # Number of seconds simulated
4sim_ticks 112490 # Number of ticks simulated
5final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000 # Frequency of simulated ticks
7host_inst_rate 94486 # Simulator instruction rate (inst/s)
8host_op_rate 94411 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1658372 # Simulator tick rate (ticks/s)
10host_mem_usage 414356 # Number of bytes of host memory used
11host_seconds 0.07 # Real time elapsed on the host
12sim_insts 6403 # Number of instructions simulated
13sim_ops 6403 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1 # Clock period in ticks
16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
17system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
18system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
19system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
20system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory
21system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory
22system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory
23system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory
24system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory
25system.mem_ctrls.bw_read::ruby.dir_cntrl0 984834207 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrls.bw_read::total 984834207 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrls.bw_write::ruby.dir_cntrl0 982558450 # Write bandwidth from this memory (bytes/s)
28system.mem_ctrls.bw_write::total 982558450 # Write bandwidth from this memory (bytes/s)
29system.mem_ctrls.bw_total::ruby.dir_cntrl0 1967392657 # Total bandwidth to/from this memory (bytes/s)
30system.mem_ctrls.bw_total::total 1967392657 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrls.readReqs 1731 # Number of read requests accepted
32system.mem_ctrls.writeReqs 1727 # Number of write requests accepted
33system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue
34system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue
35system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM
36system.mem_ctrls.bytesReadWrQ 54080 # Total number of bytes read from write queue
37system.mem_ctrls.bytesWritten 57088 # Total number of bytes written to DRAM
38system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side
39system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side
40system.mem_ctrls.servicedByWrQ 845 # Number of DRAM read bursts serviced by the write queue
41system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one
42system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
43system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
44system.mem_ctrls.perBankRdBursts::1 50 # Per bank write bursts
45system.mem_ctrls.perBankRdBursts::2 70 # Per bank write bursts
46system.mem_ctrls.perBankRdBursts::3 63 # Per bank write bursts
47system.mem_ctrls.perBankRdBursts::4 108 # Per bank write bursts
48system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts
49system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
50system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
51system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
52system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
53system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts
54system.mem_ctrls.perBankRdBursts::11 36 # Per bank write bursts
55system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts
56system.mem_ctrls.perBankRdBursts::13 270 # Per bank write bursts
57system.mem_ctrls.perBankRdBursts::14 81 # Per bank write bursts
58system.mem_ctrls.perBankRdBursts::15 24 # Per bank write bursts
59system.mem_ctrls.perBankWrBursts::0 82 # Per bank write bursts
60system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts
61system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts
62system.mem_ctrls.perBankWrBursts::3 60 # Per bank write bursts
63system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts
64system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts
65system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
66system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
67system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
68system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
69system.mem_ctrls.perBankWrBursts::10 50 # Per bank write bursts
70system.mem_ctrls.perBankWrBursts::11 33 # Per bank write bursts
71system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts
72system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts
73system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
74system.mem_ctrls.perBankWrBursts::15 24 # Per bank write bursts
75system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
76system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
77system.mem_ctrls.totGap 112412 # Total gap between requests
78system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
79system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
80system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
81system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
82system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
83system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
84system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2)
85system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
86system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
87system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
88system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
89system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
90system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
91system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2)
92system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see
93system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
94system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
95system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
96system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
97system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
98system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
99system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
100system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
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131system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
132system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
133system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
134system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
135system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
136system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
137system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
138system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
139system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
140system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
141system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see
142system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
143system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see
144system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see
145system.mem_ctrls.wrQLenPdf::21 60 # What write queue length does an incoming req see
146system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
147system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see
148system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see
149system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
150system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
151system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see
152system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
153system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
154system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
155system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see
156system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
157system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
158system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
159system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
160system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
161system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
162system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
163system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
164system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
165system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
--- 14 unchanged lines hidden (view full) ---
180system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
181system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
182system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
183system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
184system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
185system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
186system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
187system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
188system.mem_ctrls.bytesPerActivate::samples 264 # Bytes accessed per row activation
189system.mem_ctrls.bytesPerActivate::mean 424 # Bytes accessed per row activation
190system.mem_ctrls.bytesPerActivate::gmean 260.079273 # Bytes accessed per row activation
191system.mem_ctrls.bytesPerActivate::stdev 372.426347 # Bytes accessed per row activation
192system.mem_ctrls.bytesPerActivate::0-127 66 25.00% 25.00% # Bytes accessed per row activation
193system.mem_ctrls.bytesPerActivate::128-255 58 21.97% 46.97% # Bytes accessed per row activation
194system.mem_ctrls.bytesPerActivate::256-383 27 10.23% 57.20% # Bytes accessed per row activation
195system.mem_ctrls.bytesPerActivate::384-511 16 6.06% 63.26% # Bytes accessed per row activation
196system.mem_ctrls.bytesPerActivate::512-639 17 6.44% 69.70% # Bytes accessed per row activation
197system.mem_ctrls.bytesPerActivate::640-767 8 3.03% 72.73% # Bytes accessed per row activation
198system.mem_ctrls.bytesPerActivate::768-895 12 4.55% 77.27% # Bytes accessed per row activation
199system.mem_ctrls.bytesPerActivate::896-1023 10 3.79% 81.06% # Bytes accessed per row activation
200system.mem_ctrls.bytesPerActivate::1024-1151 50 18.94% 100.00% # Bytes accessed per row activation
201system.mem_ctrls.bytesPerActivate::total 264 # Bytes accessed per row activation
202system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
203system.mem_ctrls.rdPerTurnAround::mean 15.818182 # Reads before turning the bus around for writes
204system.mem_ctrls.rdPerTurnAround::gmean 15.638991 # Reads before turning the bus around for writes
205system.mem_ctrls.rdPerTurnAround::stdev 2.938196 # Reads before turning the bus around for writes
206system.mem_ctrls.rdPerTurnAround::12-13 3 5.45% 5.45% # Reads before turning the bus around for writes
207system.mem_ctrls.rdPerTurnAround::14-15 24 43.64% 49.09% # Reads before turning the bus around for writes
208system.mem_ctrls.rdPerTurnAround::16-17 23 41.82% 90.91% # Reads before turning the bus around for writes
209system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
210system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes
211system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
212system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
213system.mem_ctrls.wrPerTurnAround::mean 16.218182 # Writes before turning the bus around for reads
214system.mem_ctrls.wrPerTurnAround::gmean 16.206001 # Writes before turning the bus around for reads
215system.mem_ctrls.wrPerTurnAround::stdev 0.658025 # Writes before turning the bus around for reads
216system.mem_ctrls.wrPerTurnAround::16 49 89.09% 89.09% # Writes before turning the bus around for reads
217system.mem_ctrls.wrPerTurnAround::17 1 1.82% 90.91% # Writes before turning the bus around for reads
218system.mem_ctrls.wrPerTurnAround::18 4 7.27% 98.18% # Writes before turning the bus around for reads
219system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads
220system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
221system.mem_ctrls.totQLat 16225 # Total ticks spent queuing
222system.mem_ctrls.totMemAccLat 33059 # Total ticks spent from burst creation until serviced by the DRAM
223system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers
224system.mem_ctrls.avgQLat 18.31 # Average queueing delay per DRAM burst
225system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
226system.mem_ctrls.avgMemAccLat 37.31 # Average memory access latency per DRAM burst
227system.mem_ctrls.avgRdBW 504.08 # Average DRAM read bandwidth in MiByte/s
228system.mem_ctrls.avgWrBW 507.49 # Average achieved write bandwidth in MiByte/s
229system.mem_ctrls.avgRdBWSys 984.83 # Average system read bandwidth in MiByte/s
230system.mem_ctrls.avgWrBWSys 982.56 # Average system write bandwidth in MiByte/s
231system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
232system.mem_ctrls.busUtil 7.90 # Data bus utilization in percentage
233system.mem_ctrls.busUtilRead 3.94 # Data bus utilization in percentage for reads
234system.mem_ctrls.busUtilWrite 3.96 # Data bus utilization in percentage for writes
235system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
236system.mem_ctrls.avgWrQLen 26.10 # Average write queue length when enqueuing
237system.mem_ctrls.readRowHits 674 # Number of row buffer hits during reads
238system.mem_ctrls.writeRowHits 833 # Number of row buffer hits during writes
239system.mem_ctrls.readRowHitRate 76.07 # Row buffer hit rate for reads
240system.mem_ctrls.writeRowHitRate 90.15 # Row buffer hit rate for writes
241system.mem_ctrls.avgGap 32.51 # Average gap between requests
242system.mem_ctrls.pageHitRate 83.26 # Row buffer hit rate, read and write combined
243system.mem_ctrls_0.actEnergy 735420 # Energy for activate commands per rank (pJ)
244system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ)
245system.mem_ctrls_0.readEnergy 4581024 # Energy for read commands per rank (pJ)
246system.mem_ctrls_0.writeEnergy 3532896 # Energy for write commands per rank (pJ)
247system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
248system.mem_ctrls_0.actBackEnergy 13923048 # Energy for active background per rank (pJ)
249system.mem_ctrls_0.preBackEnergy 195072 # Energy for precharge background per rank (pJ)
250system.mem_ctrls_0.actPowerDownEnergy 30921360 # Energy for active power-down per rank (pJ)
251system.mem_ctrls_0.prePowerDownEnergy 5237376 # Energy for precharge power-down per rank (pJ)
252system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
253system.mem_ctrls_0.totalEnergy 68117556 # Total energy per rank (pJ)
254system.mem_ctrls_0.averagePower 605.543213 # Core power per rank (mW)
255system.mem_ctrls_0.totalIdleTime 81406 # Total Idle time Per DRAM Rank
256system.mem_ctrls_0.memoryStateTime::IDLE 88 # Time in different power states
257system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states
258system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
259system.mem_ctrls_0.memoryStateTime::PRE_PDN 13639 # Time in different power states
260system.mem_ctrls_0.memoryStateTime::ACT 27313 # Time in different power states
261system.mem_ctrls_0.memoryStateTime::ACT_PDN 67810 # Time in different power states
262system.mem_ctrls_1.actEnergy 1199520 # Energy for activate commands per rank (pJ)
263system.mem_ctrls_1.preEnergy 633696 # Energy for precharge commands per rank (pJ)
264system.mem_ctrls_1.readEnergy 5540640 # Energy for read commands per rank (pJ)
265system.mem_ctrls_1.writeEnergy 3917088 # Energy for write commands per rank (pJ)
266system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
267system.mem_ctrls_1.actBackEnergy 12524952 # Energy for active background per rank (pJ)
268system.mem_ctrls_1.preBackEnergy 314880 # Energy for precharge background per rank (pJ)
269system.mem_ctrls_1.actPowerDownEnergy 33139344 # Energy for active power-down per rank (pJ)
270system.mem_ctrls_1.prePowerDownEnergy 4427136 # Energy for precharge power-down per rank (pJ)
271system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
272system.mem_ctrls_1.totalEnergy 70302216 # Total energy per rank (pJ)
273system.mem_ctrls_1.averagePower 624.964139 # Core power per rank (mW)
274system.mem_ctrls_1.totalIdleTime 83983 # Total Idle time Per DRAM Rank
275system.mem_ctrls_1.memoryStateTime::IDLE 260 # Time in different power states
276system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
277system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
278system.mem_ctrls_1.memoryStateTime::PRE_PDN 11529 # Time in different power states
279system.mem_ctrls_1.memoryStateTime::ACT 24387 # Time in different power states
280system.mem_ctrls_1.memoryStateTime::ACT_PDN 72674 # Time in different power states
281system.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
282system.cpu.clk_domain.clock 1 # Clock period in ticks
283system.cpu.dtb.fetch_hits 0 # ITB hits
284system.cpu.dtb.fetch_misses 0 # ITB misses
285system.cpu.dtb.fetch_acv 0 # ITB acv
286system.cpu.dtb.fetch_accesses 0 # ITB accesses
287system.cpu.dtb.read_hits 1185 # DTB read hits
288system.cpu.dtb.read_misses 7 # DTB read misses
289system.cpu.dtb.read_acv 0 # DTB read access violations
--- 18 unchanged lines hidden (view full) ---
308system.cpu.itb.write_misses 0 # DTB write misses
309system.cpu.itb.write_acv 0 # DTB write access violations
310system.cpu.itb.write_accesses 0 # DTB write accesses
311system.cpu.itb.data_hits 0 # DTB hits
312system.cpu.itb.data_misses 0 # DTB misses
313system.cpu.itb.data_acv 0 # DTB access violations
314system.cpu.itb.data_accesses 0 # DTB accesses
315system.cpu.workload.num_syscalls 17 # Number of system calls
316system.cpu.pwrStateResidencyTicks::ON 112490 # Cumulative time (in ticks) in various power states
317system.cpu.numCycles 112490 # number of cpu cycles simulated
318system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
319system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
320system.cpu.committedInsts 6403 # Number of instructions committed
321system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
322system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
323system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
324system.cpu.num_func_calls 251 # number of times a function call or return occured
325system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
326system.cpu.num_int_insts 6329 # number of integer instructions
327system.cpu.num_fp_insts 10 # number of float instructions
328system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
329system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
330system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
331system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
332system.cpu.num_mem_refs 2060 # number of memory refs
333system.cpu.num_load_insts 1192 # Number of load instructions
334system.cpu.num_store_insts 868 # Number of store instructions
335system.cpu.num_idle_cycles 0 # Number of idle cycles
336system.cpu.num_busy_cycles 112490 # Number of busy cycles
337system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
338system.cpu.idle_fraction 0 # Percentage of idle cycles
339system.cpu.Branches 1056 # Number of branches fetched
340system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
341system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
342system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
343system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
344system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
--- 23 unchanged lines hidden (view full) ---
368system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
369system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
370system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
371system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
372system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
373system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
374system.cpu.op_class::total 6413 # Class of executed instruction
375system.ruby.clk_domain.clock 1 # Clock period in ticks
376system.ruby.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
377system.ruby.delayHist::bucket_size 1 # delay histogram for all message
378system.ruby.delayHist::max_bucket 9 # delay histogram for all message
379system.ruby.delayHist::samples 3458 # delay histogram for all message
380system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
381system.ruby.delayHist::total 3458 # delay histogram for all message
382system.ruby.outstanding_req_hist_seqr::bucket_size 1
383system.ruby.outstanding_req_hist_seqr::max_bucket 9
384system.ruby.outstanding_req_hist_seqr::samples 8464
385system.ruby.outstanding_req_hist_seqr::mean 1
386system.ruby.outstanding_req_hist_seqr::gmean 1
387system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
388system.ruby.outstanding_req_hist_seqr::total 8464
389system.ruby.latency_hist_seqr::bucket_size 64
390system.ruby.latency_hist_seqr::max_bucket 639
391system.ruby.latency_hist_seqr::samples 8463
392system.ruby.latency_hist_seqr::mean 12.291977
393system.ruby.latency_hist_seqr::gmean 2.221869
394system.ruby.latency_hist_seqr::stdev 27.407806
395system.ruby.latency_hist_seqr | 7608 89.90% 89.90% | 798 9.43% 99.33% | 40 0.47% 99.80% | 5 0.06% 99.86% | 6 0.07% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
396system.ruby.latency_hist_seqr::total 8463
397system.ruby.hit_latency_hist_seqr::bucket_size 1
398system.ruby.hit_latency_hist_seqr::max_bucket 9
399system.ruby.hit_latency_hist_seqr::samples 6732
400system.ruby.hit_latency_hist_seqr::mean 1
401system.ruby.hit_latency_hist_seqr::gmean 1
402system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
403system.ruby.hit_latency_hist_seqr::total 6732
404system.ruby.miss_latency_hist_seqr::bucket_size 64
405system.ruby.miss_latency_hist_seqr::max_bucket 639
406system.ruby.miss_latency_hist_seqr::samples 1731
407system.ruby.miss_latency_hist_seqr::mean 56.207395
408system.ruby.miss_latency_hist_seqr::gmean 49.560362
409system.ruby.miss_latency_hist_seqr::stdev 35.333412
410system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
411system.ruby.miss_latency_hist_seqr::total 1731
412system.ruby.Directory.incomplete_times_seqr 1730
413system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
414system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
415system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
416system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
417system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
418system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
419system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
420system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
421system.ruby.network.routers0.percent_links_utilized 7.685128
422system.ruby.network.routers0.msg_count.Control::2 1731
423system.ruby.network.routers0.msg_count.Data::2 1727
424system.ruby.network.routers0.msg_count.Response_Data::4 1731
425system.ruby.network.routers0.msg_count.Writeback_Control::3 1727
426system.ruby.network.routers0.msg_bytes.Control::2 13848
427system.ruby.network.routers0.msg_bytes.Data::2 124344
428system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
429system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
430system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
431system.ruby.network.routers1.percent_links_utilized 7.685128
432system.ruby.network.routers1.msg_count.Control::2 1731
433system.ruby.network.routers1.msg_count.Data::2 1727
434system.ruby.network.routers1.msg_count.Response_Data::4 1731
435system.ruby.network.routers1.msg_count.Writeback_Control::3 1727
436system.ruby.network.routers1.msg_bytes.Control::2 13848
437system.ruby.network.routers1.msg_bytes.Data::2 124344
438system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
439system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
440system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
441system.ruby.network.routers2.percent_links_utilized 7.685128
442system.ruby.network.routers2.msg_count.Control::2 1731
443system.ruby.network.routers2.msg_count.Data::2 1727
444system.ruby.network.routers2.msg_count.Response_Data::4 1731
445system.ruby.network.routers2.msg_count.Writeback_Control::3 1727
446system.ruby.network.routers2.msg_bytes.Control::2 13848
447system.ruby.network.routers2.msg_bytes.Data::2 124344
448system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
449system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
450system.ruby.network.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
451system.ruby.network.msg_count.Control 5193
452system.ruby.network.msg_count.Data 5181
453system.ruby.network.msg_count.Response_Data 5193
454system.ruby.network.msg_count.Writeback_Control 5181
455system.ruby.network.msg_byte.Control 41544
456system.ruby.network.msg_byte.Data 373032
457system.ruby.network.msg_byte.Response_Data 373896
458system.ruby.network.msg_byte.Writeback_Control 41448
459system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
460system.ruby.network.routers0.throttle0.link_utilization 7.692239
461system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
462system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
463system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632
464system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816
465system.ruby.network.routers0.throttle1.link_utilization 7.678016
466system.ruby.network.routers0.throttle1.msg_count.Control::2 1731
467system.ruby.network.routers0.throttle1.msg_count.Data::2 1727
468system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848
469system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344
470system.ruby.network.routers1.throttle0.link_utilization 7.678016
471system.ruby.network.routers1.throttle0.msg_count.Control::2 1731
472system.ruby.network.routers1.throttle0.msg_count.Data::2 1727
473system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848
474system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344
475system.ruby.network.routers1.throttle1.link_utilization 7.692239
476system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731
477system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727
478system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632
479system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816
480system.ruby.network.routers2.throttle0.link_utilization 7.692239
481system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731
482system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727
483system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632
484system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816
485system.ruby.network.routers2.throttle1.link_utilization 7.678016
486system.ruby.network.routers2.throttle1.msg_count.Control::2 1731
487system.ruby.network.routers2.throttle1.msg_count.Data::2 1727
488system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848
489system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344
490system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
491system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
492system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1
493system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
494system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1
495system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
496system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
497system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2
498system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
499system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2
500system.ruby.LD.latency_hist_seqr::bucket_size 64
501system.ruby.LD.latency_hist_seqr::max_bucket 639
502system.ruby.LD.latency_hist_seqr::samples 1185
503system.ruby.LD.latency_hist_seqr::mean 33.356118
504system.ruby.LD.latency_hist_seqr::gmean 10.708915
505system.ruby.LD.latency_hist_seqr::stdev 36.387225
506system.ruby.LD.latency_hist_seqr | 862 72.74% 72.74% | 301 25.40% 98.14% | 16 1.35% 99.49% | 3 0.25% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
507system.ruby.LD.latency_hist_seqr::total 1185
508system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
509system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
510system.ruby.LD.hit_latency_hist_seqr::samples 457
511system.ruby.LD.hit_latency_hist_seqr::mean 1
512system.ruby.LD.hit_latency_hist_seqr::gmean 1
513system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
514system.ruby.LD.hit_latency_hist_seqr::total 457
515system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
516system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
517system.ruby.LD.miss_latency_hist_seqr::samples 728
518system.ruby.LD.miss_latency_hist_seqr::mean 53.667582
519system.ruby.LD.miss_latency_hist_seqr::gmean 47.442261
520system.ruby.LD.miss_latency_hist_seqr::stdev 32.940895
521system.ruby.LD.miss_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
522system.ruby.LD.miss_latency_hist_seqr::total 728
523system.ruby.ST.latency_hist_seqr::bucket_size 32
524system.ruby.ST.latency_hist_seqr::max_bucket 319
525system.ruby.ST.latency_hist_seqr::samples 865
526system.ruby.ST.latency_hist_seqr::mean 17.479769
527system.ruby.ST.latency_hist_seqr::gmean 3.361529
528system.ruby.ST.latency_hist_seqr::stdev 31.340829
529system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 160 18.50% 86.94% | 102 11.79% 98.73% | 0 0.00% 98.73% | 4 0.46% 99.19% | 4 0.46% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00%
530system.ruby.ST.latency_hist_seqr::total 865
531system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
532system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
533system.ruby.ST.hit_latency_hist_seqr::samples 592
534system.ruby.ST.hit_latency_hist_seqr::mean 1
535system.ruby.ST.hit_latency_hist_seqr::gmean 1
536system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
537system.ruby.ST.hit_latency_hist_seqr::total 592
538system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
539system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
540system.ruby.ST.miss_latency_hist_seqr::samples 273
541system.ruby.ST.miss_latency_hist_seqr::mean 53.216117
542system.ruby.ST.miss_latency_hist_seqr::gmean 46.594106
543system.ruby.ST.miss_latency_hist_seqr::stdev 35.315815
544system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00%
545system.ruby.ST.miss_latency_hist_seqr::total 273
546system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
547system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
548system.ruby.IFETCH.latency_hist_seqr::samples 6413
549system.ruby.IFETCH.latency_hist_seqr::mean 7.699984
550system.ruby.IFETCH.latency_hist_seqr::gmean 1.571280
551system.ruby.IFETCH.latency_hist_seqr::stdev 22.534194
552system.ruby.IFETCH.latency_hist_seqr | 5994 93.47% 93.47% | 395 6.16% 99.63% | 16 0.25% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
553system.ruby.IFETCH.latency_hist_seqr::total 6413
554system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
555system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
556system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683
557system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
558system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
559system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
560system.ruby.IFETCH.hit_latency_hist_seqr::total 5683
561system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
562system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
563system.ruby.IFETCH.miss_latency_hist_seqr::samples 730
564system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.858904
565system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.975537
566system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.310775
567system.ruby.IFETCH.miss_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
568system.ruby.IFETCH.miss_latency_hist_seqr::total 730
569system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
570system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
571system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731
572system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.207395
573system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.560362
574system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.333412
575system.ruby.Directory.miss_mach_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
576system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731
577system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
578system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
579system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
580system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan
581system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
582system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1
583system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1
--- 14 unchanged lines hidden (view full) ---
598system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75
599system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000
600system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
601system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
602system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
603system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
604system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
605system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728
606system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.667582
607system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.442261
608system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.940895
609system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
610system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728
611system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
612system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
613system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273
614system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.216117
615system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.594106
616system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.315815
617system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00%
618system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273
619system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
620system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
621system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730
622system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.858904
623system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.975537
624system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.310775
625system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
626system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730
627system.ruby.Directory_Controller.GETX 1731 0.00% 0.00%
628system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00%
629system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00%
630system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00%
631system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00%
632system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00%
633system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00%
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