| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16032500 # Number of ticks simulated 5final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 20632000 # Number of ticks simulated 5final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 34765 # Simulator instruction rate (inst/s) 8host_op_rate 34761 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 87452252 # Simulator tick rate (ticks/s) 10host_mem_usage 269696 # Number of bytes of host memory used 11host_seconds 0.18 # Real time elapsed on the host | 7host_inst_rate 1782 # Simulator instruction rate (inst/s) 8host_op_rate 1782 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5769044 # Simulator tick rate (ticks/s) 10host_mem_usage 227476 # Number of bytes of host memory used 11host_seconds 3.58 # Real time elapsed on the host |
| 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated | 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::total 31104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory | 16system.physmem.bytes_read::total 31168 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory |
| 20system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory | 20system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory |
| 21system.physmem.num_reads::total 486 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 486 # Total number of read requests seen | 21system.physmem.num_reads::total 487 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 488 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 31104 # Total number of bytes read from memory | 32system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 31168 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 15819000 # Total gap between requests | 73system.physmem.totGap 20599000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 486 # Categorize read packet sizes | 80system.physmem.readPktSize::6 488 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see |
| 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 2907500 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests 154system.physmem.totBusLat 2430000 # Total cycles spent in databus access 155system.physmem.totBankLat 8305000 # Total cycles spent in bank access 156system.physmem.avgQLat 5982.51 # Average queueing delay per request 157system.physmem.avgBankLat 17088.48 # Average bank access latency per request | 152system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation 171system.physmem.totQLat 2633750 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests 173system.physmem.totBusLat 2440000 # Total cycles spent in databus access 174system.physmem.totBankLat 7562500 # Total cycles spent in bank access 175system.physmem.avgQLat 5397.03 # Average queueing delay per request 176system.physmem.avgBankLat 15496.93 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 177system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 28070.99 # Average memory access latency 160system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s | 178system.physmem.avgMemAccLat 25893.95 # Average memory access latency 179system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 180system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s | 181system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 182system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 165system.physmem.busUtil 15.16 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.85 # Average read queue length over time | 184system.physmem.busUtil 11.80 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.61 # Average read queue length over time |
| 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 186system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 396 # Number of row buffer hits during reads | 187system.physmem.readRowHits 419 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 188system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads | 189system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 32549.38 # Average gap between requests 173system.cpu.branchPred.lookups 2896 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 746 # Number of BTB hits | 191system.physmem.avgGap 42211.07 # Average gap between requests 192system.membus.throughput 1510663048 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 415 # Transaction distribution 194system.membus.trans_dist::ReadResp 414 # Transaction distribution 195system.membus.trans_dist::ReadExReq 73 # Transaction distribution 196system.membus.trans_dist::ReadExResp 73 # Transaction distribution 197system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 975 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) 201system.membus.data_through_bus 31168 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 205system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 22.1 # Layer utilization (%) 207system.cpu.branchPred.lookups 2906 # Number of BP lookups 208system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted 209system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect 210system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups 211system.cpu.branchPred.BTBHits 759 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 212system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. | 213system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage 214system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. |
| 181system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 182system.cpu.dtb.fetch_hits 0 # ITB hits 183system.cpu.dtb.fetch_misses 0 # ITB misses 184system.cpu.dtb.fetch_acv 0 # ITB acv 185system.cpu.dtb.fetch_accesses 0 # ITB accesses | 215system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 216system.cpu.dtb.fetch_hits 0 # ITB hits 217system.cpu.dtb.fetch_misses 0 # ITB misses 218system.cpu.dtb.fetch_acv 0 # ITB acv 219system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 186system.cpu.dtb.read_hits 2071 # DTB read hits 187system.cpu.dtb.read_misses 50 # DTB read misses | 220system.cpu.dtb.read_hits 2097 # DTB read hits 221system.cpu.dtb.read_misses 47 # DTB read misses |
| 188system.cpu.dtb.read_acv 0 # DTB read access violations | 222system.cpu.dtb.read_acv 0 # DTB read access violations |
| 189system.cpu.dtb.read_accesses 2121 # DTB read accesses 190system.cpu.dtb.write_hits 1069 # DTB write hits 191system.cpu.dtb.write_misses 30 # DTB write misses | 223system.cpu.dtb.read_accesses 2144 # DTB read accesses 224system.cpu.dtb.write_hits 1063 # DTB write hits 225system.cpu.dtb.write_misses 31 # DTB write misses |
| 192system.cpu.dtb.write_acv 0 # DTB write access violations | 226system.cpu.dtb.write_acv 0 # DTB write access violations |
| 193system.cpu.dtb.write_accesses 1099 # DTB write accesses 194system.cpu.dtb.data_hits 3140 # DTB hits 195system.cpu.dtb.data_misses 80 # DTB misses | 227system.cpu.dtb.write_accesses 1094 # DTB write accesses 228system.cpu.dtb.data_hits 3160 # DTB hits 229system.cpu.dtb.data_misses 78 # DTB misses |
| 196system.cpu.dtb.data_acv 0 # DTB access violations | 230system.cpu.dtb.data_acv 0 # DTB access violations |
| 197system.cpu.dtb.data_accesses 3220 # DTB accesses 198system.cpu.itb.fetch_hits 2349 # ITB hits 199system.cpu.itb.fetch_misses 38 # ITB misses | 231system.cpu.dtb.data_accesses 3238 # DTB accesses 232system.cpu.itb.fetch_hits 2393 # ITB hits 233system.cpu.itb.fetch_misses 39 # ITB misses |
| 200system.cpu.itb.fetch_acv 0 # ITB acv | 234system.cpu.itb.fetch_acv 0 # ITB acv |
| 201system.cpu.itb.fetch_accesses 2387 # ITB accesses | 235system.cpu.itb.fetch_accesses 2432 # ITB accesses |
| 202system.cpu.itb.read_hits 0 # DTB read hits 203system.cpu.itb.read_misses 0 # DTB read misses 204system.cpu.itb.read_acv 0 # DTB read access violations 205system.cpu.itb.read_accesses 0 # DTB read accesses 206system.cpu.itb.write_hits 0 # DTB write hits 207system.cpu.itb.write_misses 0 # DTB write misses 208system.cpu.itb.write_acv 0 # DTB write access violations 209system.cpu.itb.write_accesses 0 # DTB write accesses 210system.cpu.itb.data_hits 0 # DTB hits 211system.cpu.itb.data_misses 0 # DTB misses 212system.cpu.itb.data_acv 0 # DTB access violations 213system.cpu.itb.data_accesses 0 # DTB accesses 214system.cpu.workload.num_syscalls 17 # Number of system calls | 236system.cpu.itb.read_hits 0 # DTB read hits 237system.cpu.itb.read_misses 0 # DTB read misses 238system.cpu.itb.read_acv 0 # DTB read access violations 239system.cpu.itb.read_accesses 0 # DTB read accesses 240system.cpu.itb.write_hits 0 # DTB write hits 241system.cpu.itb.write_misses 0 # DTB write misses 242system.cpu.itb.write_acv 0 # DTB write access violations 243system.cpu.itb.write_accesses 0 # DTB write accesses 244system.cpu.itb.data_hits 0 # DTB hits 245system.cpu.itb.data_misses 0 # DTB misses 246system.cpu.itb.data_acv 0 # DTB access violations 247system.cpu.itb.data_accesses 0 # DTB accesses 248system.cpu.workload.num_syscalls 17 # Number of system calls |
| 215system.cpu.numCycles 32066 # number of cpu cycles simulated | 249system.cpu.numCycles 41265 # number of cpu cycles simulated |
| 216system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 217system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 250system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 251system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 218system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss 219system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed 220system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered 221system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken 222system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked 223system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing 224system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked 225system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 226system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps 227system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched 228system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed 229system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total) | 252system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss 253system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed 254system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered 255system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 256system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked 257system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing 258system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked 259system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 260system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps 261system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched 262system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed 263system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total) |
| 232system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 266system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 233system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) 237system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) 240system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total) 241system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) | 267system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total) |
| 242system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 276system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 245system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle 247system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle 248system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle 249system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked 250system.cpu.decode.RunCycles 2752 # Number of cycles decode is running 251system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking 252system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing 253system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch 254system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction 255system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode 256system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode 257system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing 258system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle 259system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking 260system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst 261system.cpu.rename.RunCycles 2630 # Number of cycles rename is running 262system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking 263system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename | 279system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle 281system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle 282system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle 283system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked 284system.cpu.decode.RunCycles 2793 # Number of cycles decode is running 285system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking 286system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing 287system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch 288system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 289system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode 290system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 291system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing 292system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle 293system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking 294system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst 295system.cpu.rename.RunCycles 2621 # Number of cycles rename is running 296system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking 297system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename 298system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full |
| 264system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full | 299system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full |
| 265system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full 266system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed 267system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made 268system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups | 300system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full 301system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed 302system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made 303system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups |
| 269system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 270system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed | 304system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 305system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed |
| 271system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing | 306system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing |
| 272system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 273system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed | 307system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 308system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed |
| 274system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer 275system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. 276system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. | 309system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer 310system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit. 311system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit. |
| 277system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 278system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 312system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 313system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 279system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) 280system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 281system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued 282system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued 283system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling 284system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph 285system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 286system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle | 314system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec) 315system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ 316system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued 317system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued 318system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling 319system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph 320system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 321system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle |
| 289system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 324system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 290system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle 292system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle 293system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle 294system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle 295system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle 297system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle 298system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle | 325system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle |
| 299system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 334system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 302system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle | 337system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle |
| 303system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 338system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 304system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available 305system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available 306system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available 307system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available 308system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available 309system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available 310system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available 311system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available 312system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available 323system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available 324system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available 325system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available 333system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available 334system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available | 339system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available 340system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available 341system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available 346system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available 347system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available 368system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available 369system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available |
| 335system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 336system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 337system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 370system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 371system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 372system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 338system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued 339system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued 340system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued 341system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued 342system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued 343system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued 344system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued 345system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued 346system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued 357system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued 358system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued 359system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued 360system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued 367system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued 368system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued | 373system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued 374system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued 375system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued 381system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued 402system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued 403system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued |
| 369system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 370system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 404system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 405system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 371system.cpu.iq.FU_type_0::total 10806 # Type of FU issued 372system.cpu.iq.rate 0.336992 # Inst issue rate 373system.cpu.iq.fu_busy_cnt 118 # FU busy when requested 374system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) 375system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads 376system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes 377system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses | 406system.cpu.iq.FU_type_0::total 10814 # Type of FU issued 407system.cpu.iq.rate 0.262062 # Inst issue rate 408system.cpu.iq.fu_busy_cnt 111 # FU busy when requested 409system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst) 410system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads 411system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes 412system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses |
| 378system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 379system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 380system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses | 413system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 414system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 415system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
| 381system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses | 416system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses |
| 382system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses | 417system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses |
| 383system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores | 418system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores |
| 384system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 419system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 385system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed | 420system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed |
| 386system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 387system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations | 421system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 422system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations |
| 388system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed | 423system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed |
| 389system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 390system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 391system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 424system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 425system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 426system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 392system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked | 427system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked |
| 393system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 428system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 394system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing 395system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking 396system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking 397system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ 398system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch 399system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions 400system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions 401system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions | 429system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing 430system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking 431system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 432system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ 433system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch 434system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions 435system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions 436system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions |
| 402system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 403system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 404system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations | 437system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 438system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 439system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations |
| 405system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly 406system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly 407system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute 408system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions 409system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed 410system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute | 440system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly 441system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly 442system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute 443system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions 444system.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed 445system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute |
| 411system.cpu.iew.exec_swp 0 # number of swp insts executed | 446system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 412system.cpu.iew.exec_nop 86 # number of nop insts executed 413system.cpu.iew.exec_refs 3233 # number of memory reference insts executed 414system.cpu.iew.exec_branches 1613 # Number of branches executed 415system.cpu.iew.exec_stores 1101 # Number of stores executed 416system.cpu.iew.exec_rate 0.316628 # Inst execution rate 417system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit 418system.cpu.iew.wb_count 9709 # cumulative count of insts written-back 419system.cpu.iew.wb_producers 5133 # num instructions producing a value 420system.cpu.iew.wb_consumers 6918 # num instructions consuming a value | 447system.cpu.iew.exec_nop 89 # number of nop insts executed 448system.cpu.iew.exec_refs 3251 # number of memory reference insts executed 449system.cpu.iew.exec_branches 1595 # Number of branches executed 450system.cpu.iew.exec_stores 1096 # Number of stores executed 451system.cpu.iew.exec_rate 0.245147 # Inst execution rate 452system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit 453system.cpu.iew.wb_count 9641 # cumulative count of insts written-back 454system.cpu.iew.wb_producers 5053 # num instructions producing a value 455system.cpu.iew.wb_consumers 6805 # num instructions consuming a value |
| 421system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 456system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 422system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle 423system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back | 457system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle 458system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back |
| 424system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 459system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 425system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit | 460system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit |
| 426system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards | 461system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards |
| 427system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted 428system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle | 462system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted 463system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle |
| 431system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 466system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 432system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle 434system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle 435system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle 436system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle 437system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle 438system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle 439system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle 440system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle | 467system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle |
| 441system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 476system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 444system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle | 479system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle |
| 445system.cpu.commit.committedInsts 6389 # Number of instructions committed 446system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 447system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 448system.cpu.commit.refs 2048 # Number of memory references committed 449system.cpu.commit.loads 1183 # Number of loads committed 450system.cpu.commit.membars 0 # Number of memory barriers committed 451system.cpu.commit.branches 1050 # Number of branches committed 452system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 453system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 454system.cpu.commit.function_calls 127 # Number of function calls committed. | 480system.cpu.commit.committedInsts 6389 # Number of instructions committed 481system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 482system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 483system.cpu.commit.refs 2048 # Number of memory references committed 484system.cpu.commit.loads 1183 # Number of loads committed 485system.cpu.commit.membars 0 # Number of memory barriers committed 486system.cpu.commit.branches 1050 # Number of branches committed 487system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 488system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 489system.cpu.commit.function_calls 127 # Number of function calls committed. |
| 455system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached | 490system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached |
| 456system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 491system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 457system.cpu.rob.rob_reads 25930 # The number of ROB reads 458system.cpu.rob.rob_writes 27481 # The number of ROB writes 459system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself 460system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling | 492system.cpu.rob.rob_reads 26491 # The number of ROB reads 493system.cpu.rob.rob_writes 27437 # The number of ROB writes 494system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself 495system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 461system.cpu.committedInsts 6372 # Number of Instructions Simulated 462system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 463system.cpu.committedInsts_total 6372 # Number of Instructions Simulated | 496system.cpu.committedInsts 6372 # Number of Instructions Simulated 497system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 498system.cpu.committedInsts_total 6372 # Number of Instructions Simulated |
| 464system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction 465system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads 466system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle 467system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads 468system.cpu.int_regfile_reads 12887 # number of integer regfile reads 469system.cpu.int_regfile_writes 7342 # number of integer regfile writes | 499system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction 500system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads 501system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle 502system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads 503system.cpu.int_regfile_reads 12831 # number of integer regfile reads 504system.cpu.int_regfile_writes 7294 # number of integer regfile writes |
| 470system.cpu.fp_regfile_reads 8 # number of floating regfile reads 471system.cpu.fp_regfile_writes 2 # number of floating regfile writes 472system.cpu.misc_regfile_reads 1 # number of misc regfile reads 473system.cpu.misc_regfile_writes 1 # number of misc regfile writes | 505system.cpu.fp_regfile_reads 8 # number of floating regfile reads 506system.cpu.fp_regfile_writes 2 # number of floating regfile writes 507system.cpu.misc_regfile_reads 1 # number of misc regfile reads 508system.cpu.misc_regfile_writes 1 # number of misc regfile writes |
| 509system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s) 510system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 511system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 512system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 513system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 514system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes) 515system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes) 516system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes) 517system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes) 518system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) 519system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes) 520system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 521system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 522system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 523system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 524system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) 525system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) 526system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks) 527system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) |
|
| 474system.cpu.icache.replacements 0 # number of replacements | 528system.cpu.icache.replacements 0 # number of replacements |
| 475system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use 476system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. 477system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. 478system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. | 529system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use 530system.cpu.icache.total_refs 1903 # Total number of references to valid blocks. 531system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. 532system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks. |
| 479system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 533system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 480system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor 481system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy 482system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy 483system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits 484system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits 485system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits 486system.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits 487system.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits 488system.cpu.icache.overall_hits::total 1869 # number of overall hits 489system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses 490system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses 491system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses 492system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses 493system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses 494system.cpu.icache.overall_misses::total 480 # number of overall misses 495system.cpu.icache.ReadReq_miss_latency::cpu.inst 22201500 # number of ReadReq miss cycles 496system.cpu.icache.ReadReq_miss_latency::total 22201500 # number of ReadReq miss cycles 497system.cpu.icache.demand_miss_latency::cpu.inst 22201500 # number of demand (read+write) miss cycles 498system.cpu.icache.demand_miss_latency::total 22201500 # number of demand (read+write) miss cycles 499system.cpu.icache.overall_miss_latency::cpu.inst 22201500 # number of overall miss cycles 500system.cpu.icache.overall_miss_latency::total 22201500 # number of overall miss cycles 501system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) 502system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) 503system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses 504system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses 505system.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses 506system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses 507system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses 508system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses 509system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses 510system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses 511system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses 512system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses 513system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.125000 # average ReadReq miss latency 514system.cpu.icache.ReadReq_avg_miss_latency::total 46253.125000 # average ReadReq miss latency 515system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency 516system.cpu.icache.demand_avg_miss_latency::total 46253.125000 # average overall miss latency 517system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency 518system.cpu.icache.overall_avg_miss_latency::total 46253.125000 # average overall miss latency | 534system.cpu.icache.occ_blocks::cpu.inst 159.617277 # Average occupied blocks per requestor 535system.cpu.icache.occ_percent::cpu.inst 0.077938 # Average percentage of cache occupancy 536system.cpu.icache.occ_percent::total 0.077938 # Average percentage of cache occupancy 537system.cpu.icache.ReadReq_hits::cpu.inst 1903 # number of ReadReq hits 538system.cpu.icache.ReadReq_hits::total 1903 # number of ReadReq hits 539system.cpu.icache.demand_hits::cpu.inst 1903 # number of demand (read+write) hits 540system.cpu.icache.demand_hits::total 1903 # number of demand (read+write) hits 541system.cpu.icache.overall_hits::cpu.inst 1903 # number of overall hits 542system.cpu.icache.overall_hits::total 1903 # number of overall hits 543system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses 544system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses 545system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses 546system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses 547system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses 548system.cpu.icache.overall_misses::total 490 # number of overall misses 549system.cpu.icache.ReadReq_miss_latency::cpu.inst 30064500 # number of ReadReq miss cycles 550system.cpu.icache.ReadReq_miss_latency::total 30064500 # number of ReadReq miss cycles 551system.cpu.icache.demand_miss_latency::cpu.inst 30064500 # number of demand (read+write) miss cycles 552system.cpu.icache.demand_miss_latency::total 30064500 # number of demand (read+write) miss cycles 553system.cpu.icache.overall_miss_latency::cpu.inst 30064500 # number of overall miss cycles 554system.cpu.icache.overall_miss_latency::total 30064500 # number of overall miss cycles 555system.cpu.icache.ReadReq_accesses::cpu.inst 2393 # number of ReadReq accesses(hits+misses) 556system.cpu.icache.ReadReq_accesses::total 2393 # number of ReadReq accesses(hits+misses) 557system.cpu.icache.demand_accesses::cpu.inst 2393 # number of demand (read+write) accesses 558system.cpu.icache.demand_accesses::total 2393 # number of demand (read+write) accesses 559system.cpu.icache.overall_accesses::cpu.inst 2393 # number of overall (read+write) accesses 560system.cpu.icache.overall_accesses::total 2393 # number of overall (read+write) accesses 561system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204764 # miss rate for ReadReq accesses 562system.cpu.icache.ReadReq_miss_rate::total 0.204764 # miss rate for ReadReq accesses 563system.cpu.icache.demand_miss_rate::cpu.inst 0.204764 # miss rate for demand accesses 564system.cpu.icache.demand_miss_rate::total 0.204764 # miss rate for demand accesses 565system.cpu.icache.overall_miss_rate::cpu.inst 0.204764 # miss rate for overall accesses 566system.cpu.icache.overall_miss_rate::total 0.204764 # miss rate for overall accesses 567system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61356.122449 # average ReadReq miss latency 568system.cpu.icache.ReadReq_avg_miss_latency::total 61356.122449 # average ReadReq miss latency 569system.cpu.icache.demand_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency 570system.cpu.icache.demand_avg_miss_latency::total 61356.122449 # average overall miss latency 571system.cpu.icache.overall_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency 572system.cpu.icache.overall_avg_miss_latency::total 61356.122449 # average overall miss latency |
| 519system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 520system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 521system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 522system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 523system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 524system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 525system.cpu.icache.fast_writes 0 # number of fast writes performed 526system.cpu.icache.cache_copies 0 # number of cache copies performed | 573system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 574system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 575system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 576system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 577system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 578system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 579system.cpu.icache.fast_writes 0 # number of fast writes performed 580system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 527system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits 528system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits 529system.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits 530system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits 531system.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits 532system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits 533system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 534system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 535system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 536system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 537system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 538system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 539system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16101000 # number of ReadReq MSHR miss cycles 540system.cpu.icache.ReadReq_mshr_miss_latency::total 16101000 # number of ReadReq MSHR miss cycles 541system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16101000 # number of demand (read+write) MSHR miss cycles 542system.cpu.icache.demand_mshr_miss_latency::total 16101000 # number of demand (read+write) MSHR miss cycles 543system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16101000 # number of overall MSHR miss cycles 544system.cpu.icache.overall_mshr_miss_latency::total 16101000 # number of overall MSHR miss cycles 545system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses 546system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses 547system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses 548system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses 549system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses 550system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses 551system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51440.894569 # average ReadReq mshr miss latency 552system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51440.894569 # average ReadReq mshr miss latency 553system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency 554system.cpu.icache.demand_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency 555system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency 556system.cpu.icache.overall_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency | 581system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits 582system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits 583system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits 584system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits 585system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits 586system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 587system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 588system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 589system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 590system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 591system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 592system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 593system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21382000 # number of ReadReq MSHR miss cycles 594system.cpu.icache.ReadReq_mshr_miss_latency::total 21382000 # number of ReadReq MSHR miss cycles 595system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21382000 # number of demand (read+write) MSHR miss cycles 596system.cpu.icache.demand_mshr_miss_latency::total 21382000 # number of demand (read+write) MSHR miss cycles 597system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21382000 # number of overall MSHR miss cycles 598system.cpu.icache.overall_mshr_miss_latency::total 21382000 # number of overall MSHR miss cycles 599system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for ReadReq accesses 600system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131634 # mshr miss rate for ReadReq accesses 601system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for demand accesses 602system.cpu.icache.demand_mshr_miss_rate::total 0.131634 # mshr miss rate for demand accesses 603system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for overall accesses 604system.cpu.icache.overall_mshr_miss_rate::total 0.131634 # mshr miss rate for overall accesses 605system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67879.365079 # average ReadReq mshr miss latency 606system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67879.365079 # average ReadReq mshr miss latency 607system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency 608system.cpu.icache.demand_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency 609system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency 610system.cpu.icache.overall_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency |
| 557system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 558system.cpu.l2cache.replacements 0 # number of replacements | 611system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 612system.cpu.l2cache.replacements 0 # number of replacements |
| 559system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use | 613system.cpu.l2cache.tagsinuse 219.419406 # Cycle average of tags in use |
| 560system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. | 614system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. |
| 561system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. 562system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. | 615system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. 616system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. |
| 563system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 617system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 564system.cpu.l2cache.occ_blocks::cpu.inst 159.327579 # Average occupied blocks per requestor 565system.cpu.l2cache.occ_blocks::cpu.data 60.315874 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy 567system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 568system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy | 618system.cpu.l2cache.occ_blocks::cpu.inst 159.699673 # Average occupied blocks per requestor 619system.cpu.l2cache.occ_blocks::cpu.data 59.719733 # Average occupied blocks per requestor 620system.cpu.l2cache.occ_percent::cpu.inst 0.004874 # Average percentage of cache occupancy 621system.cpu.l2cache.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy 622system.cpu.l2cache.occ_percent::total 0.006696 # Average percentage of cache occupancy |
| 569system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 570system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 571system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 573system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 574system.cpu.l2cache.overall_hits::total 1 # number of overall hits | 623system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 624system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 625system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 626system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 627system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 628system.cpu.l2cache.overall_hits::total 1 # number of overall hits |
| 575system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses | 629system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses |
| 576system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses | 630system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses |
| 577system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses | 631system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses |
| 578system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 579system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses | 632system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 633system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses |
| 580system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses | 634system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses |
| 581system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses | 635system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses |
| 582system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses 583system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses | 636system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 637system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses |
| 584system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses | 638system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses |
| 585system.cpu.l2cache.overall_misses::total 486 # number of overall misses 586system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15776000 # number of ReadReq miss cycles 587system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles 588system.cpu.l2cache.ReadReq_miss_latency::total 21856500 # number of ReadReq miss cycles 589system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles 590system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles 591system.cpu.l2cache.demand_miss_latency::cpu.inst 15776000 # number of demand (read+write) miss cycles 592system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles 593system.cpu.l2cache.demand_miss_latency::total 25544000 # number of demand (read+write) miss cycles 594system.cpu.l2cache.overall_miss_latency::cpu.inst 15776000 # number of overall miss cycles 595system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles 596system.cpu.l2cache.overall_miss_latency::total 25544000 # number of overall miss cycles 597system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) | 639system.cpu.l2cache.overall_misses::total 488 # number of overall misses 640system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21056000 # number of ReadReq miss cycles 641system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8037000 # number of ReadReq miss cycles 642system.cpu.l2cache.ReadReq_miss_latency::total 29093000 # number of ReadReq miss cycles 643system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5106500 # number of ReadExReq miss cycles 644system.cpu.l2cache.ReadExReq_miss_latency::total 5106500 # number of ReadExReq miss cycles 645system.cpu.l2cache.demand_miss_latency::cpu.inst 21056000 # number of demand (read+write) miss cycles 646system.cpu.l2cache.demand_miss_latency::cpu.data 13143500 # number of demand (read+write) miss cycles 647system.cpu.l2cache.demand_miss_latency::total 34199500 # number of demand (read+write) miss cycles 648system.cpu.l2cache.overall_miss_latency::cpu.inst 21056000 # number of overall miss cycles 649system.cpu.l2cache.overall_miss_latency::cpu.data 13143500 # number of overall miss cycles 650system.cpu.l2cache.overall_miss_latency::total 34199500 # number of overall miss cycles 651system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) |
| 598system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) | 652system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) |
| 599system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) | 653system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) |
| 600system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 601system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) | 654system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 655system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) |
| 602system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses | 656system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses |
| 603system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses | 657system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses |
| 604system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses 605system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses | 658system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 659system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses |
| 606system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses | 660system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses |
| 607system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses 608system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses | 661system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 662system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses |
| 609system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses | 663system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 610system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses | 664system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses |
| 611system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 612system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 665system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 666system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 613system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses | 667system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses |
| 614system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 668system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 615system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses 616system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses | 669system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 670system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses |
| 617system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 671system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 618system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses 619system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50564.102564 # average ReadReq miss latency 620system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency 621system.cpu.l2cache.ReadReq_avg_miss_latency::total 52921.307506 # average ReadReq miss latency 622system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency 623system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency 624system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50564.102564 # average overall miss latency 625system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency 626system.cpu.l2cache.demand_avg_miss_latency::total 52559.670782 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50564.102564 # average overall miss latency 628system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency 629system.cpu.l2cache.overall_avg_miss_latency::total 52559.670782 # average overall miss latency | 672system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 673system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67057.324841 # average ReadReq miss latency 674system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79574.257426 # average ReadReq miss latency 675system.cpu.l2cache.ReadReq_avg_miss_latency::total 70103.614458 # average ReadReq miss latency 676system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69952.054795 # average ReadExReq miss latency 677system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69952.054795 # average ReadExReq miss latency 678system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency 679system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency 680system.cpu.l2cache.demand_avg_miss_latency::total 70080.942623 # average overall miss latency 681system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency 682system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency 683system.cpu.l2cache.overall_avg_miss_latency::total 70080.942623 # average overall miss latency |
| 630system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.l2cache.fast_writes 0 # number of fast writes performed 637system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 684system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 685system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 686system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 687system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 688system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 689system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 690system.cpu.l2cache.fast_writes 0 # number of fast writes performed 691system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 638system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses | 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses |
| 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses | 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses |
| 640system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses | 694system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses |
| 641system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 642system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses | 695system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 696system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses |
| 643system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses | 697system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses |
| 644system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses | 698system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses |
| 645system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses | 699system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses |
| 647system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses | 701system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses |
| 648system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses 649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11906745 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16755536 # number of ReadReq MSHR miss cycles 652system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11906745 # number of demand (read+write) MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::total 19551317 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11906745 # number of overall MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::total 19551317 # number of overall MSHR miss cycles 660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses | 702system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 703system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17174500 # number of ReadReq MSHR miss cycles 704system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6801500 # number of ReadReq MSHR miss cycles 705system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23976000 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4212000 # number of ReadExReq MSHR miss cycles 707system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4212000 # number of ReadExReq MSHR miss cycles 708system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17174500 # number of demand (read+write) MSHR miss cycles 709system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11013500 # number of demand (read+write) MSHR miss cycles 710system.cpu.l2cache.demand_mshr_miss_latency::total 28188000 # number of demand (read+write) MSHR miss cycles 711system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17174500 # number of overall MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11013500 # number of overall MSHR miss cycles 713system.cpu.l2cache.overall_mshr_miss_latency::total 28188000 # number of overall MSHR miss cycles 714system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses |
| 661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses | 715system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 662system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses | 716system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses |
| 663system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 664system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 717system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 718system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 665system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses | 719system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses |
| 666system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 720system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 667system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses 668system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses | 721system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 722system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses |
| 669system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 670system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses 671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.644231 # average ReadReq mshr miss latency 672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency 673system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40570.305085 # average ReadReq mshr miss latency 674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency 675system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency 678system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency 681system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency | 724system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 725system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54695.859873 # average ReadReq mshr miss latency 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67341.584158 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57773.493976 # average ReadReq mshr miss latency 728system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57698.630137 # average ReadExReq mshr miss latency 729system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57698.630137 # average ReadExReq mshr miss latency 730system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency 731system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency 732system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency 733system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency 734system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency 735system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency |
| 682system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 683system.cpu.dcache.replacements 0 # number of replacements | 736system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 737system.cpu.dcache.replacements 0 # number of replacements |
| 684system.cpu.dcache.tagsinuse 107.714584 # Cycle average of tags in use 685system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. | 738system.cpu.dcache.tagsinuse 106.967869 # Cycle average of tags in use 739system.cpu.dcache.total_refs 2246 # Total number of references to valid blocks. |
| 686system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. | 740system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. |
| 687system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. | 741system.cpu.dcache.avg_refs 12.908046 # Average number of references to valid blocks. |
| 688system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 742system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 689system.cpu.dcache.occ_blocks::cpu.data 107.714584 # Average occupied blocks per requestor 690system.cpu.dcache.occ_percent::cpu.data 0.026298 # Average percentage of cache occupancy 691system.cpu.dcache.occ_percent::total 0.026298 # Average percentage of cache occupancy 692system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits 693system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits | 743system.cpu.dcache.occ_blocks::cpu.data 106.967869 # Average occupied blocks per requestor 744system.cpu.dcache.occ_percent::cpu.data 0.026115 # Average percentage of cache occupancy 745system.cpu.dcache.occ_percent::total 0.026115 # Average percentage of cache occupancy 746system.cpu.dcache.ReadReq_hits::cpu.data 1740 # number of ReadReq hits 747system.cpu.dcache.ReadReq_hits::total 1740 # number of ReadReq hits |
| 694system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 695system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits | 748system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 749system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits |
| 696system.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits 697system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits 698system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits 699system.cpu.dcache.overall_hits::total 2262 # number of overall hits 700system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 701system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses | 750system.cpu.dcache.demand_hits::cpu.data 2246 # number of demand (read+write) hits 751system.cpu.dcache.demand_hits::total 2246 # number of demand (read+write) hits 752system.cpu.dcache.overall_hits::cpu.data 2246 # number of overall hits 753system.cpu.dcache.overall_hits::total 2246 # number of overall hits 754system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 755system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses |
| 702system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 703system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses | 756system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 757system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses |
| 704system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses 705system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses 706system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses 707system.cpu.dcache.overall_misses::total 528 # number of overall misses 708system.cpu.dcache.ReadReq_miss_latency::cpu.data 9128000 # number of ReadReq miss cycles 709system.cpu.dcache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles 710system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles 711system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles 712system.cpu.dcache.demand_miss_latency::cpu.data 25021487 # number of demand (read+write) miss cycles 713system.cpu.dcache.demand_miss_latency::total 25021487 # number of demand (read+write) miss cycles 714system.cpu.dcache.overall_miss_latency::cpu.data 25021487 # number of overall miss cycles 715system.cpu.dcache.overall_miss_latency::total 25021487 # number of overall miss cycles 716system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) 717system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) | 758system.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses 759system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses 760system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses 761system.cpu.dcache.overall_misses::total 529 # number of overall misses 762system.cpu.dcache.ReadReq_miss_latency::cpu.data 11698500 # number of ReadReq miss cycles 763system.cpu.dcache.ReadReq_miss_latency::total 11698500 # number of ReadReq miss cycles 764system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723478 # number of WriteReq miss cycles 765system.cpu.dcache.WriteReq_miss_latency::total 21723478 # number of WriteReq miss cycles 766system.cpu.dcache.demand_miss_latency::cpu.data 33421978 # number of demand (read+write) miss cycles 767system.cpu.dcache.demand_miss_latency::total 33421978 # number of demand (read+write) miss cycles 768system.cpu.dcache.overall_miss_latency::cpu.data 33421978 # number of overall miss cycles 769system.cpu.dcache.overall_miss_latency::total 33421978 # number of overall miss cycles 770system.cpu.dcache.ReadReq_accesses::cpu.data 1910 # number of ReadReq accesses(hits+misses) 771system.cpu.dcache.ReadReq_accesses::total 1910 # number of ReadReq accesses(hits+misses) |
| 718system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 719system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) | 772system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 773system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
| 720system.cpu.dcache.demand_accesses::cpu.data 2790 # number of demand (read+write) accesses 721system.cpu.dcache.demand_accesses::total 2790 # number of demand (read+write) accesses 722system.cpu.dcache.overall_accesses::cpu.data 2790 # number of overall (read+write) accesses 723system.cpu.dcache.overall_accesses::total 2790 # number of overall (read+write) accesses 724system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087792 # miss rate for ReadReq accesses 725system.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses | 774system.cpu.dcache.demand_accesses::cpu.data 2775 # number of demand (read+write) accesses 775system.cpu.dcache.demand_accesses::total 2775 # number of demand (read+write) accesses 776system.cpu.dcache.overall_accesses::cpu.data 2775 # number of overall (read+write) accesses 777system.cpu.dcache.overall_accesses::total 2775 # number of overall (read+write) accesses 778system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089005 # miss rate for ReadReq accesses 779system.cpu.dcache.ReadReq_miss_rate::total 0.089005 # miss rate for ReadReq accesses |
| 726system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 727system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses | 780system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 781system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses |
| 728system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses 729system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses 730system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses 731system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses 732system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54011.834320 # average ReadReq miss latency 733system.cpu.dcache.ReadReq_avg_miss_latency::total 54011.834320 # average ReadReq miss latency 734system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency 735system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency 736system.cpu.dcache.demand_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency 737system.cpu.dcache.demand_avg_miss_latency::total 47389.179924 # average overall miss latency 738system.cpu.dcache.overall_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency 739system.cpu.dcache.overall_avg_miss_latency::total 47389.179924 # average overall miss latency 740system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked | 782system.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses 783system.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses 784system.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses 785system.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses 786system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency 787system.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency 788system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency 789system.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency 790system.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency 791system.cpu.dcache.demand_avg_miss_latency::total 63179.542533 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency 793system.cpu.dcache.overall_avg_miss_latency::total 63179.542533 # average overall miss latency 794system.cpu.dcache.blocked_cycles::no_mshrs 1568 # number of cycles access was blocked |
| 741system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 795system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 742system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked | 796system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked |
| 743system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 797system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 744system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked | 798system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.515152 # average number of cycles each access was blocked |
| 745system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 746system.cpu.dcache.fast_writes 0 # number of fast writes performed 747system.cpu.dcache.cache_copies 0 # number of cache copies performed | 799system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 800system.cpu.dcache.fast_writes 0 # number of fast writes performed 801system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 748system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 749system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits | 802system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 803system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits |
| 750system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 751system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits | 804system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 805system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits |
| 752system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits 753system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits 754system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits 755system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits | 806system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 807system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 808system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 809system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits |
| 756system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 757system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 758system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 759system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 760system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 761system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 762system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 763system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses | 810system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 811system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 812system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 813system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 814system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 815system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 816system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 817system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses |
| 764system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles 765system.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles 766system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles 767system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles 768system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles 769system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles 770system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles 771system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles 772system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses 773system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses | 818system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles 819system.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles 820system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles 821system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles 822system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles 823system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles 824system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles 825system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles 826system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses 827system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses |
| 774system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 775system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses | 828system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 829system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses |
| 776system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses 777system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses 778system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses 779system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses 780system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency 781system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency 782system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency 783system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency 784system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency 785system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency 786system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency 787system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency | 830system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses 831system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses 832system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses 833system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses 834system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency 835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency 836system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency 837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency 838system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency 839system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency 840system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency 841system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency |
| 788system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 789 790---------- End Simulation Statistics ---------- | 842system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 843 844---------- End Simulation Statistics ---------- |