Cross Reference: /gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000016 # Number of seconds simulated

4sim_ticks 15653000 # Number of ticks simulated
5final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 15802500 # Number of ticks simulated
5final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 11804 # Simulator instruction rate (inst/s)
8host_op_rate 11803 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 28994780 # Simulator tick rate (ticks/s)
10host_mem_usage 217308 # Number of bytes of host memory used
11host_seconds 0.54 # Real time elapsed on the host

7host_inst_rate 38730 # Simulator instruction rate (inst/s)
8host_op_rate 38726 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 96032767 # Simulator tick rate (ticks/s)
10host_mem_usage 214332 # Number of bytes of host memory used
11host_seconds 0.16 # Real time elapsed on the host

12sim_insts 6372 # Number of instructions simulated
13sim_ops 6372 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory
16system.physmem.bytes_read::total 31168 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 487 # Number of read requests responded to by this memory

22system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s)

22system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s)

30system.physmem.readReqs 487 # Total number of read requests seen
31system.physmem.writeReqs 0 # Total number of write requests seen
32system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 31168 # Total number of bytes read from memory
34system.physmem.bytesWritten 0 # Total number of bytes written to memory
35system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis

45system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis

49system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis

49system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis

50system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis
52system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis
53system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
54system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis

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65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

73system.physmem.totGap 15508000 # Total gap between requests

73system.physmem.totGap 15655000 # Total gap between requests

74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes
80system.physmem.readPktSize::6 487 # Categorize read packet sizes
81system.physmem.readPktSize::7 0 # Categorize read packet sizes

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94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
101system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see

102system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see

102system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see

103system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see

104system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see

104system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see

105system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see

--- 46 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

167system.physmem.totQLat 2668987 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests

167system.physmem.totQLat 3073487 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests

169system.physmem.totBusLat 1948000 # Total cycles spent in databus access
170system.physmem.totBankLat 7798000 # Total cycles spent in bank access

171system.physmem.avgQLat 5480.47 # Average queueing delay per request

171system.physmem.avgQLat 6311.06 # Average queueing delay per request

172system.physmem.avgBankLat 16012.32 # Average bank access latency per request
173system.physmem.avgBusLat 4000.00 # Average bus latency per request

174system.physmem.avgMemAccLat 25492.79 # Average memory access latency
175system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s

174system.physmem.avgMemAccLat 26323.38 # Average memory access latency
175system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s

176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s

177system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s

177system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s

178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s

180system.physmem.busUtil 12.44 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.79 # Average read queue length over time

180system.physmem.busUtil 12.33 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.81 # Average read queue length over time

182system.physmem.avgWrQLen 0.00 # Average write queue length over time

183system.physmem.readRowHits 417 # Number of row buffer hits during reads

183system.physmem.readRowHits 416 # Number of row buffer hits during reads

184system.physmem.writeRowHits 0 # Number of row buffer hits during writes

185system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads

185system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads

186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

187system.physmem.avgGap 31843.94 # Average gap between requests

187system.physmem.avgGap 32145.79 # Average gap between requests

188system.cpu.dtb.fetch_hits 0 # ITB hits
189system.cpu.dtb.fetch_misses 0 # ITB misses
190system.cpu.dtb.fetch_acv 0 # ITB acv
191system.cpu.dtb.fetch_accesses 0 # ITB accesses

192system.cpu.dtb.read_hits 2048 # DTB read hits
193system.cpu.dtb.read_misses 58 # DTB read misses

192system.cpu.dtb.read_hits 2068 # DTB read hits
193system.cpu.dtb.read_misses 50 # DTB read misses

194system.cpu.dtb.read_acv 0 # DTB read access violations

195system.cpu.dtb.read_accesses 2106 # DTB read accesses
196system.cpu.dtb.write_hits 1074 # DTB write hits
197system.cpu.dtb.write_misses 32 # DTB write misses

195system.cpu.dtb.read_accesses 2118 # DTB read accesses
196system.cpu.dtb.write_hits 1071 # DTB write hits
197system.cpu.dtb.write_misses 29 # DTB write misses

198system.cpu.dtb.write_acv 0 # DTB write access violations

199system.cpu.dtb.write_accesses 1106 # DTB write accesses
200system.cpu.dtb.data_hits 3122 # DTB hits
201system.cpu.dtb.data_misses 90 # DTB misses

199system.cpu.dtb.write_accesses 1100 # DTB write accesses
200system.cpu.dtb.data_hits 3139 # DTB hits
201system.cpu.dtb.data_misses 79 # DTB misses

202system.cpu.dtb.data_acv 0 # DTB access violations

203system.cpu.dtb.data_accesses 3212 # DTB accesses
204system.cpu.itb.fetch_hits 2395 # ITB hits
205system.cpu.itb.fetch_misses 38 # ITB misses

203system.cpu.dtb.data_accesses 3218 # DTB accesses
204system.cpu.itb.fetch_hits 2370 # ITB hits
205system.cpu.itb.fetch_misses 39 # ITB misses

206system.cpu.itb.fetch_acv 0 # ITB acv

207system.cpu.itb.fetch_accesses 2433 # ITB accesses

207system.cpu.itb.fetch_accesses 2409 # ITB accesses

208system.cpu.itb.read_hits 0 # DTB read hits
209system.cpu.itb.read_misses 0 # DTB read misses
210system.cpu.itb.read_acv 0 # DTB read access violations
211system.cpu.itb.read_accesses 0 # DTB read accesses
212system.cpu.itb.write_hits 0 # DTB write hits
213system.cpu.itb.write_misses 0 # DTB write misses
214system.cpu.itb.write_acv 0 # DTB write access violations
215system.cpu.itb.write_accesses 0 # DTB write accesses
216system.cpu.itb.data_hits 0 # DTB hits
217system.cpu.itb.data_misses 0 # DTB misses
218system.cpu.itb.data_acv 0 # DTB access violations
219system.cpu.itb.data_accesses 0 # DTB accesses
220system.cpu.workload.num_syscalls 17 # Number of system calls

221system.cpu.numCycles 31307 # number of cpu cycles simulated

221system.cpu.numCycles 31606 # number of cpu cycles simulated

222system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
223system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

224system.cpu.BPredUnit.lookups 2894 # Number of BP lookups
225system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted
226system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect
227system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups
228system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits

224system.cpu.BPredUnit.lookups 2927 # Number of BP lookups
225system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted
226system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect
227system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups
228system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits

229system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

230system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target.
231system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions.
232system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss
233system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed
234system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered
235system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken
236system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked
237system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing
238system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked
239system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
240system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps
241system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched
242system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed
243system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total)
245system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total)

230system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target.
231system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions.
232system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss
233system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed
234system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered
235system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken
236system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked
237system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing
238system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked
239system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
240system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps
241system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched
242system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed
243system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total)
245system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total)

246system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

247system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total)
250system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total)
251system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total)
252system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total)
253system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total)
254system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total)

247system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total)
248system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total)
249system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total)
250system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total)
251system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total)
252system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total)
253system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total)
254system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total)
255system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total)

256system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
258system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

259system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle
261system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle
262system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle
263system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked

259system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle
261system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle
262system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle
263system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked

264system.cpu.decode.RunCycles 2779 # Number of cycles decode is running

265system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking
266system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing
267system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch

265system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking
266system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing
267system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch

268system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction

269system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode
270system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode
271system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing
272system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle
273system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking
274system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst
275system.cpu.rename.RunCycles 2656 # Number of cycles rename is running
276system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking
277system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename
278system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full
279system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed
280system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made
281system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups

269system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode
270system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode
271system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing
272system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle
273system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking
274system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst
275system.cpu.rename.RunCycles 2653 # Number of cycles rename is running
276system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking
277system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename
278system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
279system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full
280system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed
281system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made
282system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups

282system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
283system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed

283system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
284system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed

284system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing
285system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
286system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed
287system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer
288system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit.
289system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit.

285system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing
286system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
287system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed
288system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer
289system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit.
290system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit.

290system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
291system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.

291system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
292system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.

292system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec)
293system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
294system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued
295system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
296system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling
297system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph
298system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
299system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle

293system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec)
294system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
295system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued
296system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
297system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling
298system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph
299system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
300system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle
302system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle

302system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

303system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

303system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle
304system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle
305system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle
306system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle
307system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle
308system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle
309system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle
310system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle
311system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle

304system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle
305system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle
306system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle
307system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle
308system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle
309system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle
310system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle
311system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle
312system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle

312system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
313system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

313system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
314system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

315system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle

316system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle

316system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

317system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

317system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available
318system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available
319system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available
320system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available
321system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available
322system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available
323system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available
324system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available
325system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available
334system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available
335system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available
336system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available
337system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available
338system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available
339system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available
346system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available
347system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available

318system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available
319system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available
320system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available
321system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available
322system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
323system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available
324system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available
325system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available
326system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available
333system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available
334system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available
335system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available
336system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available
337system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available
338system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available
339system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available
340system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available
341system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available
342system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available
343system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available
344system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available
345system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available
346system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
347system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available
348system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available

348system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
349system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
350system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued

349system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
350system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
351system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued

351system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued
352system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued
353system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued
354system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued
355system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued
356system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued
357system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued
358system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued
359system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued
369system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued
370system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued
371system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued
372system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued
373system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued
380system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued
381system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued

352system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued
353system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued
354system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued
355system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued
356system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued
357system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued
358system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued
359system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued
360system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued
367system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued
368system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued
369system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued
370system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued
371system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued
372system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued
373system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued
374system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
381system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued
382system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued

382system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
383system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

383system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
384system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

384system.cpu.iq.FU_type_0::total 10660 # Type of FU issued
385system.cpu.iq.rate 0.340499 # Inst issue rate
386system.cpu.iq.fu_busy_cnt 114 # FU busy when requested
387system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst)
388system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads
389system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes
390system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses

385system.cpu.iq.FU_type_0::total 10819 # Type of FU issued
386system.cpu.iq.rate 0.342308 # Inst issue rate
387system.cpu.iq.fu_busy_cnt 117 # FU busy when requested
388system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst)
389system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads
390system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes
391system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses

391system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
392system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
393system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses

392system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
393system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
394system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses

394system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses

395system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses

395system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses

396system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses

396system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores

397system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores

397system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

398system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

398system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed

399system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed

399system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed

400system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed

400system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
401system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed

401system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
402system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed

402system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
403system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
404system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled

403system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
404system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
405system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled

405system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked

406system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked

406system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

407system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

407system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing
408system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking
409system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
410system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ
411system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
412system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions
413system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions
414system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
415system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall

408system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing
409system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking
410system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
411system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ
412system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch
413system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions
414system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions
415system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
416system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall

416system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

417system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall

417system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
418system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly
419system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly
420system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute
421system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions
422system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed
423system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute

418system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations
419system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly
420system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly
421system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute
422system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions
423system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed
424system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute

424system.cpu.iew.exec_swp 0 # number of swp insts executed

425system.cpu.iew.exec_swp 0 # number of swp insts executed

425system.cpu.iew.exec_nop 88 # number of nop insts executed
426system.cpu.iew.exec_refs 3225 # number of memory reference insts executed
427system.cpu.iew.exec_branches 1609 # Number of branches executed
428system.cpu.iew.exec_stores 1108 # Number of stores executed
429system.cpu.iew.exec_rate 0.319833 # Inst execution rate
430system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit
431system.cpu.iew.wb_count 9555 # cumulative count of insts written-back
432system.cpu.iew.wb_producers 5016 # num instructions producing a value
433system.cpu.iew.wb_consumers 6802 # num instructions consuming a value

426system.cpu.iew.exec_nop 87 # number of nop insts executed
427system.cpu.iew.exec_refs 3231 # number of memory reference insts executed
428system.cpu.iew.exec_branches 1614 # Number of branches executed
429system.cpu.iew.exec_stores 1102 # Number of stores executed
430system.cpu.iew.exec_rate 0.321679 # Inst execution rate
431system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit
432system.cpu.iew.wb_count 9733 # cumulative count of insts written-back
433system.cpu.iew.wb_producers 5145 # num instructions producing a value
434system.cpu.iew.wb_consumers 6933 # num instructions consuming a value

434system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

435system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

435system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle
436system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back

436system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle
437system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back

437system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

438system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

438system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit

439system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit

439system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards

440system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards

440system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted
441system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle

441system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted
442system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle
444system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle

444system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

445system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

445system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle
446system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle
447system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle
448system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle
449system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle
450system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle
451system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle
452system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle
453system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle

446system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle
447system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle
448system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle
449system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle
450system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle
451system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle
452system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle
453system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle
454system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle

454system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
455system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

455system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
456system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

457system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle

458system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle

458system.cpu.commit.committedInsts 6389 # Number of instructions committed
459system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
460system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
461system.cpu.commit.refs 2048 # Number of memory references committed
462system.cpu.commit.loads 1183 # Number of loads committed
463system.cpu.commit.membars 0 # Number of memory barriers committed
464system.cpu.commit.branches 1050 # Number of branches committed
465system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
466system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
467system.cpu.commit.function_calls 127 # Number of function calls committed.

459system.cpu.commit.committedInsts 6389 # Number of instructions committed
460system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
461system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
462system.cpu.commit.refs 2048 # Number of memory references committed
463system.cpu.commit.loads 1183 # Number of loads committed
464system.cpu.commit.membars 0 # Number of memory barriers committed
465system.cpu.commit.branches 1050 # Number of branches committed
466system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
467system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
468system.cpu.commit.function_calls 127 # Number of function calls committed.

468system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached

469system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached

469system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

470system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

470system.cpu.rob.rob_reads 25734 # The number of ROB reads
471system.cpu.rob.rob_writes 27303 # The number of ROB writes
472system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself
473system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling

471system.cpu.rob.rob_reads 25881 # The number of ROB reads
472system.cpu.rob.rob_writes 27599 # The number of ROB writes
473system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
474system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling

474system.cpu.committedInsts 6372 # Number of Instructions Simulated
475system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
476system.cpu.committedInsts_total 6372 # Number of Instructions Simulated

475system.cpu.committedInsts 6372 # Number of Instructions Simulated
476system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
477system.cpu.committedInsts_total 6372 # Number of Instructions Simulated

477system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction
478system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads
479system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle
480system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads
481system.cpu.int_regfile_reads 12695 # number of integer regfile reads
482system.cpu.int_regfile_writes 7186 # number of integer regfile writes

478system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction
479system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads
480system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle
481system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads
482system.cpu.int_regfile_reads 12907 # number of integer regfile reads
483system.cpu.int_regfile_writes 7365 # number of integer regfile writes

483system.cpu.fp_regfile_reads 8 # number of floating regfile reads
484system.cpu.fp_regfile_writes 2 # number of floating regfile writes
485system.cpu.misc_regfile_reads 1 # number of misc regfile reads
486system.cpu.misc_regfile_writes 1 # number of misc regfile writes
487system.cpu.icache.replacements 0 # number of replacements

484system.cpu.fp_regfile_reads 8 # number of floating regfile reads
485system.cpu.fp_regfile_writes 2 # number of floating regfile writes
486system.cpu.misc_regfile_reads 1 # number of misc regfile reads
487system.cpu.misc_regfile_writes 1 # number of misc regfile writes
488system.cpu.icache.replacements 0 # number of replacements

488system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use
489system.cpu.icache.total_refs 1916 # Total number of references to valid blocks.

489system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use
490system.cpu.icache.total_refs 1894 # Total number of references to valid blocks.

490system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.

491system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.

491system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks.

492system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks.

492system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

493system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

493system.cpu.icache.occ_blocks::cpu.inst 160.377030 # Average occupied blocks per requestor
494system.cpu.icache.occ_percent::cpu.inst 0.078309 # Average percentage of cache occupancy
495system.cpu.icache.occ_percent::total 0.078309 # Average percentage of cache occupancy
496system.cpu.icache.ReadReq_hits::cpu.inst 1916 # number of ReadReq hits
497system.cpu.icache.ReadReq_hits::total 1916 # number of ReadReq hits
498system.cpu.icache.demand_hits::cpu.inst 1916 # number of demand (read+write) hits
499system.cpu.icache.demand_hits::total 1916 # number of demand (read+write) hits
500system.cpu.icache.overall_hits::cpu.inst 1916 # number of overall hits
501system.cpu.icache.overall_hits::total 1916 # number of overall hits
502system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses
503system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses
504system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses
505system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses
506system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses
507system.cpu.icache.overall_misses::total 479 # number of overall misses
508system.cpu.icache.ReadReq_miss_latency::cpu.inst 21334000 # number of ReadReq miss cycles
509system.cpu.icache.ReadReq_miss_latency::total 21334000 # number of ReadReq miss cycles
510system.cpu.icache.demand_miss_latency::cpu.inst 21334000 # number of demand (read+write) miss cycles
511system.cpu.icache.demand_miss_latency::total 21334000 # number of demand (read+write) miss cycles
512system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles
513system.cpu.icache.overall_miss_latency::total 21334000 # number of overall miss cycles
514system.cpu.icache.ReadReq_accesses::cpu.inst 2395 # number of ReadReq accesses(hits+misses)
515system.cpu.icache.ReadReq_accesses::total 2395 # number of ReadReq accesses(hits+misses)
516system.cpu.icache.demand_accesses::cpu.inst 2395 # number of demand (read+write) accesses
517system.cpu.icache.demand_accesses::total 2395 # number of demand (read+write) accesses
518system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses
519system.cpu.icache.overall_accesses::total 2395 # number of overall (read+write) accesses
520system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses
521system.cpu.icache.ReadReq_miss_rate::total 0.200000 # miss rate for ReadReq accesses
522system.cpu.icache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses
523system.cpu.icache.demand_miss_rate::total 0.200000 # miss rate for demand accesses
524system.cpu.icache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses
525system.cpu.icache.overall_miss_rate::total 0.200000 # miss rate for overall accesses
526system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44538.622129 # average ReadReq miss latency
527system.cpu.icache.ReadReq_avg_miss_latency::total 44538.622129 # average ReadReq miss latency
528system.cpu.icache.demand_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency
529system.cpu.icache.demand_avg_miss_latency::total 44538.622129 # average overall miss latency
530system.cpu.icache.overall_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency
531system.cpu.icache.overall_avg_miss_latency::total 44538.622129 # average overall miss latency

494system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor
495system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy
496system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy
497system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits
498system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits
499system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits
500system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits
501system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits
502system.cpu.icache.overall_hits::total 1894 # number of overall hits
503system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses
504system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses
505system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses
506system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses
507system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses
508system.cpu.icache.overall_misses::total 476 # number of overall misses
509system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles
510system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles
511system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles
512system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles
513system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles
514system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles
515system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses)
516system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses)
517system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses
518system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses
519system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses
520system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses
521system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses
522system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses
523system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses
524system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses
525system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses
526system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses
527system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency
528system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency
529system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency
530system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency
531system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency
532system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency

532system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
533system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
534system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
535system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
536system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
537system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
538system.cpu.icache.fast_writes 0 # number of fast writes performed
539system.cpu.icache.cache_copies 0 # number of cache copies performed

533system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
534system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
535system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
536system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
537system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
538system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
539system.cpu.icache.fast_writes 0 # number of fast writes performed
540system.cpu.icache.cache_copies 0 # number of cache copies performed

540system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits
541system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits
542system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits
543system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits
544system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits
545system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits

541system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits
542system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits
543system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits
544system.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits
545system.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits
546system.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits

546system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
547system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses
548system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
549system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses
550system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
551system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses

547system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
548system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses
549system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
550system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses
551system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
552system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses

552system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15306500 # number of ReadReq MSHR miss cycles
553system.cpu.icache.ReadReq_mshr_miss_latency::total 15306500 # number of ReadReq MSHR miss cycles
554system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15306500 # number of demand (read+write) MSHR miss cycles
555system.cpu.icache.demand_mshr_miss_latency::total 15306500 # number of demand (read+write) MSHR miss cycles
556system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15306500 # number of overall MSHR miss cycles
557system.cpu.icache.overall_mshr_miss_latency::total 15306500 # number of overall MSHR miss cycles
558system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for ReadReq accesses
559system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131106 # mshr miss rate for ReadReq accesses
560system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for demand accesses
561system.cpu.icache.demand_mshr_miss_rate::total 0.131106 # mshr miss rate for demand accesses
562system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for overall accesses
563system.cpu.icache.overall_mshr_miss_rate::total 0.131106 # mshr miss rate for overall accesses
564system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48746.815287 # average ReadReq mshr miss latency
565system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48746.815287 # average ReadReq mshr miss latency
566system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency
567system.cpu.icache.demand_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency
568system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency
569system.cpu.icache.overall_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency

553system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles
554system.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles
555system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles
556system.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles
557system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles
558system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles
559system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses
560system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses
561system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses
562system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses
563system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses
564system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses
565system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency
566system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency
567system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency
568system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency
569system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency
570system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency

570system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

571system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

571system.cpu.dcache.replacements 0 # number of replacements
572system.cpu.dcache.tagsinuse 107.831538 # Cycle average of tags in use
573system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks.
574system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
575system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks.
576system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
577system.cpu.dcache.occ_blocks::cpu.data 107.831538 # Average occupied blocks per requestor
578system.cpu.dcache.occ_percent::cpu.data 0.026326 # Average percentage of cache occupancy
579system.cpu.dcache.occ_percent::total 0.026326 # Average percentage of cache occupancy
580system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits
581system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits
582system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
583system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
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585system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits
586system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits
587system.cpu.dcache.overall_hits::total 2240 # number of overall hits
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589system.cpu.dcache.ReadReq_misses::total 160 # number of ReadReq misses
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591system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
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593system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses
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595system.cpu.dcache.overall_misses::total 519 # number of overall misses
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597system.cpu.dcache.ReadReq_miss_latency::total 8308500 # number of ReadReq miss cycles
598system.cpu.dcache.WriteReq_miss_latency::cpu.data 15746484 # number of WriteReq miss cycles
599system.cpu.dcache.WriteReq_miss_latency::total 15746484 # number of WriteReq miss cycles
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601system.cpu.dcache.demand_miss_latency::total 24054984 # number of demand (read+write) miss cycles
602system.cpu.dcache.overall_miss_latency::cpu.data 24054984 # number of overall miss cycles
603system.cpu.dcache.overall_miss_latency::total 24054984 # number of overall miss cycles
604system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses)
605system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses)
606system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
607system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
608system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses
609system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses
610system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses
611system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses
612system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084477 # miss rate for ReadReq accesses
613system.cpu.dcache.ReadReq_miss_rate::total 0.084477 # miss rate for ReadReq accesses
614system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
615system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
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617system.cpu.dcache.demand_miss_rate::total 0.188112 # miss rate for demand accesses
618system.cpu.dcache.overall_miss_rate::cpu.data 0.188112 # miss rate for overall accesses
619system.cpu.dcache.overall_miss_rate::total 0.188112 # miss rate for overall accesses
620system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51928.125000 # average ReadReq miss latency
621system.cpu.dcache.ReadReq_avg_miss_latency::total 51928.125000 # average ReadReq miss latency
622system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43862.072423 # average WriteReq miss latency
623system.cpu.dcache.WriteReq_avg_miss_latency::total 43862.072423 # average WriteReq miss latency
624system.cpu.dcache.demand_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency
625system.cpu.dcache.demand_avg_miss_latency::total 46348.716763 # average overall miss latency
626system.cpu.dcache.overall_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency
627system.cpu.dcache.overall_avg_miss_latency::total 46348.716763 # average overall miss latency
628system.cpu.dcache.blocked_cycles::no_mshrs 810 # number of cycles access was blocked
629system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
630system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
631system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
632system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.928571 # average number of cycles each access was blocked
633system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
634system.cpu.dcache.fast_writes 0 # number of fast writes performed
635system.cpu.dcache.cache_copies 0 # number of cache copies performed
636system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
637system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
638system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
639system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
640system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits
641system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits
642system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits
643system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits
644system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
645system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
646system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
647system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
648system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
649system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
650system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
651system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6029500 # number of ReadReq MSHR miss cycles
653system.cpu.dcache.ReadReq_mshr_miss_latency::total 6029500 # number of ReadReq MSHR miss cycles
654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3803500 # number of WriteReq MSHR miss cycles
655system.cpu.dcache.WriteReq_mshr_miss_latency::total 3803500 # number of WriteReq MSHR miss cycles
656system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9833000 # number of demand (read+write) MSHR miss cycles
657system.cpu.dcache.demand_mshr_miss_latency::total 9833000 # number of demand (read+write) MSHR miss cycles
658system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9833000 # number of overall MSHR miss cycles
659system.cpu.dcache.overall_mshr_miss_latency::total 9833000 # number of overall MSHR miss cycles
660system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses
661system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses
662system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
663system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
664system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses
665system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses
666system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses
667system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses
668system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59698.019802 # average ReadReq mshr miss latency
669system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59698.019802 # average ReadReq mshr miss latency
670system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52102.739726 # average WriteReq mshr miss latency
671system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52102.739726 # average WriteReq mshr miss latency
672system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency
673system.cpu.dcache.demand_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency
674system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency
675system.cpu.dcache.overall_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency
676system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

677system.cpu.l2cache.replacements 0 # number of replacements

572system.cpu.l2cache.replacements 0 # number of replacements

678system.cpu.l2cache.tagsinuse 220.955415 # Cycle average of tags in use

573system.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use

679system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
680system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks.
681system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks.
682system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

574system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
575system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks.
576system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks.
577system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

683system.cpu.l2cache.occ_blocks::cpu.inst 160.525117 # Average occupied blocks per requestor
684system.cpu.l2cache.occ_blocks::cpu.data 60.430298 # Average occupied blocks per requestor
685system.cpu.l2cache.occ_percent::cpu.inst 0.004899 # Average percentage of cache occupancy
686system.cpu.l2cache.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy
687system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy

578system.cpu.l2cache.occ_blocks::cpu.inst 160.626019 # Average occupied blocks per requestor
579system.cpu.l2cache.occ_blocks::cpu.data 60.276472 # Average occupied blocks per requestor
580system.cpu.l2cache.occ_percent::cpu.inst 0.004902 # Average percentage of cache occupancy
581system.cpu.l2cache.occ_percent::cpu.data 0.001839 # Average percentage of cache occupancy
582system.cpu.l2cache.occ_percent::total 0.006741 # Average percentage of cache occupancy

688system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
689system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
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694system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses
695system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
696system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses
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698system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
699system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses
700system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses
701system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses
702system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses
703system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
704system.cpu.l2cache.overall_misses::total 487 # number of overall misses

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586system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
587system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
588system.cpu.l2cache.overall_hits::total 1 # number of overall hits
589system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses
590system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
591system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses
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593system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
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597system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses
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599system.cpu.l2cache.overall_misses::total 487 # number of overall misses

705system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14981000 # number of ReadReq miss cycles
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709system.cpu.l2cache.ReadExReq_miss_latency::total 3727500 # number of ReadExReq miss cycles
710system.cpu.l2cache.demand_miss_latency::cpu.inst 14981000 # number of demand (read+write) miss cycles
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713system.cpu.l2cache.overall_miss_latency::cpu.inst 14981000 # number of overall miss cycles
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604system.cpu.l2cache.ReadExReq_miss_latency::total 3737500 # number of ReadExReq miss cycles
605system.cpu.l2cache.demand_miss_latency::cpu.inst 15078000 # number of demand (read+write) miss cycles
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608system.cpu.l2cache.overall_miss_latency::cpu.inst 15078000 # number of overall miss cycles
609system.cpu.l2cache.overall_miss_latency::cpu.data 9948000 # number of overall miss cycles
610system.cpu.l2cache.overall_miss_latency::total 25026000 # number of overall miss cycles

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--- 6 unchanged lines hidden (view full) ---

730system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
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732system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses
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735system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses
736system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
737system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses

611system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses)
612system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
613system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
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615system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
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--- 6 unchanged lines hidden (view full) ---

625system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
626system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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628system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
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631system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
632system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses

738system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47862.619808 # average ReadReq miss latency
739system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58623.762376 # average ReadReq miss latency
740system.cpu.l2cache.ReadReq_avg_miss_latency::total 50487.922705 # average ReadReq miss latency
741system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51061.643836 # average ReadExReq miss latency
742system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51061.643836 # average ReadExReq miss latency
743system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency
744system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency
745system.cpu.l2cache.demand_avg_miss_latency::total 50573.921971 # average overall miss latency
746system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency
747system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency
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633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48172.523962 # average ReadReq miss latency
634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61490.099010 # average ReadReq miss latency
635system.cpu.l2cache.ReadReq_avg_miss_latency::total 51421.497585 # average ReadReq miss latency
636system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51198.630137 # average ReadExReq miss latency
637system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51198.630137 # average ReadExReq miss latency
638system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency
639system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency
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641system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency
642system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency
643system.cpu.l2cache.overall_avg_miss_latency::total 51388.090349 # average overall miss latency

749system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
750system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
751system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
752system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
753system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
754system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
755system.cpu.l2cache.fast_writes 0 # number of fast writes performed
756system.cpu.l2cache.cache_copies 0 # number of cache copies performed
757system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
758system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
759system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses
760system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
761system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
762system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
763system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
764system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses
765system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
766system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
767system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses

644system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
645system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
646system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
647system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
648system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
649system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
650system.cpu.l2cache.fast_writes 0 # number of fast writes performed
651system.cpu.l2cache.cache_copies 0 # number of cache copies performed
652system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
653system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
654system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses
655system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
656system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
657system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
658system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
659system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses
660system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
661system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
662system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses

768system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11042494 # number of ReadReq MSHR miss cycles
769system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4678584 # number of ReadReq MSHR miss cycles
770system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15721078 # number of ReadReq MSHR miss cycles
771system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2834058 # number of ReadExReq MSHR miss cycles
772system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2834058 # number of ReadExReq MSHR miss cycles
773system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11042494 # number of demand (read+write) MSHR miss cycles
774system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7512642 # number of demand (read+write) MSHR miss cycles
775system.cpu.l2cache.demand_mshr_miss_latency::total 18555136 # number of demand (read+write) MSHR miss cycles
776system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11042494 # number of overall MSHR miss cycles
777system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7512642 # number of overall MSHR miss cycles
778system.cpu.l2cache.overall_mshr_miss_latency::total 18555136 # number of overall MSHR miss cycles

663system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11136994 # number of ReadReq MSHR miss cycles
664system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4966088 # number of ReadReq MSHR miss cycles
665system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16103082 # number of ReadReq MSHR miss cycles
666system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2842064 # number of ReadExReq MSHR miss cycles
667system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2842064 # number of ReadExReq MSHR miss cycles
668system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11136994 # number of demand (read+write) MSHR miss cycles
669system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7808152 # number of demand (read+write) MSHR miss cycles
670system.cpu.l2cache.demand_mshr_miss_latency::total 18945146 # number of demand (read+write) MSHR miss cycles
671system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11136994 # number of overall MSHR miss cycles
672system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7808152 # number of overall MSHR miss cycles
673system.cpu.l2cache.overall_mshr_miss_latency::total 18945146 # number of overall MSHR miss cycles

779system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses
780system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
781system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses
782system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
783system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
784system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
785system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
786system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses
787system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
788system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
789system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses

674system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses
675system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
676system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses
677system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
678system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
679system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses
680system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
681system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses
682system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses
683system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
684system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses

790system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35279.533546 # average ReadReq mshr miss latency
791system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46322.613861 # average ReadReq mshr miss latency
792system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37973.618357 # average ReadReq mshr miss latency
793system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38822.712329 # average ReadExReq mshr miss latency
794system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38822.712329 # average ReadExReq mshr miss latency
795system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency
796system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency
797system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency
798system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency
799system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency
800system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency

685system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35581.450479 # average ReadReq mshr miss latency
686system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49169.188119 # average ReadReq mshr miss latency
687system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38896.333333 # average ReadReq mshr miss latency
688system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38932.383562 # average ReadExReq mshr miss latency
689system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38932.383562 # average ReadExReq mshr miss latency
690system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency
691system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency
692system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency
693system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency
694system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency
695system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency

801system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

696system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

697system.cpu.dcache.replacements 0 # number of replacements
698system.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use
699system.cpu.dcache.total_refs 2264 # Total number of references to valid blocks.
700system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
701system.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks.
702system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
703system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor
704system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy
705system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy
706system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits
707system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits
708system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
709system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
710system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits
711system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits
712system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits
713system.cpu.dcache.overall_hits::total 2264 # number of overall hits
714system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses
715system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses
716system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
717system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
718system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses
719system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses
720system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses
721system.cpu.dcache.overall_misses::total 528 # number of overall misses
722system.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles
723system.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles
724system.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles
725system.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles
726system.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles
727system.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles
728system.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles
729system.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles
730system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses)
731system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses)
732system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
733system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
734system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses
735system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses
736system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses
737system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses
738system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses
739system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses
740system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
741system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
742system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses
743system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses
744system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses
745system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses
746system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency
747system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency
748system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency
749system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency
750system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency
751system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency
752system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency
753system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency
754system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked
755system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
756system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
757system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
758system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked
759system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
760system.cpu.dcache.fast_writes 0 # number of fast writes performed
761system.cpu.dcache.cache_copies 0 # number of cache copies performed
762system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits
763system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
764system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
765system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
766system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits
767system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits
768system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits
769system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits
770system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
771system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
772system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
773system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
774system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
775system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
776system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
777system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
778system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles
779system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles
780system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles
781system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles
782system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles
783system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles
784system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles
785system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles
786system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses
787system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses
788system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
789system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
790system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses
791system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses
792system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses
793system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses
794system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency
795system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency
796system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency
797system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency
798system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency
799system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency
800system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency
801system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency
802system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate