1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000012 # Number of seconds simulated
4sim_ticks 12146500 # Number of ticks simulated
5final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
| 3sim_seconds 0.000013 # Number of seconds simulated
4sim_ticks 12811000 # Number of ticks simulated
5final_tick 12811000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
6sim_freq 1000000000000 # Frequency of simulated ticks
| 6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 109785 # Simulator instruction rate (inst/s)
8host_op_rate 109750 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 208686624 # Simulator tick rate (ticks/s)
10host_mem_usage 218220 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host
| 7host_inst_rate 61639 # Simulator instruction rate (inst/s)
8host_op_rate 61622 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 123585600 # Simulator tick rate (ticks/s)
10host_mem_usage 219212 # Number of bytes of host memory used
11host_seconds 0.10 # Real time elapsed on the host
|
12sim_insts 6386 # Number of instructions simulated
13sim_ops 6386 # Number of ops (including micro ops) simulated
| 12sim_insts 6386 # Number of instructions simulated
13sim_ops 6386 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory
16system.physmem.bytes_read::total 31232 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 488 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s)
| 14system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory
16system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1568651940 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 874248693 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2442900632 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1568651940 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1568651940 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1568651940 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 874248693 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2442900632 # Total bandwidth to/from this memory (bytes/s)
|
30system.cpu.dtb.fetch_hits 0 # ITB hits
31system.cpu.dtb.fetch_misses 0 # ITB misses
32system.cpu.dtb.fetch_acv 0 # ITB acv
33system.cpu.dtb.fetch_accesses 0 # ITB accesses
| 30system.cpu.dtb.fetch_hits 0 # ITB hits
31system.cpu.dtb.fetch_misses 0 # ITB misses
32system.cpu.dtb.fetch_acv 0 # ITB acv
33system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
34system.cpu.dtb.read_hits 1978 # DTB read hits
35system.cpu.dtb.read_misses 49 # DTB read misses
| 34system.cpu.dtb.read_hits 1966 # DTB read hits
35system.cpu.dtb.read_misses 45 # DTB read misses
|
36system.cpu.dtb.read_acv 0 # DTB read access violations
| 36system.cpu.dtb.read_acv 0 # DTB read access violations
|
37system.cpu.dtb.read_accesses 2027 # DTB read accesses
| 37system.cpu.dtb.read_accesses 2011 # DTB read accesses
|
38system.cpu.dtb.write_hits 1059 # DTB write hits
| 38system.cpu.dtb.write_hits 1059 # DTB write hits
|
39system.cpu.dtb.write_misses 31 # DTB write misses
| 39system.cpu.dtb.write_misses 28 # DTB write misses
|
40system.cpu.dtb.write_acv 0 # DTB write access violations
| 40system.cpu.dtb.write_acv 0 # DTB write access violations
|
41system.cpu.dtb.write_accesses 1090 # DTB write accesses
42system.cpu.dtb.data_hits 3037 # DTB hits
43system.cpu.dtb.data_misses 80 # DTB misses
| 41system.cpu.dtb.write_accesses 1087 # DTB write accesses
42system.cpu.dtb.data_hits 3025 # DTB hits
43system.cpu.dtb.data_misses 73 # DTB misses
|
44system.cpu.dtb.data_acv 0 # DTB access violations
| 44system.cpu.dtb.data_acv 0 # DTB access violations
|
45system.cpu.dtb.data_accesses 3117 # DTB accesses
46system.cpu.itb.fetch_hits 2279 # ITB hits
47system.cpu.itb.fetch_misses 30 # ITB misses
| 45system.cpu.dtb.data_accesses 3098 # DTB accesses
46system.cpu.itb.fetch_hits 2254 # ITB hits
47system.cpu.itb.fetch_misses 39 # ITB misses
|
48system.cpu.itb.fetch_acv 0 # ITB acv
| 48system.cpu.itb.fetch_acv 0 # ITB acv
|
49system.cpu.itb.fetch_accesses 2309 # ITB accesses
| 49system.cpu.itb.fetch_accesses 2293 # ITB accesses
|
50system.cpu.itb.read_hits 0 # DTB read hits
51system.cpu.itb.read_misses 0 # DTB read misses
52system.cpu.itb.read_acv 0 # DTB read access violations
53system.cpu.itb.read_accesses 0 # DTB read accesses
54system.cpu.itb.write_hits 0 # DTB write hits
55system.cpu.itb.write_misses 0 # DTB write misses
56system.cpu.itb.write_acv 0 # DTB write access violations
57system.cpu.itb.write_accesses 0 # DTB write accesses
58system.cpu.itb.data_hits 0 # DTB hits
59system.cpu.itb.data_misses 0 # DTB misses
60system.cpu.itb.data_acv 0 # DTB access violations
61system.cpu.itb.data_accesses 0 # DTB accesses
62system.cpu.workload.num_syscalls 17 # Number of system calls
| 50system.cpu.itb.read_hits 0 # DTB read hits
51system.cpu.itb.read_misses 0 # DTB read misses
52system.cpu.itb.read_acv 0 # DTB read access violations
53system.cpu.itb.read_accesses 0 # DTB read accesses
54system.cpu.itb.write_hits 0 # DTB write hits
55system.cpu.itb.write_misses 0 # DTB write misses
56system.cpu.itb.write_acv 0 # DTB write access violations
57system.cpu.itb.write_accesses 0 # DTB write accesses
58system.cpu.itb.data_hits 0 # DTB hits
59system.cpu.itb.data_misses 0 # DTB misses
60system.cpu.itb.data_acv 0 # DTB access violations
61system.cpu.itb.data_accesses 0 # DTB accesses
62system.cpu.workload.num_syscalls 17 # Number of system calls
|
63system.cpu.numCycles 24294 # number of cpu cycles simulated
| 63system.cpu.numCycles 25623 # number of cpu cycles simulated
|
64system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
65system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
| 64system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
65system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
66system.cpu.BPredUnit.lookups 2808 # Number of BP lookups
67system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted
68system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect
69system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups
70system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits
| 66system.cpu.BPredUnit.lookups 2750 # Number of BP lookups
67system.cpu.BPredUnit.condPredicted 1591 # Number of conditional branches predicted
68system.cpu.BPredUnit.condIncorrect 527 # Number of conditional branches incorrect
69system.cpu.BPredUnit.BTBLookups 2077 # Number of BTB lookups
70system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits
|
71system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
| 71system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
72system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target.
73system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
74system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss
75system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed
76system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered
77system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken
78system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked
79system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing
80system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked
81system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
82system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps
83system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched
84system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed
85system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total)
86system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total)
87system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total)
| 72system.cpu.BPredUnit.usedRAS 402 # Number of times the RAS was used to get a target.
73system.cpu.BPredUnit.RASInCorrect 69 # Number of incorrect RAS predictions.
74system.cpu.fetch.icacheStallCycles 8523 # Number of cycles fetch is stalled on an Icache miss
75system.cpu.fetch.Insts 15693 # Number of instructions fetch has processed
76system.cpu.fetch.Branches 2750 # Number of branches that fetch encountered
77system.cpu.fetch.predictedBranches 1150 # Number of branches that fetch has predicted taken
78system.cpu.fetch.Cycles 2817 # Number of cycles fetch has run and was not squashing or blocked
79system.cpu.fetch.SquashCycles 1761 # Number of cycles fetch has spent squashing
80system.cpu.fetch.BlockedCycles 996 # Number of cycles fetch has spent blocked
81system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
82system.cpu.fetch.PendingTrapStallCycles 745 # Number of stall cycles due to pending traps
83system.cpu.fetch.CacheLines 2254 # Number of cache lines fetched
84system.cpu.fetch.IcacheSquashes 361 # Number of outstanding Icache misses that were squashed
85system.cpu.fetch.rateDist::samples 14299 # Number of instructions fetched each cycle (Total)
86system.cpu.fetch.rateDist::mean 1.097489 # Number of instructions fetched each cycle (Total)
87system.cpu.fetch.rateDist::stdev 2.491166 # Number of instructions fetched each cycle (Total)
|
88system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
| 88system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
89system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total)
| 89system.cpu.fetch.rateDist::0 11482 80.30% 80.30% # Number of instructions fetched each cycle (Total)
90system.cpu.fetch.rateDist::1 287 2.01% 82.31% # Number of instructions fetched each cycle (Total)
91system.cpu.fetch.rateDist::2 235 1.64% 83.95% # Number of instructions fetched each cycle (Total)
92system.cpu.fetch.rateDist::3 221 1.55% 85.50% # Number of instructions fetched each cycle (Total)
93system.cpu.fetch.rateDist::4 257 1.80% 87.29% # Number of instructions fetched each cycle (Total)
94system.cpu.fetch.rateDist::5 195 1.36% 88.66% # Number of instructions fetched each cycle (Total)
95system.cpu.fetch.rateDist::6 267 1.87% 90.52% # Number of instructions fetched each cycle (Total)
96system.cpu.fetch.rateDist::7 172 1.20% 91.73% # Number of instructions fetched each cycle (Total)
97system.cpu.fetch.rateDist::8 1183 8.27% 100.00% # Number of instructions fetched each cycle (Total)
|
98system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
| 98system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
99system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
100system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
101system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle
103system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle
104system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle
105system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked
106system.cpu.decode.RunCycles 2684 # Number of cycles decode is running
107system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking
108system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing
109system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch
| 101system.cpu.fetch.rateDist::total 14299 # Number of instructions fetched each cycle (Total)
102system.cpu.fetch.branchRate 0.107325 # Number of branch fetches per cycle
103system.cpu.fetch.rate 0.612458 # Number of inst fetches per cycle
104system.cpu.decode.IdleCycles 9448 # Number of cycles decode is idle
105system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked
106system.cpu.decode.RunCycles 2627 # Number of cycles decode is running
107system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
108system.cpu.decode.SquashCycles 1110 # Number of cycles decode is squashing
109system.cpu.decode.BranchResolved 255 # Number of times decode resolved a branch
|
110system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
| 110system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
|
111system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode
| 111system.cpu.decode.DecodedInsts 14531 # Number of instructions handled by decode
|
112system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode
| 112system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode
|
113system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing
114system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle
115system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking
116system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst
117system.cpu.rename.RunCycles 2519 # Number of cycles rename is running
118system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking
119system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename
120system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
121system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full
122system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed
123system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made
124system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups
| 113system.cpu.rename.SquashCycles 1110 # Number of cycles rename is squashing
114system.cpu.rename.IdleCycles 9647 # Number of cycles rename is idle
115system.cpu.rename.BlockCycles 356 # Number of cycles rename is blocking
116system.cpu.rename.serializeStallCycles 379 # count of cycles rename stalled for serializing inst
117system.cpu.rename.RunCycles 2494 # Number of cycles rename is running
118system.cpu.rename.UnblockCycles 313 # Number of cycles rename is unblocking
119system.cpu.rename.RenamedInsts 13871 # Number of instructions processed by rename
120system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
121system.cpu.rename.LSQFullEvents 268 # Number of times rename has blocked due to LSQ full
122system.cpu.rename.RenamedOperands 10378 # Number of destination operands rename has renamed
123system.cpu.rename.RenameLookups 17349 # Number of register rename lookups that rename has made
124system.cpu.rename.int_rename_lookups 17332 # Number of integer rename lookups
|
125system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
126system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
| 125system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
126system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
|
127system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing
128system.cpu.rename.serializingInsts 33 # count of serializing insts renamed
129system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
130system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer
131system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit.
132system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit.
| 127system.cpu.rename.UndoneMaps 5795 # Number of HB maps that are undone due to squashing
128system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
129system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed
130system.cpu.rename.skidInsts 762 # count of insts added to the skid buffer
131system.cpu.memDep0.insertedLoads 2605 # Number of loads inserted to the mem dependence unit.
132system.cpu.memDep0.insertedStores 1307 # Number of stores inserted to the mem dependence unit.
|
133system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
134system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
| 133system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
134system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
135system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec)
136system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ
137system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued
138system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
139system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling
140system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph
141system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
142system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle
143system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle
144system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle
| 135system.cpu.iq.iqInstsAdded 12446 # Number of instructions added to the IQ (excludes non-spec)
136system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
137system.cpu.iq.iqInstsIssued 10341 # Number of instructions issued
138system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued
139system.cpu.iq.iqSquashedInstsExamined 5740 # Number of squashed instructions iterated over during squash; mainly for profiling
140system.cpu.iq.iqSquashedOperandsExamined 3350 # Number of squashed operands that are examined and possibly removed from graph
141system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
142system.cpu.iq.issued_per_cycle::samples 14299 # Number of insts issued each cycle
143system.cpu.iq.issued_per_cycle::mean 0.723197 # Number of insts issued each cycle
144system.cpu.iq.issued_per_cycle::stdev 1.354818 # Number of insts issued each cycle
|
145system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
| 145system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
146system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle
147system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle
148system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle
| 146system.cpu.iq.issued_per_cycle::0 9905 69.27% 69.27% # Number of insts issued each cycle
147system.cpu.iq.issued_per_cycle::1 1622 11.34% 80.61% # Number of insts issued each cycle
148system.cpu.iq.issued_per_cycle::2 1176 8.22% 88.84% # Number of insts issued each cycle
149system.cpu.iq.issued_per_cycle::3 704 4.92% 93.76% # Number of insts issued each cycle
150system.cpu.iq.issued_per_cycle::4 444 3.11% 96.87% # Number of insts issued each cycle
151system.cpu.iq.issued_per_cycle::5 263 1.84% 98.71% # Number of insts issued each cycle
152system.cpu.iq.issued_per_cycle::6 141 0.99% 99.69% # Number of insts issued each cycle
153system.cpu.iq.issued_per_cycle::7 34 0.24% 99.93% # Number of insts issued each cycle
154system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle
|
155system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
| 155system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
156system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
157system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
158system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle
| 158system.cpu.iq.issued_per_cycle::total 14299 # Number of insts issued each cycle
|
159system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
| 159system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
160system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available
161system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available
162system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available
163system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available
164system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available
165system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available
166system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available
167system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available
168system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
169system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available
170system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available
171system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available
172system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available
173system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available
174system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
189system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available
190system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available
| 160system.cpu.iq.fu_full::IntAlu 8 7.27% 7.27% # attempts to use FU when none available
161system.cpu.iq.fu_full::IntMult 0 0.00% 7.27% # attempts to use FU when none available
162system.cpu.iq.fu_full::IntDiv 0 0.00% 7.27% # attempts to use FU when none available
163system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.27% # attempts to use FU when none available
164system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.27% # attempts to use FU when none available
165system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.27% # attempts to use FU when none available
166system.cpu.iq.fu_full::FloatMult 0 0.00% 7.27% # attempts to use FU when none available
167system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.27% # attempts to use FU when none available
168system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.27% # attempts to use FU when none available
169system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.27% # attempts to use FU when none available
170system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.27% # attempts to use FU when none available
171system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.27% # attempts to use FU when none available
172system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.27% # attempts to use FU when none available
173system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.27% # attempts to use FU when none available
174system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.27% # attempts to use FU when none available
175system.cpu.iq.fu_full::SimdMult 0 0.00% 7.27% # attempts to use FU when none available
176system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.27% # attempts to use FU when none available
177system.cpu.iq.fu_full::SimdShift 0 0.00% 7.27% # attempts to use FU when none available
178system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.27% # attempts to use FU when none available
179system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.27% # attempts to use FU when none available
180system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.27% # attempts to use FU when none available
181system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.27% # attempts to use FU when none available
182system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.27% # attempts to use FU when none available
183system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.27% # attempts to use FU when none available
184system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.27% # attempts to use FU when none available
185system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.27% # attempts to use FU when none available
186system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.27% # attempts to use FU when none available
187system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.27% # attempts to use FU when none available
188system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.27% # attempts to use FU when none available
189system.cpu.iq.fu_full::MemRead 65 59.09% 66.36% # attempts to use FU when none available
190system.cpu.iq.fu_full::MemWrite 37 33.64% 100.00% # attempts to use FU when none available
|
191system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
192system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
193system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
| 191system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
192system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
193system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
194system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued
195system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued
196system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued
197system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued
198system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued
199system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued
200system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued
201system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued
202system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued
203system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued
204system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued
205system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued
206system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued
207system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued
208system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued
223system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued
224system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued
| 194system.cpu.iq.FU_type_0::IntAlu 7000 67.69% 67.71% # Type of FU issued
195system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.72% # Type of FU issued
196system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.72% # Type of FU issued
197system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.74% # Type of FU issued
198system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.74% # Type of FU issued
199system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.74% # Type of FU issued
200system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.74% # Type of FU issued
201system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.74% # Type of FU issued
202system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.74% # Type of FU issued
203system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.74% # Type of FU issued
204system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.74% # Type of FU issued
205system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.74% # Type of FU issued
206system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.74% # Type of FU issued
207system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.74% # Type of FU issued
208system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.74% # Type of FU issued
209system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.74% # Type of FU issued
210system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.74% # Type of FU issued
211system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.74% # Type of FU issued
212system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued
213system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.74% # Type of FU issued
214system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued
215system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued
216system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued
217system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued
218system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued
219system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued
220system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.74% # Type of FU issued
221system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued
222system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued
223system.cpu.iq.FU_type_0::MemRead 2210 21.37% 89.11% # Type of FU issued
224system.cpu.iq.FU_type_0::MemWrite 1126 10.89% 100.00% # Type of FU issued
|
225system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
226system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
| 225system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
226system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
227system.cpu.iq.FU_type_0::total 10419 # Type of FU issued
228system.cpu.iq.rate 0.428871 # Inst issue rate
229system.cpu.iq.fu_busy_cnt 108 # FU busy when requested
230system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst)
231system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads
232system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes
233system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses
| 227system.cpu.iq.FU_type_0::total 10341 # Type of FU issued
228system.cpu.iq.rate 0.403583 # Inst issue rate
229system.cpu.iq.fu_busy_cnt 110 # FU busy when requested
230system.cpu.iq.fu_busy_rate 0.010637 # FU busy rate (busy events/executed inst)
231system.cpu.iq.int_inst_queue_reads 35107 # Number of integer instruction queue reads
232system.cpu.iq.int_inst_queue_writes 18223 # Number of integer instruction queue writes
233system.cpu.iq.int_inst_queue_wakeup_accesses 9409 # Number of integer instruction queue wakeup accesses
|
234system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
235system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
236system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
| 234system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
235system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
236system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
|
237system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses
| 237system.cpu.iq.int_alu_accesses 10438 # Number of integer alu accesses
|
238system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
| 238system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
|
239system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
| 239system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores
|
240system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
| 240system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
241system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed
242system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
| 241system.cpu.iew.lsq.thread0.squashedLoads 1420 # Number of loads squashed
242system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
|
243system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
| 243system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
|
244system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed
| 244system.cpu.iew.lsq.thread0.squashedStores 442 # Number of stores squashed
|
245system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
246system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
247system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
248system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
249system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
| 245system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
246system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
247system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
248system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
249system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
250system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing
251system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking
| 250system.cpu.iew.iewSquashCycles 1110 # Number of cycles IEW is squashing
251system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking
|
252system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
| 252system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
|
253system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ
254system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch
255system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions
256system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions
257system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
| 253system.cpu.iew.iewDispatchedInsts 12564 # Number of instructions dispatched to IQ
254system.cpu.iew.iewDispSquashedInsts 188 # Number of squashed instructions skipped by dispatch
255system.cpu.iew.iewDispLoadInsts 2605 # Number of dispatched load instructions
256system.cpu.iew.iewDispStoreInsts 1307 # Number of dispatched store instructions
257system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
|
258system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
259system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
260system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
| 258system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
259system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
260system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
|
261system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly
262system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly
263system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute
264system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions
265system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed
266system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute
| 261system.cpu.iew.predictedTakenIncorrect 139 # Number of branches that were predicted taken incorrectly
262system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly
263system.cpu.iew.branchMispredicts 524 # Number of branch mispredicts detected at execute
264system.cpu.iew.iewExecutedInsts 9796 # Number of executed instructions
265system.cpu.iew.iewExecLoadInsts 2022 # Number of load instructions executed
266system.cpu.iew.iewExecSquashedInsts 545 # Number of squashed instructions skipped in execute
|
267system.cpu.iew.exec_swp 0 # number of swp insts executed
| 267system.cpu.iew.exec_swp 0 # number of swp insts executed
|
268system.cpu.iew.exec_nop 83 # number of nop insts executed
269system.cpu.iew.exec_refs 3133 # number of memory reference insts executed
| 268system.cpu.iew.exec_nop 88 # number of nop insts executed
269system.cpu.iew.exec_refs 3112 # number of memory reference insts executed
|
270system.cpu.iew.exec_branches 1595 # Number of branches executed
| 270system.cpu.iew.exec_branches 1595 # Number of branches executed
|
271system.cpu.iew.exec_stores 1093 # Number of stores executed
272system.cpu.iew.exec_rate 0.405244 # Inst execution rate
273system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit
274system.cpu.iew.wb_count 9443 # cumulative count of insts written-back
275system.cpu.iew.wb_producers 4951 # num instructions producing a value
276system.cpu.iew.wb_consumers 6720 # num instructions consuming a value
| 271system.cpu.iew.exec_stores 1090 # Number of stores executed
272system.cpu.iew.exec_rate 0.382313 # Inst execution rate
273system.cpu.iew.wb_sent 9558 # cumulative count of insts sent to commit
274system.cpu.iew.wb_count 9419 # cumulative count of insts written-back
275system.cpu.iew.wb_producers 4945 # num instructions producing a value
276system.cpu.iew.wb_consumers 6634 # num instructions consuming a value
|
277system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
| 277system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
278system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle
279system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back
| 278system.cpu.iew.wb_rate 0.367599 # insts written-back per cycle
279system.cpu.iew.wb_fanout 0.745402 # average fanout of values written-back
|
280system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
281system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
282system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions
| 280system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
281system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
282system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions
|
283system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit
| 283system.cpu.commit.commitSquashedInsts 6160 # The number of squashed insts skipped by commit
|
284system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
| 284system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
285system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted
286system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle
287system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle
288system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle
| 285system.cpu.commit.branchMispredicts 444 # The number of times a branch was mispredicted
286system.cpu.commit.committed_per_cycle::samples 13189 # Number of insts commited each cycle
287system.cpu.commit.committed_per_cycle::mean 0.485480 # Number of insts commited each cycle
288system.cpu.commit.committed_per_cycle::stdev 1.291478 # Number of insts commited each cycle
|
289system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
| 289system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
290system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle
291system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle
292system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle
| 290system.cpu.commit.committed_per_cycle::0 10357 78.53% 78.53% # Number of insts commited each cycle
291system.cpu.commit.committed_per_cycle::1 1540 11.68% 90.20% # Number of insts commited each cycle
292system.cpu.commit.committed_per_cycle::2 523 3.97% 94.17% # Number of insts commited each cycle
293system.cpu.commit.committed_per_cycle::3 223 1.69% 95.86% # Number of insts commited each cycle
294system.cpu.commit.committed_per_cycle::4 163 1.24% 97.10% # Number of insts commited each cycle
295system.cpu.commit.committed_per_cycle::5 109 0.83% 97.92% # Number of insts commited each cycle
296system.cpu.commit.committed_per_cycle::6 106 0.80% 98.73% # Number of insts commited each cycle
297system.cpu.commit.committed_per_cycle::7 29 0.22% 98.95% # Number of insts commited each cycle
298system.cpu.commit.committed_per_cycle::8 139 1.05% 100.00% # Number of insts commited each cycle
|
299system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
| 299system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
300system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
301system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
302system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle
| 302system.cpu.commit.committed_per_cycle::total 13189 # Number of insts commited each cycle
|
303system.cpu.commit.committedInsts 6403 # Number of instructions committed
304system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed
305system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
306system.cpu.commit.refs 2050 # Number of memory references committed
307system.cpu.commit.loads 1185 # Number of loads committed
308system.cpu.commit.membars 0 # Number of memory barriers committed
309system.cpu.commit.branches 1051 # Number of branches committed
310system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
311system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
312system.cpu.commit.function_calls 127 # Number of function calls committed.
| 303system.cpu.commit.committedInsts 6403 # Number of instructions committed
304system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed
305system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
306system.cpu.commit.refs 2050 # Number of memory references committed
307system.cpu.commit.loads 1185 # Number of loads committed
308system.cpu.commit.membars 0 # Number of memory barriers committed
309system.cpu.commit.branches 1051 # Number of branches committed
310system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
311system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
312system.cpu.commit.function_calls 127 # Number of function calls committed.
|
313system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached
| 313system.cpu.commit.bw_lim_events 139 # number cycles where commit BW limit reached
|
314system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
| 314system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
315system.cpu.rob.rob_reads 24228 # The number of ROB reads
316system.cpu.rob.rob_writes 26471 # The number of ROB writes
317system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
318system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling
| 315system.cpu.rob.rob_reads 25262 # The number of ROB reads
316system.cpu.rob.rob_writes 26244 # The number of ROB writes
317system.cpu.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself
318system.cpu.idleCycles 11324 # Total number of cycles that the CPU has spent unscheduled due to idling
|
319system.cpu.committedInsts 6386 # Number of Instructions Simulated
320system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated
321system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
| 319system.cpu.committedInsts 6386 # Number of Instructions Simulated
320system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated
321system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
322system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction
323system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads
324system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle
325system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads
326system.cpu.int_regfile_reads 12506 # number of integer regfile reads
327system.cpu.int_regfile_writes 7104 # number of integer regfile writes
| 322system.cpu.cpi 4.012371 # CPI: Cycles Per Instruction
323system.cpu.cpi_total 4.012371 # CPI: Total CPI of All Threads
324system.cpu.ipc 0.249229 # IPC: Instructions Per Cycle
325system.cpu.ipc_total 0.249229 # IPC: Total IPC of All Threads
326system.cpu.int_regfile_reads 12434 # number of integer regfile reads
327system.cpu.int_regfile_writes 7077 # number of integer regfile writes
|
328system.cpu.fp_regfile_reads 8 # number of floating regfile reads
329system.cpu.fp_regfile_writes 2 # number of floating regfile writes
330system.cpu.misc_regfile_reads 1 # number of misc regfile reads
331system.cpu.misc_regfile_writes 1 # number of misc regfile writes
332system.cpu.icache.replacements 0 # number of replacements
| 328system.cpu.fp_regfile_reads 8 # number of floating regfile reads
329system.cpu.fp_regfile_writes 2 # number of floating regfile writes
330system.cpu.misc_regfile_reads 1 # number of misc regfile reads
331system.cpu.misc_regfile_writes 1 # number of misc regfile writes
332system.cpu.icache.replacements 0 # number of replacements
|
333system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use
334system.cpu.icache.total_refs 1829 # Total number of references to valid blocks.
335system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
336system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks.
| 333system.cpu.icache.tagsinuse 159.968477 # Cycle average of tags in use
334system.cpu.icache.total_refs 1800 # Total number of references to valid blocks.
335system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks.
336system.cpu.icache.avg_refs 5.714286 # Average number of references to valid blocks.
|
337system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 337system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
338system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor
339system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy
340system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy
341system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits
342system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits
343system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits
344system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits
345system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits
346system.cpu.icache.overall_hits::total 1829 # number of overall hits
347system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses
348system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses
349system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses
350system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses
351system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses
352system.cpu.icache.overall_misses::total 450 # number of overall misses
353system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles
354system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles
355system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles
356system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles
357system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles
358system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles
359system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses)
360system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses)
361system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses
362system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses
363system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses
364system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses
365system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses
366system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses
367system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses
368system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses
369system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses
370system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses
371system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency
372system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency
373system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency
374system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency
376system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency
| 338system.cpu.icache.occ_blocks::cpu.inst 159.968477 # Average occupied blocks per requestor
339system.cpu.icache.occ_percent::cpu.inst 0.078110 # Average percentage of cache occupancy
340system.cpu.icache.occ_percent::total 0.078110 # Average percentage of cache occupancy
341system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits
342system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits
343system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits
344system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits
345system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits
346system.cpu.icache.overall_hits::total 1800 # number of overall hits
347system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses
348system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses
349system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses
350system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses
351system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses
352system.cpu.icache.overall_misses::total 454 # number of overall misses
353system.cpu.icache.ReadReq_miss_latency::cpu.inst 16294000 # number of ReadReq miss cycles
354system.cpu.icache.ReadReq_miss_latency::total 16294000 # number of ReadReq miss cycles
355system.cpu.icache.demand_miss_latency::cpu.inst 16294000 # number of demand (read+write) miss cycles
356system.cpu.icache.demand_miss_latency::total 16294000 # number of demand (read+write) miss cycles
357system.cpu.icache.overall_miss_latency::cpu.inst 16294000 # number of overall miss cycles
358system.cpu.icache.overall_miss_latency::total 16294000 # number of overall miss cycles
359system.cpu.icache.ReadReq_accesses::cpu.inst 2254 # number of ReadReq accesses(hits+misses)
360system.cpu.icache.ReadReq_accesses::total 2254 # number of ReadReq accesses(hits+misses)
361system.cpu.icache.demand_accesses::cpu.inst 2254 # number of demand (read+write) accesses
362system.cpu.icache.demand_accesses::total 2254 # number of demand (read+write) accesses
363system.cpu.icache.overall_accesses::cpu.inst 2254 # number of overall (read+write) accesses
364system.cpu.icache.overall_accesses::total 2254 # number of overall (read+write) accesses
365system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.201420 # miss rate for ReadReq accesses
366system.cpu.icache.ReadReq_miss_rate::total 0.201420 # miss rate for ReadReq accesses
367system.cpu.icache.demand_miss_rate::cpu.inst 0.201420 # miss rate for demand accesses
368system.cpu.icache.demand_miss_rate::total 0.201420 # miss rate for demand accesses
369system.cpu.icache.overall_miss_rate::cpu.inst 0.201420 # miss rate for overall accesses
370system.cpu.icache.overall_miss_rate::total 0.201420 # miss rate for overall accesses
371system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35889.867841 # average ReadReq miss latency
372system.cpu.icache.ReadReq_avg_miss_latency::total 35889.867841 # average ReadReq miss latency
373system.cpu.icache.demand_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency
374system.cpu.icache.demand_avg_miss_latency::total 35889.867841 # average overall miss latency
375system.cpu.icache.overall_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency
376system.cpu.icache.overall_avg_miss_latency::total 35889.867841 # average overall miss latency
|
377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
| 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
383system.cpu.icache.fast_writes 0 # number of fast writes performed
384system.cpu.icache.cache_copies 0 # number of cache copies performed
|
385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits
386system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits
387system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits
388system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits
389system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits
390system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits
391system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
392system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses
393system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
394system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
395system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
396system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles
398system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles
403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses
404system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses
405system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses
406system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses
407system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses
408system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses
409system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency
410system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency
411system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency
412system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency
413system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency
414system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency
| 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 139 # number of ReadReq MSHR hits
386system.cpu.icache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits
387system.cpu.icache.demand_mshr_hits::cpu.inst 139 # number of demand (read+write) MSHR hits
388system.cpu.icache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits
389system.cpu.icache.overall_mshr_hits::cpu.inst 139 # number of overall MSHR hits
390system.cpu.icache.overall_mshr_hits::total 139 # number of overall MSHR hits
391system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses
392system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses
393system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses
394system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses
395system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses
396system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses
397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11617000 # number of ReadReq MSHR miss cycles
398system.cpu.icache.ReadReq_mshr_miss_latency::total 11617000 # number of ReadReq MSHR miss cycles
399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11617000 # number of demand (read+write) MSHR miss cycles
400system.cpu.icache.demand_mshr_miss_latency::total 11617000 # number of demand (read+write) MSHR miss cycles
401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11617000 # number of overall MSHR miss cycles
402system.cpu.icache.overall_mshr_miss_latency::total 11617000 # number of overall MSHR miss cycles
403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for ReadReq accesses
404system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139752 # mshr miss rate for ReadReq accesses
405system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for demand accesses
406system.cpu.icache.demand_mshr_miss_rate::total 0.139752 # mshr miss rate for demand accesses
407system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for overall accesses
408system.cpu.icache.overall_mshr_miss_rate::total 0.139752 # mshr miss rate for overall accesses
409system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36879.365079 # average ReadReq mshr miss latency
410system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36879.365079 # average ReadReq mshr miss latency
411system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency
412system.cpu.icache.demand_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency
413system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency
414system.cpu.icache.overall_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency
|
415system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
416system.cpu.dcache.replacements 0 # number of replacements
| 415system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
416system.cpu.dcache.replacements 0 # number of replacements
|
417system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use
418system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks.
419system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks.
420system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks.
| 417system.cpu.dcache.tagsinuse 107.786985 # Cycle average of tags in use
418system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks.
419system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
420system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks.
|
421system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 421system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
422system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor
423system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy
424system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy
425system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits
426system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits
427system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits
428system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits
429system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits
430system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits
431system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits
432system.cpu.dcache.overall_hits::total 2275 # number of overall hits
433system.cpu.dcache.ReadReq_misses::cpu.data 146 # number of ReadReq misses
434system.cpu.dcache.ReadReq_misses::total 146 # number of ReadReq misses
435system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses
436system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses
437system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses
438system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses
439system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses
440system.cpu.dcache.overall_misses::total 502 # number of overall misses
441system.cpu.dcache.ReadReq_miss_latency::cpu.data 5337000 # number of ReadReq miss cycles
442system.cpu.dcache.ReadReq_miss_latency::total 5337000 # number of ReadReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::cpu.data 12518000 # number of WriteReq miss cycles
444system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles
445system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles
446system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles
447system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles
448system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles
449system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses)
450system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses)
| 422system.cpu.dcache.occ_blocks::cpu.data 107.786985 # Average occupied blocks per requestor
423system.cpu.dcache.occ_percent::cpu.data 0.026315 # Average percentage of cache occupancy
424system.cpu.dcache.occ_percent::total 0.026315 # Average percentage of cache occupancy
425system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits
426system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits
427system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
428system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
429system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits
430system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits
431system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits
432system.cpu.dcache.overall_hits::total 2240 # number of overall hits
433system.cpu.dcache.ReadReq_misses::cpu.data 161 # number of ReadReq misses
434system.cpu.dcache.ReadReq_misses::total 161 # number of ReadReq misses
435system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
436system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
437system.cpu.dcache.demand_misses::cpu.data 520 # number of demand (read+write) misses
438system.cpu.dcache.demand_misses::total 520 # number of demand (read+write) misses
439system.cpu.dcache.overall_misses::cpu.data 520 # number of overall misses
440system.cpu.dcache.overall_misses::total 520 # number of overall misses
441system.cpu.dcache.ReadReq_miss_latency::cpu.data 6422000 # number of ReadReq miss cycles
442system.cpu.dcache.ReadReq_miss_latency::total 6422000 # number of ReadReq miss cycles
443system.cpu.dcache.WriteReq_miss_latency::cpu.data 15048500 # number of WriteReq miss cycles
444system.cpu.dcache.WriteReq_miss_latency::total 15048500 # number of WriteReq miss cycles
445system.cpu.dcache.demand_miss_latency::cpu.data 21470500 # number of demand (read+write) miss cycles
446system.cpu.dcache.demand_miss_latency::total 21470500 # number of demand (read+write) miss cycles
447system.cpu.dcache.overall_miss_latency::cpu.data 21470500 # number of overall miss cycles
448system.cpu.dcache.overall_miss_latency::total 21470500 # number of overall miss cycles
449system.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses)
450system.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses)
|
451system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
452system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
| 451system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
452system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
453system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses
454system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses
455system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses
456system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses
457system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses
458system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses
459system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
460system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
461system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses
462system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses
463system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses
464system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses
465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency
466system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency
467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency
468system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency
469system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency
470system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency
472system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency
| 453system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses
454system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses
455system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses
456system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses
457system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084960 # miss rate for ReadReq accesses
458system.cpu.dcache.ReadReq_miss_rate::total 0.084960 # miss rate for ReadReq accesses
459system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
460system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
461system.cpu.dcache.demand_miss_rate::cpu.data 0.188406 # miss rate for demand accesses
462system.cpu.dcache.demand_miss_rate::total 0.188406 # miss rate for demand accesses
463system.cpu.dcache.overall_miss_rate::cpu.data 0.188406 # miss rate for overall accesses
464system.cpu.dcache.overall_miss_rate::total 0.188406 # miss rate for overall accesses
465system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39888.198758 # average ReadReq miss latency
466system.cpu.dcache.ReadReq_avg_miss_latency::total 39888.198758 # average ReadReq miss latency
467system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41917.827298 # average WriteReq miss latency
468system.cpu.dcache.WriteReq_avg_miss_latency::total 41917.827298 # average WriteReq miss latency
469system.cpu.dcache.demand_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency
470system.cpu.dcache.demand_avg_miss_latency::total 41289.423077 # average overall miss latency
471system.cpu.dcache.overall_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency
472system.cpu.dcache.overall_avg_miss_latency::total 41289.423077 # average overall miss latency
|
473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
479system.cpu.dcache.fast_writes 0 # number of fast writes performed
480system.cpu.dcache.cache_copies 0 # number of cache copies performed
| 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
474system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
476system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
477system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
478system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
479system.cpu.dcache.fast_writes 0 # number of fast writes performed
480system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
482system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits
484system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits
485system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits
486system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits
487system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits
488system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits
489system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
490system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses
491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
492system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
493system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
494system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
495system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
496system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses
497system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles
498system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles
499system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles
500system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles
501system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles
502system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles
503system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles
504system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles
505system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # mshr miss rate for ReadReq accesses
506system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054393 # mshr miss rate for ReadReq accesses
507system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
508system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
509system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses
510system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses
511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses
512system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # average ReadReq mshr miss latency
514system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692 # average ReadReq mshr miss latency
515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889 # average WriteReq mshr miss latency
516system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889 # average WriteReq mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency
518system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency
519system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency
520system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency
| 481system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
482system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
483system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
484system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
485system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits
486system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits
487system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits
488system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits
489system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses
490system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses
491system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
492system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
493system.cpu.dcache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses
494system.cpu.dcache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
495system.cpu.dcache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses
496system.cpu.dcache.overall_mshr_misses::total 175 # number of overall MSHR misses
497system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4236500 # number of ReadReq MSHR miss cycles
498system.cpu.dcache.ReadReq_mshr_miss_latency::total 4236500 # number of ReadReq MSHR miss cycles
499system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2874500 # number of WriteReq MSHR miss cycles
500system.cpu.dcache.WriteReq_mshr_miss_latency::total 2874500 # number of WriteReq MSHR miss cycles
501system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7111000 # number of demand (read+write) MSHR miss cycles
502system.cpu.dcache.demand_mshr_miss_latency::total 7111000 # number of demand (read+write) MSHR miss cycles
503system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7111000 # number of overall MSHR miss cycles
504system.cpu.dcache.overall_mshr_miss_latency::total 7111000 # number of overall MSHR miss cycles
505system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses
506system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses
507system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
508system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
509system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for demand accesses
510system.cpu.dcache.demand_mshr_miss_rate::total 0.063406 # mshr miss rate for demand accesses
511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for overall accesses
512system.cpu.dcache.overall_mshr_miss_rate::total 0.063406 # mshr miss rate for overall accesses
513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41534.313725 # average ReadReq mshr miss latency
514system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41534.313725 # average ReadReq mshr miss latency
515system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39376.712329 # average WriteReq mshr miss latency
516system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39376.712329 # average WriteReq mshr miss latency
517system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40634.285714 # average overall mshr miss latency
518system.cpu.dcache.demand_avg_mshr_miss_latency::total 40634.285714 # average overall mshr miss latency
519system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40634.285714 # average overall mshr miss latency
520system.cpu.dcache.overall_avg_mshr_miss_latency::total 40634.285714 # average overall mshr miss latency
|
521system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
522system.cpu.l2cache.replacements 0 # number of replacements
| 521system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
522system.cpu.l2cache.replacements 0 # number of replacements
|
523system.cpu.l2cache.tagsinuse 224.380125 # Cycle average of tags in use
| 523system.cpu.l2cache.tagsinuse 220.452556 # Cycle average of tags in use
|
524system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
| 524system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
525system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
526system.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks.
| 525system.cpu.l2cache.sampled_refs 415 # Sample count of references to valid blocks.
526system.cpu.l2cache.avg_refs 0.002410 # Average number of references to valid blocks.
|
527system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
| 527system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
528system.cpu.l2cache.occ_blocks::cpu.inst 161.620273 # Average occupied blocks per requestor
529system.cpu.l2cache.occ_blocks::cpu.data 62.759852 # Average occupied blocks per requestor
530system.cpu.l2cache.occ_percent::cpu.inst 0.004932 # Average percentage of cache occupancy
531system.cpu.l2cache.occ_percent::cpu.data 0.001915 # Average percentage of cache occupancy
532system.cpu.l2cache.occ_percent::total 0.006848 # Average percentage of cache occupancy
| 528system.cpu.l2cache.occ_blocks::cpu.inst 159.940532 # Average occupied blocks per requestor
529system.cpu.l2cache.occ_blocks::cpu.data 60.512024 # Average occupied blocks per requestor
530system.cpu.l2cache.occ_percent::cpu.inst 0.004881 # Average percentage of cache occupancy
531system.cpu.l2cache.occ_percent::cpu.data 0.001847 # Average percentage of cache occupancy
532system.cpu.l2cache.occ_percent::total 0.006728 # Average percentage of cache occupancy
|
533system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
534system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
535system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
536system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
537system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
538system.cpu.l2cache.overall_hits::total 1 # number of overall hits
| 533system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
534system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
535system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
536system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
537system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
538system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
539system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses
540system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses
| 539system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses
540system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
|
541system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses
| 541system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses
|
542system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses
543system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
544system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses
545system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses
546system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses
547system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses
548system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses
549system.cpu.l2cache.overall_misses::total 488 # number of overall misses
550system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10703000 # number of ReadReq miss cycles
551system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3603500 # number of ReadReq miss cycles
552system.cpu.l2cache.ReadReq_miss_latency::total 14306500 # number of ReadReq miss cycles
553system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2489000 # number of ReadExReq miss cycles
554system.cpu.l2cache.ReadExReq_miss_latency::total 2489000 # number of ReadExReq miss cycles
555system.cpu.l2cache.demand_miss_latency::cpu.inst 10703000 # number of demand (read+write) miss cycles
556system.cpu.l2cache.demand_miss_latency::cpu.data 6092500 # number of demand (read+write) miss cycles
557system.cpu.l2cache.demand_miss_latency::total 16795500 # number of demand (read+write) miss cycles
558system.cpu.l2cache.overall_miss_latency::cpu.inst 10703000 # number of overall miss cycles
559system.cpu.l2cache.overall_miss_latency::cpu.data 6092500 # number of overall miss cycles
560system.cpu.l2cache.overall_miss_latency::total 16795500 # number of overall miss cycles
561system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses)
562system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses)
| 542system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
543system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
544system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses
545system.cpu.l2cache.demand_misses::cpu.data 175 # number of demand (read+write) misses
546system.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses
547system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses
548system.cpu.l2cache.overall_misses::cpu.data 175 # number of overall misses
549system.cpu.l2cache.overall_misses::total 489 # number of overall misses
550system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11286500 # number of ReadReq miss cycles
551system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4103500 # number of ReadReq miss cycles
552system.cpu.l2cache.ReadReq_miss_latency::total 15390000 # number of ReadReq miss cycles
553system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2793500 # number of ReadExReq miss cycles
554system.cpu.l2cache.ReadExReq_miss_latency::total 2793500 # number of ReadExReq miss cycles
555system.cpu.l2cache.demand_miss_latency::cpu.inst 11286500 # number of demand (read+write) miss cycles
556system.cpu.l2cache.demand_miss_latency::cpu.data 6897000 # number of demand (read+write) miss cycles
557system.cpu.l2cache.demand_miss_latency::total 18183500 # number of demand (read+write) miss cycles
558system.cpu.l2cache.overall_miss_latency::cpu.inst 11286500 # number of overall miss cycles
559system.cpu.l2cache.overall_miss_latency::cpu.data 6897000 # number of overall miss cycles
560system.cpu.l2cache.overall_miss_latency::total 18183500 # number of overall miss cycles
561system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses)
562system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses)
|
563system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses)
| 563system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses)
|
564system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
565system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
566system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses
567system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses
568system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses
569system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses
570system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses
571system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses
572system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses
| 564system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
565system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
566system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses
567system.cpu.l2cache.demand_accesses::cpu.data 175 # number of demand (read+write) accesses
568system.cpu.l2cache.demand_accesses::total 490 # number of demand (read+write) accesses
569system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses
570system.cpu.l2cache.overall_accesses::cpu.data 175 # number of overall (read+write) accesses
571system.cpu.l2cache.overall_accesses::total 490 # number of overall (read+write) accesses
572system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses
|
573system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
574system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses
575system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
576system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
| 573system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
574system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses
575system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
576system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
577system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
| 577system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses
|
578system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
| 578system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
579system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses
580system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
| 579system.cpu.l2cache.demand_miss_rate::total 0.997959 # miss rate for demand accesses
580system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses
|
581system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
| 581system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
582system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
583system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179 # average ReadReq miss latency
584system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency
585system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency
586system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency
587system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency
588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency
590system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency
591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency
592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency
593system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency
| 582system.cpu.l2cache.overall_miss_rate::total 0.997959 # miss rate for overall accesses
583system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35944.267516 # average ReadReq miss latency
584system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40230.392157 # average ReadReq miss latency
585system.cpu.l2cache.ReadReq_avg_miss_latency::total 36995.192308 # average ReadReq miss latency
586system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38267.123288 # average ReadExReq miss latency
587system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38267.123288 # average ReadExReq miss latency
588system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency
589system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency
590system.cpu.l2cache.demand_avg_miss_latency::total 37185.071575 # average overall miss latency
591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency
592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency
593system.cpu.l2cache.overall_avg_miss_latency::total 37185.071575 # average overall miss latency
|
594system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
596system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
597system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
598system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
599system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
600system.cpu.l2cache.fast_writes 0 # number of fast writes performed
601system.cpu.l2cache.cache_copies 0 # number of cache copies performed
| 594system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
595system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
596system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
597system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
598system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
599system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
600system.cpu.l2cache.fast_writes 0 # number of fast writes performed
601system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
602system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses
603system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses
| 602system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses
603system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses
|
604system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses
| 604system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses
|
605system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses
606system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
607system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses
608system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses
609system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses
610system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses
611system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses
612system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses
613system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles
614system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles
615system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles
616system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles
617system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles
618system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles
619system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles
620system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles
621system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles
622system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles
623system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles
624system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
| 605system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
606system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
607system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses
608system.cpu.l2cache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses
609system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses
610system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses
611system.cpu.l2cache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses
612system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses
613system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10285500 # number of ReadReq MSHR miss cycles
614system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3793000 # number of ReadReq MSHR miss cycles
615system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14078500 # number of ReadReq MSHR miss cycles
616system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2567500 # number of ReadExReq MSHR miss cycles
617system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2567500 # number of ReadExReq MSHR miss cycles
618system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10285500 # number of demand (read+write) MSHR miss cycles
619system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6360500 # number of demand (read+write) MSHR miss cycles
620system.cpu.l2cache.demand_mshr_miss_latency::total 16646000 # number of demand (read+write) MSHR miss cycles
621system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10285500 # number of overall MSHR miss cycles
622system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6360500 # number of overall MSHR miss cycles
623system.cpu.l2cache.overall_mshr_miss_latency::total 16646000 # number of overall MSHR miss cycles
624system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses
|
625system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
626system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses
627system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
628system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
| 625system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
626system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses
627system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
628system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
629system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
| 629system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses
|
630system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
| 630system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
631system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses
632system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
| 631system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses
632system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses
|
633system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
| 633system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
634system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency
636system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency
637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency
638system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency
639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency
640system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency
641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency
642system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency
643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency
644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency
645system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency
| 634system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses
635system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32756.369427 # average ReadReq mshr miss latency
636system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37186.274510 # average ReadReq mshr miss latency
637system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33842.548077 # average ReadReq mshr miss latency
638system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877 # average ReadExReq mshr miss latency
639system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877 # average ReadExReq mshr miss latency
640system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency
641system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency
642system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency
643system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency
644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency
645system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency
|
646system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
647
648---------- End Simulation Statistics ----------
| 646system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
647
648---------- End Simulation Statistics ----------
|