| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12450500 # Number of ticks simulated 5final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12450500 # Number of ticks simulated 5final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 87465 # Simulator instruction rate (inst/s) 8host_op_rate 87444 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 170447462 # Simulator tick rate (ticks/s) 10host_mem_usage 210080 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 42940 # Simulator instruction rate (inst/s) 8host_op_rate 42933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 83690683 # Simulator tick rate (ticks/s) 10host_mem_usage 215012 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 6386 # Number of instructions simulated 13sim_ops 6386 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 31360 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 490 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 340 unchanged lines hidden (view full) --- 360system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses 361system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency 362system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 363system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 364system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 365system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 366system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 367system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 6386 # Number of instructions simulated 13sim_ops 6386 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 31360 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 490 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 340 unchanged lines hidden (view full) --- 360system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses 361system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency 362system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 363system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 364system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 365system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 366system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 367system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 368system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 369system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 368system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 369system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 370system.cpu.icache.fast_writes 0 # number of fast writes performed 371system.cpu.icache.cache_copies 0 # number of cache copies performed 372system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits 373system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits 374system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits 375system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits 376system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits 377system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 442system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency 445system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency 446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 370system.cpu.icache.fast_writes 0 # number of fast writes performed 371system.cpu.icache.cache_copies 0 # number of cache copies performed 372system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits 373system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits 374system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits 375system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits 376system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits 377system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 442system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency 445system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency 446system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 447system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 448system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 450system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 450system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 452system.cpu.dcache.fast_writes 0 # number of fast writes performed 453system.cpu.dcache.cache_copies 0 # number of cache copies performed 454system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 455system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 458system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits 459system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 547system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 548system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 551system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 552system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 452system.cpu.dcache.fast_writes 0 # number of fast writes performed 453system.cpu.dcache.cache_copies 0 # number of cache copies performed 454system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 455system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits 456system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 458system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits 459system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 547system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 548system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 549system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 550system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 551system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 552system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 554system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 555system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 555system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 556system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 557system.cpu.l2cache.fast_writes 0 # number of fast writes performed 558system.cpu.l2cache.cache_copies 0 # number of cache copies performed 559system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 560system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 561system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 563system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 564system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 557system.cpu.l2cache.fast_writes 0 # number of fast writes performed 558system.cpu.l2cache.cache_copies 0 # number of cache copies performed 559system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 560system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 561system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses 562system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 563system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 564system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |