| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23776000 # Number of ticks simulated 5final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23776000 # Number of ticks simulated 5final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 4743 # Simulator instruction rate (inst/s) 8host_op_rate 4743 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17659718 # Simulator tick rate (ticks/s) 10host_mem_usage 236044 # Number of bytes of host memory used 11host_seconds 1.35 # Real time elapsed on the host | 7host_inst_rate 135386 # Simulator instruction rate (inst/s) 8host_op_rate 135348 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 503875461 # Simulator tick rate (ticks/s) 10host_mem_usage 253920 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states | 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.inst 19904 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 30976 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19904 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19904 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 311 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::total 485 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) | 24system.physmem.num_reads::total 484 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 837146703 # Total read bandwidth from this memory (bytes/s) |
| 26system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) | 26system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) |
| 27system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) | 27system.physmem.bw_read::total 1302826380 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 837146703 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 837146703 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 837146703 # Total bandwidth to/from this memory (bytes/s) |
| 31system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) | 31system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 485 # Number of read requests accepted | 32system.physmem.bw_total::total 1302826380 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 484 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 484 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 30976 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 30976 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 69 # Per bank write bursts 46system.physmem.perBankRdBursts::1 32 # Per bank write bursts | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 69 # Per bank write bursts 46system.physmem.perBankRdBursts::1 32 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::2 33 # Per bank write bursts | 47system.physmem.perBankRdBursts::2 32 # Per bank write bursts |
| 48system.physmem.perBankRdBursts::3 47 # Per bank write bursts 49system.physmem.perBankRdBursts::4 42 # Per bank write bursts 50system.physmem.perBankRdBursts::5 20 # Per bank write bursts 51system.physmem.perBankRdBursts::6 1 # Per bank write bursts 52system.physmem.perBankRdBursts::7 3 # Per bank write bursts 53system.physmem.perBankRdBursts::8 0 # Per bank write bursts 54system.physmem.perBankRdBursts::9 1 # Per bank write bursts 55system.physmem.perBankRdBursts::10 22 # Per bank write bursts --- 22 unchanged lines hidden (view full) --- 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 23381000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 48system.physmem.perBankRdBursts::3 47 # Per bank write bursts 49system.physmem.perBankRdBursts::4 42 # Per bank write bursts 50system.physmem.perBankRdBursts::5 20 # Per bank write bursts 51system.physmem.perBankRdBursts::6 1 # Per bank write bursts 52system.physmem.perBankRdBursts::7 3 # Per bank write bursts 53system.physmem.perBankRdBursts::8 0 # Per bank write bursts 54system.physmem.perBankRdBursts::9 1 # Per bank write bursts 55system.physmem.perBankRdBursts::10 22 # Per bank write bursts --- 22 unchanged lines hidden (view full) --- 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 23381000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 485 # Read request sizes (log2) | 86system.physmem.readPktSize::6 484 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation | 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 79 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation |
| 191system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation | 191system.physmem.bytesPerActivate::mean 347.325843 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 230.027877 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 312.328054 # Bytes accessed per row activation |
| 194system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation |
| 204system.physmem.totQLat 8008750 # Total ticks spent queuing 205system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst | 204system.physmem.totQLat 8020750 # Total ticks spent queuing 205system.physmem.totMemAccLat 17095750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2420000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16571.80 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 35321.80 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1302.83 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1302.83 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 10.20 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 10.18 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 395 # Number of row buffer hits during reads | 220system.physmem.readRowHits 394 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 81.40 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 48208.25 # Average gap between requests 225system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined | 224system.physmem.avgGap 48307.85 # Average gap between requests 225system.physmem.pageHitRate 81.40 # Row buffer hit rate, read and write combined |
| 226system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) | 226system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) | 228system.physmem_0.readEnergy 1756440 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) | 231system.physmem_0.actBackEnergy 3000480 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 47040 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 7630020 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 131040 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) 237system.physmem_0.averagePower 621.784975 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank | 236system.physmem_0.totalEnergy 14776935 # Total energy per rank (pJ) 237system.physmem_0.averagePower 621.499816 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 16971750 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states | 242system.physmem_0.memoryStateTime::PRE_PDN 340500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 5886000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16729000 # Time in different power states |
| 245system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 245system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) | 250system.physmem_1.actBackEnergy 2975400 # Energy for active background per rank (pJ) |
| 251system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) | 251system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) |
| 252system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) | 252system.physmem_1.actPowerDownEnergy 7630590 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 68640 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) 256system.physmem_1.averagePower 629.216130 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank | 255system.physmem_1.totalEnergy 14960310 # Total energy per rank (pJ) 256system.physmem_1.averagePower 629.212344 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 16765250 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states | 258system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states |
| 262system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states | 262system.physmem_1.memoryStateTime::ACT 5879250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 16724250 # Time in different power states |
| 264system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states | 264system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 265system.cpu.branchPred.lookups 2854 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 713 # Number of BTB hits | 265system.cpu.branchPred.lookups 2851 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1679 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 484 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2196 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 719 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. | 271system.cpu.branchPred.BTBHitPct 32.741348 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. |
| 273system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. | 273system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. | 274system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. |
| 275system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. | 275system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. |
| 276system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. | 276system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. |
| 277system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses | 277system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 283system.cpu.dtb.read_hits 2252 # DTB read hits | 283system.cpu.dtb.read_hits 2241 # DTB read hits |
| 284system.cpu.dtb.read_misses 48 # DTB read misses 285system.cpu.dtb.read_acv 0 # DTB read access violations | 284system.cpu.dtb.read_misses 48 # DTB read misses 285system.cpu.dtb.read_acv 0 # DTB read access violations |
| 286system.cpu.dtb.read_accesses 2300 # DTB read accesses 287system.cpu.dtb.write_hits 1038 # DTB write hits | 286system.cpu.dtb.read_accesses 2289 # DTB read accesses 287system.cpu.dtb.write_hits 1046 # DTB write hits |
| 288system.cpu.dtb.write_misses 28 # DTB write misses 289system.cpu.dtb.write_acv 0 # DTB write access violations | 288system.cpu.dtb.write_misses 28 # DTB write misses 289system.cpu.dtb.write_acv 0 # DTB write access violations |
| 290system.cpu.dtb.write_accesses 1066 # DTB write accesses 291system.cpu.dtb.data_hits 3290 # DTB hits | 290system.cpu.dtb.write_accesses 1074 # DTB write accesses 291system.cpu.dtb.data_hits 3287 # DTB hits |
| 292system.cpu.dtb.data_misses 76 # DTB misses 293system.cpu.dtb.data_acv 0 # DTB access violations | 292system.cpu.dtb.data_misses 76 # DTB misses 293system.cpu.dtb.data_acv 0 # DTB access violations |
| 294system.cpu.dtb.data_accesses 3366 # DTB accesses 295system.cpu.itb.fetch_hits 2295 # ITB hits | 294system.cpu.dtb.data_accesses 3363 # DTB accesses 295system.cpu.itb.fetch_hits 2298 # ITB hits |
| 296system.cpu.itb.fetch_misses 27 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv | 296system.cpu.itb.fetch_misses 27 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv |
| 298system.cpu.itb.fetch_accesses 2322 # ITB accesses | 298system.cpu.itb.fetch_accesses 2325 # ITB accesses |
| 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 47553 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 47553 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 316system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss 317system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing | 316system.cpu.fetch.icacheStallCycles 8497 # Number of cycles fetch is stalled on an Icache miss 317system.cpu.fetch.Insts 16552 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 2851 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 1186 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 5772 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 1050 # Number of cycles fetch has spent squashing |
| 322system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps | 322system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps |
| 324system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total) | 324system.cpu.fetch.CacheLines 2298 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 15472 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.069804 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.455665 # Number of instructions fetched each cycle (Total) |
| 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 330system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) | 330system.cpu.fetch.rateDist::0 12480 80.66% 80.66% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 299 1.93% 82.59% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 231 1.49% 84.09% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 265 1.71% 85.80% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 295 1.91% 87.71% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 231 1.49% 89.20% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 280 1.81% 91.01% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 147 0.95% 91.96% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 1244 8.04% 100.00% # Number of instructions fetched each cycle (Total) |
| 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 342system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch | 342system.cpu.fetch.rateDist::total 15472 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.059954 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.348075 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 8344 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 4012 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 2454 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 211 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 451 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 754 # Number of times decode resolved a branch |
| 351system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction | 351system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction |
| 352system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode | 352system.cpu.decode.DecodedInsts 14992 # Number of instructions handled by decode |
| 353system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode | 353system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode |
| 354system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking | 354system.cpu.rename.SquashCycles 451 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 8504 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 1836 # Number of cycles rename is blocking |
| 357system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst | 357system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst |
| 358system.cpu.rename.RunCycles 2476 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename | 358system.cpu.rename.RunCycles 2480 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 14425 # Number of instructions processed by rename |
| 361system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full | 361system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full |
| 364system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups | 364system.cpu.rename.SQFullEvents 1479 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 10912 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 17882 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 17873 # Number of integer rename lookups |
| 368system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed | 368system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed |
| 370system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing | 370system.cpu.rename.UndoneMaps 6335 # Number of HB maps that are undone due to squashing |
| 371system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed | 371system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed |
| 373system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. | 373system.cpu.rename.skidInsts 586 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2823 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1299 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. |
| 377system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. | 377system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. |
| 378system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) | 378system.cpu.iq.iqInstsAdded 13035 # Number of instructions added to the IQ (excludes non-spec) |
| 379system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ | 379system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ |
| 380system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued | 380system.cpu.iq.iqInstsIssued 10770 # Number of instructions issued |
| 381system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued | 381system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued |
| 382system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph | 382system.cpu.iq.iqSquashedInstsExamined 6676 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 3655 # Number of squashed operands that are examined and possibly removed from graph |
| 384system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed | 384system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed |
| 385system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle | 385system.cpu.iq.issued_per_cycle::samples 15472 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.696096 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.440906 # Number of insts issued each cycle |
| 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 389system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle | 389system.cpu.iq.issued_per_cycle::0 11426 73.85% 73.85% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1307 8.45% 82.30% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 919 5.94% 88.24% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 676 4.37% 92.61% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 515 3.33% 95.93% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::5 346 2.24% 98.17% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::6 202 1.31% 99.48% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 53 0.34% 99.82% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 28 0.18% 100.00% # Number of insts issued each cycle |
| 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 401system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle | 401system.cpu.iq.issued_per_cycle::total 15472 # Number of insts issued each cycle |
| 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 403system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.89% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available 434system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available 435system.cpu.iq.fu_full::MemWrite 36 25.53% 99.29% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.29% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatMemWrite 1 0.71% 100.00% # attempts to use FU when none available | 403system.cpu.iq.fu_full::IntAlu 21 14.79% 14.79% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 14.79% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 14.79% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.79% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.79% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.79% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 14.79% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.79% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.79% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.79% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.79% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.79% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.79% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.79% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.79% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.79% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdMult 0 0.00% 14.79% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.79% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdShift 0 0.00% 14.79% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.79% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.79% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.79% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.79% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.79% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.79% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.79% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.79% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.79% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.79% # attempts to use FU when none available 434system.cpu.iq.fu_full::MemRead 83 58.45% 73.24% # attempts to use FU when none available 435system.cpu.iq.fu_full::MemWrite 37 26.06% 99.30% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.30% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatMemWrite 1 0.70% 100.00% # attempts to use FU when none available |
| 438system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 440system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 438system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 440system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 441system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued 442system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued 443system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued 446system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.72% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.72% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued 472system.cpu.iq.FU_type_0::MemRead 2474 22.96% 89.68% # Type of FU issued 473system.cpu.iq.FU_type_0::MemWrite 1104 10.24% 99.93% # Type of FU issued | 441system.cpu.iq.FU_type_0::IntAlu 7179 66.66% 66.68% # Type of FU issued 442system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.69% # Type of FU issued 443system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.70% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued 446system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.70% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.70% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued 472system.cpu.iq.FU_type_0::MemRead 2465 22.89% 89.59% # Type of FU issued 473system.cpu.iq.FU_type_0::MemWrite 1113 10.33% 99.93% # Type of FU issued |
| 474system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 474system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 478system.cpu.iq.FU_type_0::total 10776 # Type of FU issued 479system.cpu.iq.rate 0.226610 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 141 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses | 478system.cpu.iq.FU_type_0::total 10770 # Type of FU issued 479system.cpu.iq.rate 0.226484 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 142 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.013185 # FU busy rate (busy events/executed inst) 482system.cpu.iq.int_inst_queue_reads 37150 # Number of integer instruction queue reads 483system.cpu.iq.int_inst_queue_writes 19749 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 9744 # Number of integer instruction queue wakeup accesses |
| 485system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses | 485system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses |
| 488system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses | 488system.cpu.iq.int_alu_accesses 10899 # Number of integer alu accesses |
| 489system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 489system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 491system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 492system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed | 492system.cpu.iew.lsq.thread0.squashedLoads 1638 # Number of loads squashed |
| 493system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations | 493system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 494system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations |
| 495system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed | 495system.cpu.iew.lsq.thread0.squashedStores 434 # Number of stores squashed |
| 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 498system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 496system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 497system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 498system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 499system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked 500system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 501system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking | 501system.cpu.iew.iewSquashCycles 451 # Number of cycles IEW is squashing 502system.cpu.iew.iewBlockCycles 1424 # Number of cycles IEW is blocking |
| 503system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking | 503system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking |
| 504system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ | 504system.cpu.iew.iewDispatchedInsts 13146 # Number of instructions dispatched to IQ |
| 505system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch | 505system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch |
| 506system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions | 506system.cpu.iew.iewDispLoadInsts 2823 # Number of dispatched load instructions 507system.cpu.iew.iewDispStoreInsts 1299 # Number of dispatched store instructions |
| 508system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations | 508system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 509system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 510system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall 511system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations |
| 512system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute | 512system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 513system.cpu.iew.predictedNotTakenIncorrect 389 # Number of branches that were predicted not taken incorrectly 514system.cpu.iew.branchMispredicts 499 # Number of branch mispredicts detected at execute 515system.cpu.iew.iewExecutedInsts 10283 # Number of executed instructions 516system.cpu.iew.iewExecLoadInsts 2289 # Number of load instructions executed 517system.cpu.iew.iewExecSquashedInsts 487 # Number of squashed instructions skipped in execute |
| 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 84 # number of nop insts executed | 518system.cpu.iew.exec_swp 0 # number of swp insts executed 519system.cpu.iew.exec_nop 84 # number of nop insts executed |
| 520system.cpu.iew.exec_refs 3376 # number of memory reference insts executed 521system.cpu.iew.exec_branches 1642 # Number of branches executed 522system.cpu.iew.exec_stores 1076 # Number of stores executed 523system.cpu.iew.exec_rate 0.216390 # Inst execution rate 524system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 9755 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 5155 # num instructions producing a value | 520system.cpu.iew.exec_refs 3373 # number of memory reference insts executed 521system.cpu.iew.exec_branches 1639 # Number of branches executed 522system.cpu.iew.exec_stores 1084 # Number of stores executed 523system.cpu.iew.exec_rate 0.216243 # Inst execution rate 524system.cpu.iew.wb_sent 9942 # cumulative count of insts sent to commit 525system.cpu.iew.wb_count 9754 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 5150 # num instructions producing a value |
| 527system.cpu.iew.wb_consumers 7025 # num instructions consuming a value | 527system.cpu.iew.wb_consumers 7025 # num instructions consuming a value |
| 528system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle 529system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back 530system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit | 528system.cpu.iew.wb_rate 0.205118 # insts written-back per cycle 529system.cpu.iew.wb_fanout 0.733096 # average fanout of values written-back 530system.cpu.commit.commitSquashedInsts 6693 # The number of squashed insts skipped by commit |
| 531system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards | 531system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards |
| 532system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted 533system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle | 532system.cpu.commit.branchMispredicts 410 # The number of times a branch was mispredicted 533system.cpu.commit.committed_per_cycle::samples 14238 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::mean 0.449642 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::stdev 1.359190 # Number of insts commited each cycle |
| 536system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 536system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 537system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle | 537system.cpu.commit.committed_per_cycle::0 11808 82.93% 82.93% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::1 1161 8.15% 91.09% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::2 469 3.29% 94.38% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::3 204 1.43% 95.81% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::4 134 0.94% 96.76% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::5 86 0.60% 97.36% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::6 97 0.68% 98.04% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::7 89 0.63% 98.67% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::8 190 1.33% 100.00% # Number of insts commited each cycle |
| 546system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 546system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 549system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle | 549system.cpu.commit.committed_per_cycle::total 14238 # Number of insts commited each cycle |
| 550system.cpu.commit.committedInsts 6402 # Number of instructions committed 551system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 552system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 553system.cpu.commit.refs 2050 # Number of memory references committed 554system.cpu.commit.loads 1185 # Number of loads committed 555system.cpu.commit.membars 0 # Number of memory barriers committed 556system.cpu.commit.branches 1056 # Number of branches committed 557system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 591system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 592system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction 593system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 598system.cpu.commit.op_class_0::total 6402 # Class of committed instruction | 550system.cpu.commit.committedInsts 6402 # Number of instructions committed 551system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 552system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 553system.cpu.commit.refs 2050 # Number of memory references committed 554system.cpu.commit.loads 1185 # Number of loads committed 555system.cpu.commit.membars 0 # Number of memory barriers committed 556system.cpu.commit.branches 1056 # Number of branches committed 557system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 591system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 592system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction 593system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 598system.cpu.commit.op_class_0::total 6402 # Class of committed instruction |
| 599system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached | 599system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached |
| 600system.cpu.rob.rob_reads 26792 # The number of ROB reads | 600system.cpu.rob.rob_reads 26792 # The number of ROB reads |
| 601system.cpu.rob.rob_writes 27482 # The number of ROB writes | 601system.cpu.rob.rob_writes 27441 # The number of ROB writes |
| 602system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself | 602system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 603system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling | 603system.cpu.idleCycles 32081 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 604system.cpu.committedInsts 6385 # Number of Instructions Simulated 605system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 606system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 607system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 608system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 609system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads | 604system.cpu.committedInsts 6385 # Number of Instructions Simulated 605system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 606system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 607system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 608system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 609system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads |
| 610system.cpu.int_regfile_reads 12923 # number of integer regfile reads 611system.cpu.int_regfile_writes 7437 # number of integer regfile writes | 610system.cpu.int_regfile_reads 13028 # number of integer regfile reads 611system.cpu.int_regfile_writes 7426 # number of integer regfile writes |
| 612system.cpu.fp_regfile_reads 8 # number of floating regfile reads 613system.cpu.fp_regfile_writes 2 # number of floating regfile writes 614system.cpu.misc_regfile_reads 1 # number of misc regfile reads 615system.cpu.misc_regfile_writes 1 # number of misc regfile writes 616system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 617system.cpu.dcache.tags.replacements 0 # number of replacements | 612system.cpu.fp_regfile_reads 8 # number of floating regfile reads 613system.cpu.fp_regfile_writes 2 # number of floating regfile writes 614system.cpu.misc_regfile_reads 1 # number of misc regfile reads 615system.cpu.misc_regfile_writes 1 # number of misc regfile writes 616system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 617system.cpu.dcache.tags.replacements 0 # number of replacements |
| 618system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use 619system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. | 618system.cpu.dcache.tags.tagsinuse 110.199847 # Cycle average of tags in use 619system.cpu.dcache.tags.total_refs 2391 # Total number of references to valid blocks. |
| 620system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. | 620system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. |
| 621system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. | 621system.cpu.dcache.tags.avg_refs 13.820809 # Average number of references to valid blocks. |
| 622system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 622system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 623system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor 624system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy 625system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy | 623system.cpu.dcache.tags.occ_blocks::cpu.data 110.199847 # Average occupied blocks per requestor 624system.cpu.dcache.tags.occ_percent::cpu.data 0.026904 # Average percentage of cache occupancy 625system.cpu.dcache.tags.occ_percent::total 0.026904 # Average percentage of cache occupancy |
| 626system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 629system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id | 626system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 629system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id |
| 630system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses 631system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses | 630system.cpu.dcache.tags.tag_accesses 6029 # Number of tag accesses 631system.cpu.dcache.tags.data_accesses 6029 # Number of data accesses |
| 632system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states | 632system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 633system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits 634system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits | 633system.cpu.dcache.ReadReq_hits::cpu.data 1883 # number of ReadReq hits 634system.cpu.dcache.ReadReq_hits::total 1883 # number of ReadReq hits |
| 635system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 636system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits | 635system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 636system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits |
| 637system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits 638system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits 639system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits 640system.cpu.dcache.overall_hits::total 2402 # number of overall hits | 637system.cpu.dcache.demand_hits::cpu.data 2391 # number of demand (read+write) hits 638system.cpu.dcache.demand_hits::total 2391 # number of demand (read+write) hits 639system.cpu.dcache.overall_hits::cpu.data 2391 # number of overall hits 640system.cpu.dcache.overall_hits::total 2391 # number of overall hits |
| 641system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 642system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 643system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 644system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 645system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 646system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 647system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 648system.cpu.dcache.overall_misses::total 537 # number of overall misses | 641system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 642system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 643system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 644system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 645system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 646system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 647system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 648system.cpu.dcache.overall_misses::total 537 # number of overall misses |
| 649system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles 650system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles 651system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles 652system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles 653system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles 654system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles 655system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles 656system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles 657system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) 658system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) | 649system.cpu.dcache.ReadReq_miss_latency::cpu.data 13954000 # number of ReadReq miss cycles 650system.cpu.dcache.ReadReq_miss_latency::total 13954000 # number of ReadReq miss cycles 651system.cpu.dcache.WriteReq_miss_latency::cpu.data 31258982 # number of WriteReq miss cycles 652system.cpu.dcache.WriteReq_miss_latency::total 31258982 # number of WriteReq miss cycles 653system.cpu.dcache.demand_miss_latency::cpu.data 45212982 # number of demand (read+write) miss cycles 654system.cpu.dcache.demand_miss_latency::total 45212982 # number of demand (read+write) miss cycles 655system.cpu.dcache.overall_miss_latency::cpu.data 45212982 # number of overall miss cycles 656system.cpu.dcache.overall_miss_latency::total 45212982 # number of overall miss cycles 657system.cpu.dcache.ReadReq_accesses::cpu.data 2063 # number of ReadReq accesses(hits+misses) 658system.cpu.dcache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) |
| 659system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 660system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) | 659system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 660system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) |
| 661system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses 662system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses 663system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses 664system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses 665system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses 666system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses | 661system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses 662system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses 663system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses 664system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses 665system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087252 # miss rate for ReadReq accesses 666system.cpu.dcache.ReadReq_miss_rate::total 0.087252 # miss rate for ReadReq accesses |
| 667system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 668system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses | 667system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 668system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses |
| 669system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses 670system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses 671system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses 672system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses 673system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency 674system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency 677system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency 678system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency 680system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency 681system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked | 669system.cpu.dcache.demand_miss_rate::cpu.data 0.183402 # miss rate for demand accesses 670system.cpu.dcache.demand_miss_rate::total 0.183402 # miss rate for demand accesses 671system.cpu.dcache.overall_miss_rate::cpu.data 0.183402 # miss rate for overall accesses 672system.cpu.dcache.overall_miss_rate::total 0.183402 # miss rate for overall accesses 673system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77522.222222 # average ReadReq miss latency 674system.cpu.dcache.ReadReq_avg_miss_latency::total 77522.222222 # average ReadReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87560.173669 # average WriteReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::total 87560.173669 # average WriteReq miss latency 677system.cpu.dcache.demand_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency 678system.cpu.dcache.demand_avg_miss_latency::total 84195.497207 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency 680system.cpu.dcache.overall_avg_miss_latency::total 84195.497207 # average overall miss latency 681system.cpu.dcache.blocked_cycles::no_mshrs 3108 # number of cycles access was blocked |
| 682system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 683system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked 684system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 682system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 683system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked 684system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 685system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked | 685system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked |
| 686system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 687system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 688system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 689system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 690system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 691system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 692system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 693system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 694system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 695system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 696system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 697system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 698system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 699system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 700system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 701system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 702system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses | 686system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 687system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 688system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 689system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 690system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 691system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 692system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 693system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 694system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 695system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 696system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 697system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 698system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 699system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 700system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 701system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 702system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses |
| 703system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles 705system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles 706system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles 707system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles 708system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles 709system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles 710system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles 711system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses | 703system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9402500 # number of ReadReq MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_miss_latency::total 9402500 # number of ReadReq MSHR miss cycles 705system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7030000 # number of WriteReq MSHR miss cycles 706system.cpu.dcache.WriteReq_mshr_miss_latency::total 7030000 # number of WriteReq MSHR miss cycles 707system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16432500 # number of demand (read+write) MSHR miss cycles 708system.cpu.dcache.demand_mshr_miss_latency::total 16432500 # number of demand (read+write) MSHR miss cycles 709system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16432500 # number of overall MSHR miss cycles 710system.cpu.dcache.overall_mshr_miss_latency::total 16432500 # number of overall MSHR miss cycles 711system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048958 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048958 # mshr miss rate for ReadReq accesses |
| 713system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses | 713system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses |
| 715system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses 716system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses 717system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses 718system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency 720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency 721system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency 722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency 723system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency 724system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency 725system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency 726system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency | 715system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for demand accesses 716system.cpu.dcache.demand_mshr_miss_rate::total 0.059085 # mshr miss rate for demand accesses 717system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for overall accesses 718system.cpu.dcache.overall_mshr_miss_rate::total 0.059085 # mshr miss rate for overall accesses 719system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93094.059406 # average ReadReq mshr miss latency 720system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93094.059406 # average ReadReq mshr miss latency 721system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97638.888889 # average WriteReq mshr miss latency 722system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97638.888889 # average WriteReq mshr miss latency 723system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency 724system.cpu.dcache.demand_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency 725system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency 726system.cpu.dcache.overall_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency |
| 727system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 728system.cpu.icache.tags.replacements 0 # number of replacements | 727system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 728system.cpu.icache.tags.replacements 0 # number of replacements |
| 729system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use 730system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. 731system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 732system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. | 729system.cpu.icache.tags.tagsinuse 160.011089 # Cycle average of tags in use 730system.cpu.icache.tags.total_refs 1840 # Total number of references to valid blocks. 731system.cpu.icache.tags.sampled_refs 312 # Sample count of references to valid blocks. 732system.cpu.icache.tags.avg_refs 5.897436 # Average number of references to valid blocks. |
| 733system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 733system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 734system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor 735system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy 736system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy 737system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id | 734system.cpu.icache.tags.occ_blocks::cpu.inst 160.011089 # Average occupied blocks per requestor 735system.cpu.icache.tags.occ_percent::cpu.inst 0.078130 # Average percentage of cache occupancy 736system.cpu.icache.tags.occ_percent::total 0.078130 # Average percentage of cache occupancy 737system.cpu.icache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id |
| 738system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id | 738system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id |
| 739system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id 740system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id 741system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses 742system.cpu.icache.tags.data_accesses 4903 # Number of data accesses | 739system.cpu.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id 740system.cpu.icache.tags.occ_task_id_percent::1024 0.152344 # Percentage of cache occupancy per task id 741system.cpu.icache.tags.tag_accesses 4908 # Number of tag accesses 742system.cpu.icache.tags.data_accesses 4908 # Number of data accesses |
| 743system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states | 743system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 744system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits 745system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits 746system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits 747system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits 748system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits 749system.cpu.icache.overall_hits::total 1837 # number of overall hits | 744system.cpu.icache.ReadReq_hits::cpu.inst 1840 # number of ReadReq hits 745system.cpu.icache.ReadReq_hits::total 1840 # number of ReadReq hits 746system.cpu.icache.demand_hits::cpu.inst 1840 # number of demand (read+write) hits 747system.cpu.icache.demand_hits::total 1840 # number of demand (read+write) hits 748system.cpu.icache.overall_hits::cpu.inst 1840 # number of overall hits 749system.cpu.icache.overall_hits::total 1840 # number of overall hits |
| 750system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 751system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 752system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 753system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 754system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 755system.cpu.icache.overall_misses::total 458 # number of overall misses | 750system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 751system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 752system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 753system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 754system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 755system.cpu.icache.overall_misses::total 458 # number of overall misses |
| 756system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles 757system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles 758system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles 759system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles 760system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles 761system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles 762system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) 763system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) 764system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses 765system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses 766system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses 767system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses 768system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses 769system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses 770system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses 771system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses 772system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses 773system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses 774system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency 775system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency 776system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency 777system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency 778system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency 779system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency 780system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked | 756system.cpu.icache.ReadReq_miss_latency::cpu.inst 35481000 # number of ReadReq miss cycles 757system.cpu.icache.ReadReq_miss_latency::total 35481000 # number of ReadReq miss cycles 758system.cpu.icache.demand_miss_latency::cpu.inst 35481000 # number of demand (read+write) miss cycles 759system.cpu.icache.demand_miss_latency::total 35481000 # number of demand (read+write) miss cycles 760system.cpu.icache.overall_miss_latency::cpu.inst 35481000 # number of overall miss cycles 761system.cpu.icache.overall_miss_latency::total 35481000 # number of overall miss cycles 762system.cpu.icache.ReadReq_accesses::cpu.inst 2298 # number of ReadReq accesses(hits+misses) 763system.cpu.icache.ReadReq_accesses::total 2298 # number of ReadReq accesses(hits+misses) 764system.cpu.icache.demand_accesses::cpu.inst 2298 # number of demand (read+write) accesses 765system.cpu.icache.demand_accesses::total 2298 # number of demand (read+write) accesses 766system.cpu.icache.overall_accesses::cpu.inst 2298 # number of overall (read+write) accesses 767system.cpu.icache.overall_accesses::total 2298 # number of overall (read+write) accesses 768system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199304 # miss rate for ReadReq accesses 769system.cpu.icache.ReadReq_miss_rate::total 0.199304 # miss rate for ReadReq accesses 770system.cpu.icache.demand_miss_rate::cpu.inst 0.199304 # miss rate for demand accesses 771system.cpu.icache.demand_miss_rate::total 0.199304 # miss rate for demand accesses 772system.cpu.icache.overall_miss_rate::cpu.inst 0.199304 # miss rate for overall accesses 773system.cpu.icache.overall_miss_rate::total 0.199304 # miss rate for overall accesses 774system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77469.432314 # average ReadReq miss latency 775system.cpu.icache.ReadReq_avg_miss_latency::total 77469.432314 # average ReadReq miss latency 776system.cpu.icache.demand_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency 777system.cpu.icache.demand_avg_miss_latency::total 77469.432314 # average overall miss latency 778system.cpu.icache.overall_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency 779system.cpu.icache.overall_avg_miss_latency::total 77469.432314 # average overall miss latency 780system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 781system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 781system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 782system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked | 782system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 783system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 783system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 784system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked | 784system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 785system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 785system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 786system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits 787system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits 788system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits 789system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits 790system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits 791system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits 792system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 793system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 794system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 795system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 796system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 797system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 798system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles 799system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles 800system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles 801system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles 802system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles 803system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles 804system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses 806system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses 807system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses 808system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses 809system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses 810system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency 811system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency 812system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency 813system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency 814system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency 815system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency | 786system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits 787system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits 788system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits 789system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits 790system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits 791system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits 792system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses 793system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses 794system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 795system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses 796system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 797system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses 798system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26195000 # number of ReadReq MSHR miss cycles 799system.cpu.icache.ReadReq_mshr_miss_latency::total 26195000 # number of ReadReq MSHR miss cycles 800system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26195000 # number of demand (read+write) MSHR miss cycles 801system.cpu.icache.demand_mshr_miss_latency::total 26195000 # number of demand (read+write) MSHR miss cycles 802system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26195000 # number of overall MSHR miss cycles 803system.cpu.icache.overall_mshr_miss_latency::total 26195000 # number of overall MSHR miss cycles 804system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135770 # mshr miss rate for ReadReq accesses 806system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for demand accesses 807system.cpu.icache.demand_mshr_miss_rate::total 0.135770 # mshr miss rate for demand accesses 808system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for overall accesses 809system.cpu.icache.overall_mshr_miss_rate::total 0.135770 # mshr miss rate for overall accesses 810system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83958.333333 # average ReadReq mshr miss latency 811system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83958.333333 # average ReadReq mshr miss latency 812system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency 813system.cpu.icache.demand_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency 814system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency 815system.cpu.icache.overall_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency |
| 816system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 817system.cpu.l2cache.tags.replacements 0 # number of replacements | 816system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 817system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 818system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use | 818system.cpu.l2cache.tags.tagsinuse 270.308724 # Cycle average of tags in use |
| 819system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. | 819system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. |
| 820system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 821system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. | 820system.cpu.l2cache.tags.sampled_refs 484 # Sample count of references to valid blocks. 821system.cpu.l2cache.tags.avg_refs 0.002066 # Average number of references to valid blocks. |
| 822system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 822system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 823system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor 824system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor 825system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy | 823system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.032476 # Average occupied blocks per requestor 824system.cpu.l2cache.tags.occ_blocks::cpu.data 110.276248 # Average occupied blocks per requestor 825system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004884 # Average percentage of cache occupancy |
| 826system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy | 826system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy |
| 827system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy 828system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id | 827system.cpu.l2cache.tags.occ_percent::total 0.008249 # Average percentage of cache occupancy 828system.cpu.l2cache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id |
| 829system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id | 829system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id |
| 830system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 831system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id 832system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 833system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses | 830system.cpu.l2cache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 831system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014771 # Percentage of cache occupancy per task id 832system.cpu.l2cache.tags.tag_accesses 4364 # Number of tag accesses 833system.cpu.l2cache.tags.data_accesses 4364 # Number of data accesses |
| 834system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 835system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 836system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 837system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 838system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 839system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 840system.cpu.l2cache.overall_hits::total 1 # number of overall hits 841system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 842system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses | 834system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 835system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 836system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 837system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 838system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 839system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 840system.cpu.l2cache.overall_hits::total 1 # number of overall hits 841system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 842system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses |
| 843system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses 844system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses | 843system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 311 # number of ReadCleanReq misses 844system.cpu.l2cache.ReadCleanReq_misses::total 311 # number of ReadCleanReq misses |
| 845system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 846system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses | 845system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 846system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses |
| 847system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses | 847system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses |
| 848system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses | 848system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses |
| 849system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses | 849system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses |
| 851system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses | 851system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses |
| 852system.cpu.l2cache.overall_misses::total 485 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles | 852system.cpu.l2cache.overall_misses::total 484 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6919000 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 6919000 # number of ReadExReq miss cycles 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25713500 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 25713500 # number of ReadCleanReq miss cycles 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9242500 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 9242500 # number of ReadSharedReq miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.inst 25713500 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.data 16161500 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::total 41875000 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 25713500 # number of overall miss cycles 863system.cpu.l2cache.overall_miss_latency::cpu.data 16161500 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::total 41875000 # number of overall miss cycles |
| 865system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 866system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) | 865system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 866system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) |
| 867system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) 868system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) | 867system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 312 # number of ReadCleanReq accesses(hits+misses) 868system.cpu.l2cache.ReadCleanReq_accesses::total 312 # number of ReadCleanReq accesses(hits+misses) |
| 869system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 870system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) | 869system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 870system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) |
| 871system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses | 871system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses |
| 872system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses | 872system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses |
| 873system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 874system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses | 873system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses 874system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses |
| 875system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses | 875system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses |
| 876system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses | 876system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses |
| 877system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 877system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 878system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 879system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses 880system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses | 879system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadCleanReq accesses 880system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996795 # miss rate for ReadCleanReq accesses |
| 881system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 882system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 881system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 882system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 883system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses | 883system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses |
| 884system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 884system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 885system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 886system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses | 885system.cpu.l2cache.demand_miss_rate::total 0.997938 # miss rate for demand accesses 886system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses |
| 887system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 887system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 888system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses 889system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency 890system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency 891system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency 892system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency 893system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency 894system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency | 888system.cpu.l2cache.overall_miss_rate::total 0.997938 # miss rate for overall accesses 889system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96097.222222 # average ReadExReq miss latency 890system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96097.222222 # average ReadExReq miss latency 891system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82680.064309 # average ReadCleanReq miss latency 892system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82680.064309 # average ReadCleanReq miss latency 893system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91509.900990 # average ReadSharedReq miss latency 894system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91509.900990 # average ReadSharedReq miss latency 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency 897system.cpu.l2cache.demand_avg_miss_latency::total 86518.595041 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency 900system.cpu.l2cache.overall_avg_miss_latency::total 86518.595041 # average overall miss latency |
| 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses | 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses |
| 909system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 910system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses | 909system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 311 # number of ReadCleanReq MSHR misses 910system.cpu.l2cache.ReadCleanReq_mshr_misses::total 311 # number of ReadCleanReq MSHR misses |
| 911system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 912system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses | 911system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 912system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses |
| 913system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses | 913system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses |
| 914system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses | 914system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses |
| 915system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses | 915system.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses |
| 917system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses | 917system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses |
| 918system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses 919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles 920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles 921system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles 922system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles 923system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles 924system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles 925system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles 926system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles 929system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles | 918system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses 919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6199000 # number of ReadExReq MSHR miss cycles 920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6199000 # number of ReadExReq MSHR miss cycles 921system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22603500 # number of ReadCleanReq MSHR miss cycles 922system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22603500 # number of ReadCleanReq MSHR miss cycles 923system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8232500 # number of ReadSharedReq MSHR miss cycles 924system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8232500 # number of ReadSharedReq MSHR miss cycles 925system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22603500 # number of demand (read+write) MSHR miss cycles 926system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14431500 # number of demand (read+write) MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::total 37035000 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22603500 # number of overall MSHR miss cycles 929system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14431500 # number of overall MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::total 37035000 # number of overall MSHR miss cycles |
| 931system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 932system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 931system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 932system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 933system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 934system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses | 933system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadCleanReq accesses 934system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996795 # mshr miss rate for ReadCleanReq accesses |
| 935system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 936system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 935system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 936system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 937system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses | 937system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses |
| 938system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 938system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 939system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 940system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses | 939system.cpu.l2cache.demand_mshr_miss_rate::total 0.997938 # mshr miss rate for demand accesses 940system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses |
| 941system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 941system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 942system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency 944system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency 945system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency 946system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency 947system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency 948system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency 950system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency 951system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency 953system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency 954system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency 955system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. | 942system.cpu.l2cache.overall_mshr_miss_rate::total 0.997938 # mshr miss rate for overall accesses 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86097.222222 # average ReadExReq mshr miss latency 944system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86097.222222 # average ReadExReq mshr miss latency 945system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72680.064309 # average ReadCleanReq mshr miss latency 946system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72680.064309 # average ReadCleanReq mshr miss latency 947system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81509.900990 # average ReadSharedReq mshr miss latency 948system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81509.900990 # average ReadSharedReq mshr miss latency 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency 950system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency 951system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency 953system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency 954system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency 955system.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. |
| 956system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 957system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 958system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 959system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 960system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 961system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states | 956system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 957system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 958system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 959system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 960system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 961system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 962system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution | 962system.cpu.toL2Bus.trans_dist::ReadResp 413 # Transaction distribution |
| 963system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution | 963system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 964system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution |
| 965system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution | 965system.cpu.toL2Bus.trans_dist::ReadCleanReq 312 # Transaction distribution |
| 966system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution | 966system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution |
| 967system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) | 967system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) |
| 968system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) | 968system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) |
| 969system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) 970system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) | 969system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 970system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19968 # Cumulative packet size per connected master and slave (bytes) |
| 971system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) | 971system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) |
| 972system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) | 972system.cpu.toL2Bus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) |
| 973system.cpu.toL2Bus.snoops 0 # Total snoops (count) 974system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 973system.cpu.toL2Bus.snoops 0 # Total snoops (count) 974system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 975system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram | 975system.cpu.toL2Bus.snoop_fanout::samples 485 # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::mean 0.002062 # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram |
| 978system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 978system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 979system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram | 979system.cpu.toL2Bus.snoop_fanout::0 484 99.79% 99.79% # Request fanout histogram |
| 980system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 984system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 980system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 982system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 983system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 984system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 985system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 986system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) | 985system.cpu.toL2Bus.snoop_fanout::total 485 # Request fanout histogram 986system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) |
| 987system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) | 987system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 988system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) | 988system.cpu.toL2Bus.respLayer0.occupancy 468000 # Layer occupancy (ticks) |
| 989system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 990system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 991system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) | 989system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 990system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 991system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 992system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. | 992system.membus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. |
| 993system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 994system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 995system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 996system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 997system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 998system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states | 993system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 994system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 995system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 996system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 997system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 998system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states |
| 999system.membus.trans_dist::ReadResp 413 # Transaction distribution | 999system.membus.trans_dist::ReadResp 412 # Transaction distribution |
| 1000system.membus.trans_dist::ReadExReq 72 # Transaction distribution 1001system.membus.trans_dist::ReadExResp 72 # Transaction distribution | 1000system.membus.trans_dist::ReadExReq 72 # Transaction distribution 1001system.membus.trans_dist::ReadExResp 72 # Transaction distribution |
| 1002system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 1003system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 1004system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 1005system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 1006system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) | 1002system.membus.trans_dist::ReadSharedReq 412 # Transaction distribution 1003system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 968 # Packet count per connected master and slave (bytes) 1004system.membus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 1005system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30976 # Cumulative packet size per connected master and slave (bytes) 1006system.membus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) |
| 1007system.membus.snoops 0 # Total snoops (count) 1008system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1007system.membus.snoops 0 # Total snoops (count) 1008system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1009system.membus.snoop_fanout::samples 485 # Request fanout histogram | 1009system.membus.snoop_fanout::samples 484 # Request fanout histogram |
| 1010system.membus.snoop_fanout::mean 0 # Request fanout histogram 1011system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1012system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1010system.membus.snoop_fanout::mean 0 # Request fanout histogram 1011system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1012system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1013system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram | 1013system.membus.snoop_fanout::0 484 100.00% 100.00% # Request fanout histogram |
| 1014system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1015system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1016system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1017system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1014system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1015system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1016system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1017system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1018system.membus.snoop_fanout::total 485 # Request fanout histogram 1019system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) | 1018system.membus.snoop_fanout::total 484 # Request fanout histogram 1019system.membus.reqLayer0.occupancy 593000 # Layer occupancy (ticks) |
| 1020system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) | 1020system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) |
| 1021system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) | 1021system.membus.respLayer1.occupancy 2566000 # Layer occupancy (ticks) |
| 1022system.membus.respLayer1.utilization 10.8 # Layer utilization (%) 1023 1024---------- End Simulation Statistics ---------- | 1022system.membus.respLayer1.utilization 10.8 # Layer utilization (%) 1023 1024---------- End Simulation Statistics ---------- |