| stats.txt (11687:b3d5f0e9e258) | stats.txt (11731:c473ca7cc650) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23776000 # Number of ticks simulated 5final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23776000 # Number of ticks simulated 5final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 139405 # Simulator instruction rate (inst/s) 8host_op_rate 139373 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 518883929 # Simulator tick rate (ticks/s) 10host_mem_usage 254032 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 4743 # Simulator instruction rate (inst/s) 8host_op_rate 4743 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17659718 # Simulator tick rate (ticks/s) 10host_mem_usage 236044 # Number of bytes of host memory used 11host_seconds 1.35 # Real time elapsed on the host |
| 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation | 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation |
| 204system.physmem.totQLat 8009750 # Total ticks spent queuing 205system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 8008750 # Total ticks spent queuing 205system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst |
| 210system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 10.20 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 48208.25 # Average gap between requests 225system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 210system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 10.20 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 48208.25 # Average gap between requests 225system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) | 231system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) | 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) | 233system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ) |
| 234system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) 237system.physmem_0.averagePower 621.784975 # Core power per rank (mW) | 234system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) 237system.physmem_0.averagePower 621.784975 # Core power per rank (mW) |
| 238system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank | 238system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states |
| 243system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states | 243system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states |
| 245system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) --- 55 unchanged lines hidden (view full) --- 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 47553 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 245system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) --- 55 unchanged lines hidden (view full) --- 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 47553 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 316system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss | 316system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss |
| 317system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing 322system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps 324system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed | 317system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing 322system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps 324system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed |
| 326system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) | 326system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total) |
| 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 330system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) | 330system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total) |
| 331system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 331system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 342system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) | 342system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total) |
| 343system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle | 343system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle |
| 345system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle | 345system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle |
| 346system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing | 346system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing |
| 355system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle | 355system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle |
| 356system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 2476 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full --- 13 unchanged lines hidden (view full) --- 377system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 378system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) 379system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 380system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued 381system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 382system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph 384system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed | 356system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 2476 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full --- 13 unchanged lines hidden (view full) --- 377system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 378system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) 379system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 380system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued 381system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 382system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph 384system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed |
| 385system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle | 385system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle |
| 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 389system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle | 389system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle |
| 391system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle | 391system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle |
| 394system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle | 394system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle |
| 395system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 395system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 401system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle | 401system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle |
| 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available --- 64 unchanged lines hidden (view full) --- 474system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::total 10776 # Type of FU issued 479system.cpu.iq.rate 0.226610 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 141 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) | 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available --- 64 unchanged lines hidden (view full) --- 474system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued 475system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued 476system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 477system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::total 10776 # Type of FU issued 479system.cpu.iq.rate 0.226610 # Inst issue rate 480system.cpu.iq.fu_busy_cnt 141 # FU busy when requested 481system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) |
| 482system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads | 482system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads |
| 483system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores --- 34 unchanged lines hidden (view full) --- 525system.cpu.iew.wb_count 9755 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 5155 # num instructions producing a value 527system.cpu.iew.wb_consumers 7025 # num instructions consuming a value 528system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle 529system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back 530system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit 531system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 532system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted | 483system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes 484system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses 485system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 486system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 487system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 488system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses 489system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 490system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores --- 34 unchanged lines hidden (view full) --- 525system.cpu.iew.wb_count 9755 # cumulative count of insts written-back 526system.cpu.iew.wb_producers 5155 # num instructions producing a value 527system.cpu.iew.wb_consumers 7025 # num instructions consuming a value 528system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle 529system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back 530system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit 531system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 532system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted |
| 533system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle | 533system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle |
| 536system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 536system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 537system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle | 537system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle |
| 538system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 538system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 549system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle | 549system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle |
| 550system.cpu.commit.committedInsts 6402 # Number of instructions committed 551system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 552system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 553system.cpu.commit.refs 2050 # Number of memory references committed 554system.cpu.commit.loads 1185 # Number of loads committed 555system.cpu.commit.membars 0 # Number of memory barriers committed 556system.cpu.commit.branches 1056 # Number of branches committed 557system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 34 unchanged lines hidden (view full) --- 592system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction 593system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 598system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 599system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached | 550system.cpu.commit.committedInsts 6402 # Number of instructions committed 551system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 552system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 553system.cpu.commit.refs 2050 # Number of memory references committed 554system.cpu.commit.loads 1185 # Number of loads committed 555system.cpu.commit.membars 0 # Number of memory barriers committed 556system.cpu.commit.branches 1056 # Number of branches committed 557system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. --- 34 unchanged lines hidden (view full) --- 592system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction 593system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction 594system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 595system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 598system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 599system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached |
| 600system.cpu.rob.rob_reads 26790 # The number of ROB reads | 600system.cpu.rob.rob_reads 26792 # The number of ROB reads |
| 601system.cpu.rob.rob_writes 27482 # The number of ROB writes 602system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself | 601system.cpu.rob.rob_writes 27482 # The number of ROB writes 602system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 603system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling | 603system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 604system.cpu.committedInsts 6385 # Number of Instructions Simulated 605system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 606system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 607system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 608system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 609system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads 610system.cpu.int_regfile_reads 12923 # number of integer regfile reads 611system.cpu.int_regfile_writes 7437 # number of integer regfile writes --- 136 unchanged lines hidden (view full) --- 748system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits 749system.cpu.icache.overall_hits::total 1837 # number of overall hits 750system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 751system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 752system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 753system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 754system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 755system.cpu.icache.overall_misses::total 458 # number of overall misses | 604system.cpu.committedInsts 6385 # Number of Instructions Simulated 605system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 606system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 607system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 608system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 609system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads 610system.cpu.int_regfile_reads 12923 # number of integer regfile reads 611system.cpu.int_regfile_writes 7437 # number of integer regfile writes --- 136 unchanged lines hidden (view full) --- 748system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits 749system.cpu.icache.overall_hits::total 1837 # number of overall hits 750system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 751system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 752system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 753system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 754system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 755system.cpu.icache.overall_misses::total 458 # number of overall misses |
| 756system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles 757system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles 758system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles 759system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles 760system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles 761system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles | 756system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles 757system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles 758system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles 759system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles 760system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles 761system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles |
| 762system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) 763system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) 764system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses 765system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses 766system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses 767system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses 768system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses 769system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses 770system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses 771system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses 772system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses 773system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses | 762system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) 763system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) 764system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses 765system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses 766system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses 767system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses 768system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses 769system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses 770system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses 771system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses 772system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses 773system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses |
| 774system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency 775system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency 776system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency 777system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency 778system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency 779system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency | 774system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency 775system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency 776system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency 777system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency 778system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency 779system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency |
| 780system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked 781system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 783system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked 785system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits 787system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits 788system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits 789system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits 790system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits 791system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits 792system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 793system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 794system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 795system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 796system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 797system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses | 780system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked 781system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 783system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked 785system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits 787system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits 788system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits 789system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits 790system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits 791system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits 792system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 793system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 794system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 795system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 796system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 797system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses |
| 798system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles 799system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles 800system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles 801system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles 802system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles 803system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles | 798system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles 799system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles 800system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles 801system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles 802system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles 803system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles |
| 804system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses 806system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses 807system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses 808system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses 809system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses | 804system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses 805system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses 806system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses 807system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses 808system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses 809system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses |
| 810system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency 811system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency 812system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency 813system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency 814system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency 815system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency | 810system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency 811system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency 812system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency 813system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency 814system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency 815system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency |
| 816system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 817system.cpu.l2cache.tags.replacements 0 # number of replacements 818system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use 819system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 820system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 821system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. 822system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 823system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor --- 23 unchanged lines hidden (view full) --- 847system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 849system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 851system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 852system.cpu.l2cache.overall_misses::total 485 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles | 816system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 817system.cpu.l2cache.tags.replacements 0 # number of replacements 818system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use 819system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 820system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 821system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. 822system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 823system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor --- 23 unchanged lines hidden (view full) --- 847system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 848system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 849system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 850system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 851system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 852system.cpu.l2cache.overall_misses::total 485 # number of overall misses 853system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles |
| 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles | 855system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles 856system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles |
| 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles | 857system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles 858system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles |
| 859system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles | 859system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles |
| 860system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles | 860system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles |
| 861system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles | 861system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles |
| 863system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles | 863system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles |
| 864system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles | 864system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles |
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| 891system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency 892system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency | 891system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency 892system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency |
| 893system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency 894system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency | 893system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency 894system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency |
| 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency | 895system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency |
| 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency | 896system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency |
| 897system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency | 897system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency 898system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency |
| 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency | 899system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency |
| 900system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency | 900system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency |
| 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 913system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 914system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 915system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 917system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 918system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses 919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles 920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles | 901system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 908system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 913system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 914system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 915system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 917system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 918system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses 919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles 920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles |
| 921system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles 922system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles | 921system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles 922system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles |
| 923system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles 924system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles | 923system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles 924system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles |
| 925system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles | 925system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles |
| 926system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles | 926system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles |
| 927system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles | 927system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles |
| 929system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles | 929system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles |
| 930system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles | 930system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles |
| 931system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 932system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 933system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 934system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses 935system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 936system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 937system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 938system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 939system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 940system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 941system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 942system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency 944system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency | 931system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 932system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 933system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 934system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses 935system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 936system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 937system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 938system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 939system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 940system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 941system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 942system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 943system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency 944system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency |
| 945system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency 946system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency | 945system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency 946system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency |
| 947system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency 948system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency | 947system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency 948system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency |
| 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency | 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency |
| 950system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency | 950system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency |
| 951system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency | 951system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency |
| 953system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency | 953system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency |
| 954system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency | 954system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency |
| 955system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 956system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 957system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 958system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 959system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 960system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 961system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 962system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution --- 62 unchanged lines hidden --- | 955system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 956system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 957system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 958system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 959system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 960system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 961system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 962system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution --- 62 unchanged lines hidden --- |